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cleanup rom usage
[fpga-games] / galaxian / src / mc_top.v
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1//===============================================================================\r
2// FPGA GALAXIAN TOP\r
3//\r
4// Version : 2.50\r
5//\r
6// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
7//\r
8// Important !\r
9//\r
10// This program is freeware for non-commercial use. \r
11// An author does no guarantee about this program.\r
12// You can use this under your own risk.\r
13//\r
14// 2004- 4-30 galaxian modify by K.DEGAWA\r
15// 2004- 5- 6 first release.\r
16// 2004- 8-23 Improvement with T80-IP.\r
17// 2004- 9-18 The description of ALTERA(CYCLONE) and XILINX(SPARTAN2E) was made one.\r
18// 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r
19//================================================================================\r
20\r
21`include "src/mc_conf.v" \r
22 \r
23module mc_top(\r
24\r
25// FPGA_USE\r
26I_CLK_125M,\r
27\r
28`ifdef PSPAD_USE\r
29// PS_PAD interface\r
30psCLK,\r
31psSEL,\r
32psTXD,\r
33psRXD,\r
34`endif\r
35\r
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36// INPORT SW IF\r
37I_PSW,\r
38\r
39// SOUND OUT\r
40O_SOUND_OUT_L,\r
41O_SOUND_OUT_R,\r
42\r
43// VGA (VIDEO) IF\r
44O_VGA_R,\r
45O_VGA_G,\r
46O_VGA_B,\r
47O_VGA_H_SYNCn,\r
48O_VGA_V_SYNCn\r
49\r
50);\r
51\r
52// FPGA_USE\r
53input I_CLK_125M;\r
54\r
55// CPU ADDRESS BUS\r
56wire [15:0]W_A;\r
57// CPU IF\r
58wire W_CPU_RDn;\r
59wire W_CPU_WRn;\r
60wire W_CPU_MREQn;\r
61wire W_CPU_RFSHn;\r
62wire W_CPU_BUSAKn;\r
63wire W_CPU_IORQn;\r
64wire W_CPU_M1n;\r
65wire W_CPU_CLK;\r
66wire W_CPU_HRDWR_RESETn;\r
67wire W_CPU_WAITn;\r
68wire W_CPU_NMIn;\r
69\r
70`ifdef PSPAD_USE\r
71// PS_PAD interface\r
72input psRXD;\r
73output psTXD,psCLK,psSEL;\r
74`endif\r
75\r
782690d0 76// INPORT SW IF\r
3fc34adf 77input [8:0]I_PSW;\r
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78\r
79// SOUND OUT \r
80output O_SOUND_OUT_L;\r
81output O_SOUND_OUT_R;\r
82\r
83// VGA (VIDEO) IF\r
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84output [3:0]O_VGA_R;\r
85output [3:0]O_VGA_G;\r
86output [3:0]O_VGA_B;\r
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87output O_VGA_H_SYNCn;\r
88output O_VGA_V_SYNCn;\r
89\r
3fc34adf 90wire W_RESETn = |(~I_PSW[8:5]);\r
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91//------ CLOCK GEN ---------------------------\r
92wire I_CLK_18432M;\r
93wire W_CLK_12M,WB_CLK_12M;\r
94wire W_CLK_6M,WB_CLK_6M;\r
95wire W_STARS_CLK;\r
96\r
b884ab49 97mc_dcm clockgen(\r
782690d0 98.CLKIN_IN(I_CLK_125M),\r
fc28fcbf 99.RST_IN(! W_RESETn),\r
36a47d3c 100.CLKFX_OUT(I_CLK_18432M)\r
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101);\r
102\r
103//------ H&V COUNTER -------------------------\r
104wire [8:0]W_H_CNT;\r
105wire [7:0]W_V_CNT;\r
106wire W_H_BL;\r
107wire W_V_BLn;\r
108wire W_C_BLn;\r
109wire W_H_SYNC;\r
110wire W_V_SYNC;\r
111\r
112//------ CPU RAM ----------------------------\r
113wire [7:0]W_CPU_RAM_DO;\r
114\r
115//------ ADDRESS DECDER ----------------------\r
116wire W_CPU_ROM_CSn;\r
117wire W_CPU_RAM_RDn;\r
118wire W_CPU_RAM_WRn;\r
119wire W_CPU_RAM_CSn;\r
120wire W_OBJ_RAM_RDn;\r
121wire W_OBJ_RAM_WRn;\r
122wire W_OBJ_RAM_RQn;\r
123wire W_VID_RAM_RDn;\r
124wire W_VID_RAM_WRn;\r
125wire W_SW0_OEn;\r
126wire W_SW1_OEn;\r
127wire W_DIP_OEn;\r
128wire W_WDR_OEn;\r
129wire W_LAMP_WEn;\r
130wire W_SOUND_WEn;\r
131wire W_PITCHn;\r
132wire W_H_FLIP;\r
133wire W_V_FLIP;\r
134wire W_BD_G;\r
135wire W_STARS_ON;\r
136\r
137wire W_VID_RDn = W_OBJ_RAM_RDn & W_VID_RAM_RDn ;\r
138wire W_SW_OEn = W_SW0_OEn & W_SW1_OEn & W_DIP_OEn ;\r
139//------- INPORT -----------------------------\r
140wire [7:0]W_SW_DO;\r
141//------- VIDEO -----------------------------\r
142wire [7:0]W_VID_DO;\r
143//--------------------------------------------\r
144\r
145mc_clock MC_CLK(\r
146\r
147.I_CLK_18M(I_CLK_18432M),\r
148.O_CLK_12M(WB_CLK_12M),\r
149.O_CLK_06M(WB_CLK_6M)\r
150\r
151);\r
152\r
153`ifdef DEVICE_CYCLONE\r
154assign W_CLK_12M = WB_CLK_12M;\r
155assign W_CLK_6M = WB_CLK_6M;\r
156`endif\r
157`ifdef DEVICE_SPARTAN2E\r
158BUFG BUFG_12MHz( .I(WB_CLK_12M),.O(W_CLK_12M) );\r
159BUFG BUFG_6MHz ( .I(WB_CLK_6M ),.O(W_CLK_6M ) );\r
160`endif\r
161//--- DATA I/F -------------------------------------\r
162reg [7:0]W_CPU_ROM_DO;\r
163wire [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;\r
164\r
165wire [7:0]W_BDO = W_SW_DO | W_VID_DO | W_CPU_RAM_DO | W_CPU_ROM_DOB ;\r
166wire [7:0]W_BDI;\r
167\r
168//--- CPU I/F -------------------------------------\r
169reg [3:0]rst_count;\r
170always@(posedge W_H_CNT[0] or negedge W_RESETn)\r
171begin\r
172 if(! W_RESETn) rst_count <= 0;\r
173 else begin\r
174 if( rst_count == 15) \r
175 rst_count <= rst_count;\r
176 else\r
177 rst_count <= rst_count+1;\r
178 end\r
179end\r
180\r
181assign W_CPU_RESETn = W_RESETn;\r
182assign W_CPU_CLK = W_H_CNT[0];\r
183\r
184Z80IP CPU(\r
185 \r
186.CLK(W_CPU_CLK),\r
187.RESET_N(W_CPU_RESETn),\r
188.INT_N(1'b1),\r
189.NMI_N(W_CPU_NMIn),\r
190.ADRS(W_A),\r
191.DOUT(W_BDI),\r
192.DINP(W_BDO),\r
193.M1_N(),\r
194.MREQ_N(W_CPU_MREQn),\r
195.IORQ_N(),\r
196.RD_N(W_CPU_RDn ),\r
197.WR_N(W_CPU_WRn ),\r
198.WAIT_N(W_CPU_WAITn),\r
199.BUSWO(),\r
200.RFSH_N(W_CPU_RFSHn),\r
201.HALT_N()\r
202\r
203);\r
204\r
205wire W_CPU_RAM_CLK = W_CLK_12M & ~W_CPU_RAM_CSn;\r
206\r
207mc_cpu_ram MC_CPU_RAM(\r
208\r
209.I_CLK(W_CPU_RAM_CLK),\r
210.I_ADDR(W_A[9:0]),\r
211.I_D(W_BDI),\r
212.I_WE(~W_CPU_WRn),\r
213.I_OE(~W_CPU_RAM_RDn ),\r
214.O_D(W_CPU_RAM_DO)\r
215\r
216);\r
217\r
218\r
219mc_adec MC_ADEC(\r
220\r
221.I_CLK_12M(W_CLK_12M),\r
222.I_CLK_6M(W_CLK_6M),\r
223.I_CPU_CLK(W_H_CNT[0]),\r
224.I_RSTn(W_RESETn),\r
225\r
226.I_CPU_A(W_A),\r
227.I_CPU_D(W_BDI[0]),\r
228.I_MREQn(W_CPU_MREQn),\r
229.I_RFSHn(W_CPU_RFSHn),\r
230.I_RDn(W_CPU_RDn),\r
231.I_WRn(W_CPU_WRn),\r
232.I_H_BL(W_H_BL),\r
233.I_V_BLn(W_V_BLn),\r
234\r
235.O_WAITn(W_CPU_WAITn),\r
236.O_NMIn(W_CPU_NMIn),\r
237.O_CPU_ROM_CSn(W_CPU_ROM_CSn),\r
238.O_CPU_RAM_RDn(W_CPU_RAM_RDn),\r
239.O_CPU_RAM_WRn(W_CPU_RAM_WRn),\r
240.O_CPU_RAM_CSn(W_CPU_RAM_CSn),\r
241.O_OBJ_RAM_RDn(W_OBJ_RAM_RDn),\r
242.O_OBJ_RAM_WRn(W_OBJ_RAM_WRn),\r
243.O_OBJ_RAM_RQn(W_OBJ_RAM_RQn),\r
244.O_VID_RAM_RDn(W_VID_RAM_RDn),\r
245.O_VID_RAM_WRn(W_VID_RAM_WRn),\r
246.O_SW0_OEn(W_SW0_OEn),\r
247.O_SW1_OEn(W_SW1_OEn),\r
248.O_DIP_OEn(W_DIP_OEn),\r
249.O_WDR_OEn(W_WDR_OEn),\r
250.O_LAMP_WEn(W_LAMP_WEn),\r
251.O_SOUND_WEn(W_SOUND_WEn),\r
252.O_PITCHn(W_PITCHn),\r
253.O_H_FLIP(W_H_FLIP),\r
254.O_V_FLIP(W_V_FLIP),\r
255.O_BD_G(W_BD_G),\r
256.O_STARS_ON(W_STARS_ON)\r
257\r
258);\r
259\r
260//-------- SOUND I/F -----------------------------\r
261//--- Parts 9L ---------\r
262reg [7:0]W_9L_Q;\r
263always@(posedge W_CLK_12M or negedge W_RESETn)\r
264begin\r
265 if(W_RESETn == 1'b0)begin\r
266 W_9L_Q <= 0;\r
267 end \r
268 else begin\r
269 if(W_SOUND_WEn == 1'b0)begin\r
270 case(W_A[2:0])\r
271 3'h0 : W_9L_Q[0] <= W_BDI[0];\r
272 3'h1 : W_9L_Q[1] <= W_BDI[0];\r
273 3'h2 : W_9L_Q[2] <= W_BDI[0];\r
274 3'h3 : W_9L_Q[3] <= W_BDI[0];\r
275 3'h4 : W_9L_Q[4] <= W_BDI[0];\r
276 3'h5 : W_9L_Q[5] <= W_BDI[0];\r
277 3'h6 : W_9L_Q[6] <= W_BDI[0];\r
278 3'h7 : W_9L_Q[7] <= W_BDI[0];\r
279 endcase\r
280 end\r
281 end\r
282end\r
283wire W_VOL1 = W_9L_Q[6];\r
284wire W_VOL2 = W_9L_Q[7];\r
285wire W_FIRE = W_9L_Q[5];\r
286wire W_HIT = W_9L_Q[3];\r
287wire W_FS3 = W_9L_Q[2];\r
288wire W_FS2 = W_9L_Q[1];\r
289wire W_FS1 = W_9L_Q[0];\r
290//---------------------------------------------------\r
291//---- CPU DATA WATCH -------------------------------\r
292wire ZMWR = W_CPU_MREQn | W_CPU_WRn ;\r
293\r
294reg [1:0]on_game;\r
295always @(posedge W_CPU_CLK)\r
296begin\r
297 if(~ZMWR)begin\r
298 if(W_A == 16'h4007)begin\r
299 if(W_BDI == 8'h00) \r
300 on_game[0] <= 1;\r
301 else\r
302 on_game[0] <= 0;\r
303 end\r
304 if(W_A == 16'h4005)begin\r
305 if(W_BDI == 8'h03 || W_BDI == 8'h04 ) \r
306 on_game[1] <= 1;\r
307 else\r
308 on_game[1] <= 0;\r
309 end\r
310 end \r
311end\r
312\r
313`ifdef PSPAD_USE\r
314reg died;\r
315always @(posedge W_CPU_CLK)\r
316begin\r
317 if(~ZMWR)begin\r
318 if(W_A == 16'h4206)begin\r
319 if(W_BDI == 8'h00) \r
320 died <= 0;\r
321 else\r
322 died <= 1;\r
323 end\r
324 end\r
325end\r
326//---- PS_PAD Interface -----------------------------\r
327wire [8:0]ps_PSW;\r
328wire VIB_SW = died & (&on_game[1:0]);\r
329\r
330fpga_arcade_if pspad(\r
331\r
332.CLK_18M432(I_CLK_18432M),\r
333.I_RSTn(W_RESETn),\r
334.psCLK(psCLK),\r
335.psSEL(psSEL),\r
336.psTXD(psTXD),\r
337.psRXD(psRXD),\r
338.ps_PSW(ps_PSW),\r
339.I_VIB_SW(VIB_SW)\r
340\r
341);\r
342`endif\r
343//---- SW Interface ---------------------------------\r
344`ifdef PSPAD_USE\r
345wire L1 = I_PSW[2] & ps_PSW[2];\r
346wire R1 = I_PSW[3] & ps_PSW[3];\r
347wire U1 = I_PSW[0];\r
348wire D1 = I_PSW[1];\r
349wire J1 = I_PSW[4] & ps_PSW[8];\r
350\r
351wire S1 = (U1|J1) & ps_PSW[6];\r
352wire S2 = (D1|J1) & ps_PSW[7];\r
353\r
354wire C1 = (L1|R1|U1|~D1) & ps_PSW[4];\r
355`else\r
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356wire L1 = ! I_PSW[2];\r
357wire R1 = ! I_PSW[3];\r
358wire U1 = ! I_PSW[0];\r
359wire D1 = ! I_PSW[1];\r
360wire J1 = ! I_PSW[4];\r
782690d0 361\r
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362wire S1 = ! I_PSW[5];\r
363wire S2 = ! I_PSW[7];\r
782690d0 364\r
3fc34adf 365wire C1 = ! I_PSW[6];\r
782690d0 366`endif\r
3fc34adf 367wire C2 = ! I_PSW[8];\r
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368\r
369wire L2 = L1;\r
370wire R2 = R1;\r
371wire U2 = U1;\r
372wire D2 = D1;\r
373wire J2 = J1;\r
374\r
375mc_inport MC_INPORT(\r
376\r
377.I_COIN1(~C1), // ACTIVE HI\r
378.I_COIN2(~C2), // ACTIVE HI\r
379.I_1P_LE(~L1), // ACTIVE HI\r
380.I_1P_RI(~R1), // ACTIVE HI\r
381.I_1P_SH(~J1), // ACTIVE HI\r
382.I_2P_LE(~L2), // ACTIVE HI\r
383.I_2P_RI(~R2), // ACTIVE HI\r
384.I_2P_SH(~J2), // ACTIVE HI\r
385.I_1P_START(~S1), // ACTIVE HI\r
386.I_2P_START(~S2), // ACTIVE HI\r
387\r
388.I_SW0_OEn(W_SW0_OEn),\r
389.I_SW1_OEn(W_SW1_OEn),\r
390.I_DIP_OEn(W_DIP_OEn),\r
391\r
392.O_D(W_SW_DO)\r
393\r
394);\r
395\r
396//-----------------------------------------------------------------------------\r
397//------- ROM -------------------------------------------------------\r
398reg [18:0]ROM_A;\r
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399\r
400wire [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;\r
401reg [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;\r
402\r
36a47d3c 403wire [7:0]ROM_D;\r
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404\r
405galaxian_roms ROMS(\r
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406.I_ROM_CLK(W_CLK_12M),\r
407.I_ADDR({3'h0,W_A[15:0]}),\r
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408.O_DATA(ROM_D)\r
409);\r
410\r
36a47d3c 411always@(posedge W_CLK_12M)\r
782690d0 412begin\r
36a47d3c 413 W_CPU_ROM_DO <= ROM_D;\r
782690d0 414end\r
36a47d3c 415\r
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416//-----------------------------------------------------------------------------\r
417\r
418wire W_V_BL2n;\r
419\r
420mc_hv_count MC_HV(\r
421\r
422.I_CLK(WB_CLK_6M),\r
423.I_RSTn(W_RESETn),\r
424\r
425.O_H_CNT(W_H_CNT),\r
426.O_H_SYNC(W_H_SYNC),\r
427.O_H_BL(W_H_BL),\r
428.O_V_CNT(W_V_CNT),\r
429.O_V_SYNC(W_V_SYNC),\r
430.O_V_BL2n(W_V_BL2n),\r
431.O_V_BLn(W_V_BLn),\r
432.O_C_BLn(W_C_BLn)\r
433\r
434);\r
435\r
436//------ VIDEO -----------------------------\r
437wire W_8HF;\r
438wire W_1VF;\r
439wire W_C_BLnX;\r
440wire W_256HnX;\r
441wire W_MISSILEn;\r
442wire W_SHELLn;\r
443wire [1:0]W_VID;\r
444wire [2:0]W_COL;\r
445\r
446mc_video MC_VID(\r
447.I_CLK_18M(I_CLK_18432M),\r
448.I_CLK_12M(W_CLK_12M),\r
449.I_CLK_6M(W_CLK_6M),\r
450.I_H_CNT(W_H_CNT),\r
451.I_V_CNT(W_V_CNT),\r
452.I_H_FLIP(W_H_FLIP),\r
453.I_V_FLIP(W_V_FLIP),\r
454.I_V_BLn(W_V_BLn),\r
455.I_C_BLn(W_C_BLn),\r
456\r
457.I_A(W_A[9:0]),\r
458.I_OBJ_SUB_A(3'b000),\r
459.I_BD(W_BDI),\r
460.I_OBJ_RAM_RQn(W_OBJ_RAM_RQn),\r
461.I_OBJ_RAM_RDn(W_OBJ_RAM_RDn),\r
462.I_OBJ_RAM_WRn(W_OBJ_RAM_WRn),\r
463.I_VID_RAM_RDn(W_VID_RAM_RDn),\r
464.I_VID_RAM_WRn(W_VID_RAM_WRn),\r
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465\r
466.O_C_BLnX(W_C_BLnX),\r
467.O_8HF(W_8HF),\r
468.O_256HnX(W_256HnX),\r
469.O_1VF(W_1VF),\r
470.O_MISSILEn(W_MISSILEn),\r
471.O_SHELLn(W_SHELLn),\r
472.O_BD(W_VID_DO),\r
473.O_VID(W_VID),\r
474.O_COL(W_COL)\r
475\r
476);\r
477\r
478wire W_C_BLX;\r
479wire W_STARS_OFFn;\r
480wire [2:0]W_VIDEO_R;\r
481wire [2:0]W_VIDEO_G;\r
482wire [1:0]W_VIDEO_B;\r
483\r
484mc_col_pal MC_COL_PAL(\r
485\r
486.I_CLK_12M(W_CLK_12M),\r
487.I_CLK_6M(W_CLK_6M),\r
488.I_VID(W_VID),\r
489.I_COL(W_COL),\r
490.I_C_BLnX(W_C_BLnX),\r
491\r
492.O_C_BLX(W_C_BLX),\r
493.O_STARS_OFFn(W_STARS_OFFn),\r
494.O_R(W_VIDEO_R),\r
495.O_G(W_VIDEO_G),\r
496.O_B(W_VIDEO_B)\r
497\r
498);\r
499\r
500wire [2:0]W_STARS_R;\r
501wire [2:0]W_STARS_G;\r
502wire [1:0]W_STARS_B;\r
503\r
504mc_stars MC_STARS( \r
505\r
506.I_CLK_18M(I_CLK_18432M),\r
507`ifdef DEVICE_CYCLONE\r
508.I_CLK_6M(~WB_CLK_6M),\r
509`endif\r
510`ifdef DEVICE_SPARTAN2E \r
511.I_CLK_6M(WB_CLK_6M), \r
512`endif\r
513.I_H_FLIP(W_H_FLIP),\r
514.I_V_SYNC(W_V_SYNC),\r
515.I_8HF(W_8HF),\r
516.I_256HnX(W_256HnX),\r
517.I_1VF(W_1VF),\r
518.I_2V(W_V_CNT[1]),\r
519.I_STARS_ON(W_STARS_ON),\r
520.I_STARS_OFFn(W_STARS_OFFn),\r
521\r
522.O_R(W_STARS_R),\r
523.O_G(W_STARS_G),\r
524.O_B(W_STARS_B),\r
525.O_NOISE()\r
526\r
527);\r
528\r
529wire [2:0]W_R;\r
530wire [2:0]W_G;\r
531wire [1:0]W_B;\r
532\r
533mc_vedio_mix MIX(\r
534\r
535.I_VID_R(W_VIDEO_R),\r
536.I_VID_G(W_VIDEO_G),\r
537.I_VID_B(W_VIDEO_B),\r
538.I_STR_R(W_STARS_R),\r
539.I_STR_G(W_STARS_G),\r
540.I_STR_B(W_STARS_B),\r
541\r
542.I_C_BLnXX(~W_C_BLX),\r
543.I_C_BLX(W_C_BLX | ~W_V_BL2n),\r
544.I_MISSILEn(W_MISSILEn),\r
545.I_SHELLn(W_SHELLn),\r
546\r
547.O_R(W_R),\r
548.O_G(W_G),\r
549.O_B(W_B)\r
550\r
551);\r
552\r
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553wire [2:0]W_VGA_R;\r
554wire [2:0]W_VGA_G;\r
555wire [1:0]W_VGA_B;\r
556\r
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557`ifdef VGA_USE\r
558mc_vga_if VGA(\r
559\r
560// input\r
561.I_CLK_1(W_CLK_6M),\r
562.I_CLK_2(W_CLK_12M),\r
563.I_R(W_R),\r
564.I_G(W_G),\r
565.I_B(W_B),\r
566.I_H_SYNC(W_H_SYNC),\r
567.I_V_SYNC(W_V_SYNC),\r
568// output\r
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569.O_R(W_VGA_R),\r
570.O_G(W_VGA_G),\r
571.O_B(W_VGA_B),\r
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572.O_H_SYNCn(O_VGA_H_SYNCn),\r
573.O_V_SYNCn(O_VGA_V_SYNCn)\r
574\r
575);\r
576\r
577`else\r
578\r
491f582f 579assign W_VGA_R[2:0] = W_R;\r
782690d0 580\r
491f582f 581assign W_VGA_G[2:0] = W_G;\r
782690d0 582\r
491f582f 583assign W_VGA_B[1:0] = W_B;\r
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584\r
585//assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ; // AKIDUKI LCD USED\r
586assign O_VGA_H_SYNCn = ~W_H_SYNC ;\r
587assign O_VGA_V_SYNCn = ~W_V_SYNC ;\r
588\r
589`endif\r
590\r
e780c439 591assign O_VGA_R[3:0] = {W_VGA_R[0], W_VGA_R[1], W_VGA_R[2], 1'b0};\r
491f582f 592\r
e780c439 593assign O_VGA_G[3:0] = {W_VGA_G[0], W_VGA_G[1], W_VGA_G[2], 1'b0};\r
491f582f 594\r
e780c439 595assign O_VGA_B[3:0] = {W_VGA_B[0], W_VGA_B[1], 2'b0};\r
491f582f 596\r
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597wire [7:0]W_SDAT_A;\r
598\r
599mc_sound_a MC_SOUND_A(\r
600\r
601.I_CLK_12M(W_CLK_12M),\r
602.I_CLK_6M(W_CLK_6M),\r
603.I_H_CNT1(W_H_CNT[1]),\r
604.I_BD(W_BDI),\r
605.I_PITCHn(W_PITCHn),\r
606.I_VOL1(W_VOL1),\r
607.I_VOL2(W_VOL2),\r
608\r
609.O_SDAT(W_SDAT_A),\r
610.O_DO()\r
611\r
612);\r
613\r
614wire [7:0]W_SDAT_B;\r
615\r
616mc_sound_b MC_SOUND_B(\r
617\r
618.I_CLK1(I_CLK_18432M),\r
619.I_CLK2(W_CLK_6M),\r
620.I_RSTn(rst_count[3]),\r
621.I_SW({&on_game[1:0],W_HIT,W_FIRE}),\r
622\r
623.O_WAV_A0(W_WAV_A0),\r
624.O_WAV_A1(W_WAV_A1),\r
625.O_WAV_A2(W_WAV_A2),\r
626.I_WAV_D0(W_WAV_D0),\r
627.I_WAV_D1(W_WAV_D1),\r
628.I_WAV_D2(W_WAV_D2),\r
629\r
630.O_SDAT(W_SDAT_B)\r
631\r
632);\r
633\r
634wire W_DAC_A;\r
635wire W_DAC_B;\r
636\r
637assign O_SOUND_OUT_L = W_DAC_A;\r
638assign O_SOUND_OUT_R = W_DAC_B;\r
639\r
640dac wav_dac_a(\r
641\r
642.Clk(I_CLK_18432M), \r
643.Reset(~W_RESETn),\r
644.DACin(W_SDAT_A),\r
645.DACout(W_DAC_A)\r
646\r
647);\r
648\r
649dac wav_dac_b(\r
650\r
651.Clk(I_CLK_18432M), \r
652.Reset(~W_RESETn),\r
653.DACin(W_SDAT_B),\r
654.DACout(W_DAC_B)\r
655\r
656);\r
657\r
658\r
659endmodule\r
660\r
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