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[fpga-games] / galaxian / src / mc_adec.v

//---------------------------------------------------------------------\r
// FPGA GALAXIAN   ADDRESS DECDER\r
//\r
// Version : 2.01\r
//\r
// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
//\r
// Important !\r
//\r
// This program is freeware for non-commercial use. \r
// An author does no guarantee about this program.\r
// You can use this under your own risk.\r
//\r
// 2004- 4-30  galaxian modify by K.DEGAWA\r
// 2004- 5- 6  first release.\r
// 2004- 8-23  Improvement with T80-IP. \r
//---------------------------------------------------------------------\r
//\r
//GALAXIAN Address Map\r
//\r
// Address      Item(R..read-mode W..wight-mode)        Parts                       \r
//0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )    \r
//2000 - 3FFF   CPU-ROM..R                            ( 7L )\r
//4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P ) \r
//5000 - 57FF   VID-RAM..RW   \r
//5800 - 5FFF   OBJ-RAM..RW\r
//6000 -        SW0..R   LAMP......W\r
//6800 -        SW1..R   SOUND.....W\r
//7000 -        DIP..R   \r
//7001                   NMI_ON....W\r
//7004                   STARS_ON..W\r
//7006                   H_FLIP....W\r
//7007                   V-FLIP....W\r
//7800          WDR..R   PITCH.....W\r
//\r
//W MODE\r
//6000 - 6002           \r
//6003                  COIN CNTR                   \r
//6004 - 6007           SOUND CONTROL(OSC)\r
//\r
//6800                  SOUND CONTROL(FS1)\r
//6801                  SOUND CONTROL(FS2)\r
//6802                  SOUND CONTROL(FS3)\r
//6803                  SOUND CONTROL(HIT)\r
//6805                  SOUND CONTROL(SHOT)\r
//6806                  SOUND CONTROL(VOL1)\r
//6807                  SOUND CONTROL(VOL2)\r
//\r
\r
module mc_adec(\r
\r
I_CLK_12M,\r
I_CLK_6M,\r
I_CPU_CLK,\r
I_RSTn,\r
\r
I_CPU_A,\r
I_CPU_D,\r
I_MREQn,\r
I_RFSHn,\r
I_RDn,\r
I_WRn,\r
I_H_BL,\r
I_V_BLn,\r
\r
O_WAITn,\r
O_NMIn,\r
O_CPU_ROM_CSn,\r
O_CPU_RAM_RDn,\r
O_CPU_RAM_WRn,\r
O_CPU_RAM_CSn,\r
O_OBJ_RAM_RDn,\r
O_OBJ_RAM_WRn,\r
O_OBJ_RAM_RQn,\r
O_VID_RAM_RDn,\r
O_VID_RAM_WRn,\r
O_SW0_OEn,\r
O_SW1_OEn,\r
O_DIP_OEn,\r
O_WDR_OEn,\r
O_LAMP_WEn,\r
O_SOUND_WEn,\r
O_PITCHn,\r
O_H_FLIP,\r
O_V_FLIP,\r
O_BD_G,\r
O_STARS_ON\r
\r
);\r
\r
\r
input  I_CLK_12M;\r
input  I_CLK_6M;\r
input  I_CPU_CLK;\r
input  I_RSTn;\r
\r
input  [15:0]I_CPU_A;\r
input  I_CPU_D;\r
input  I_MREQn;\r
input  I_RFSHn;\r
input  I_RDn;\r
input  I_WRn;\r
input  I_H_BL;\r
input  I_V_BLn;\r
\r
output O_WAITn;\r
output O_NMIn;\r
output O_CPU_ROM_CSn;\r
output O_CPU_RAM_RDn;\r
output O_CPU_RAM_WRn;\r
output O_CPU_RAM_CSn;\r
output O_OBJ_RAM_RDn;\r
output O_OBJ_RAM_WRn;\r
output O_OBJ_RAM_RQn;\r
output O_VID_RAM_RDn;\r
output O_VID_RAM_WRn;\r
output O_SW0_OEn;\r
output O_SW1_OEn;\r
output O_DIP_OEn;\r
output O_WDR_OEn;\r
output O_LAMP_WEn;\r
output O_SOUND_WEn;\r
output O_PITCHn;\r
output O_H_FLIP;\r
output O_V_FLIP;\r
output O_BD_G;\r
output O_STARS_ON;\r
\r
\r
wire   [3:0]W_8E1_Q;\r
wire   [3:0]W_8E2_Q;\r
wire   [7:0]W_8P_Q,W_8N_Q,W_8M_Q;\r
reg    [7:0]W_9N_Q;\r
wire   W_NMI_ONn = W_9N_Q[1]; //  galaxian\r
//------  CPU WAITn  ---------------------------------------------- \r
\r
reg    W_6S1_Q,W_6S1_Qn;\r
reg    W_6S2_Qn;\r
\r
//assign O_WAITn = W_6S1_Qn;\r
assign O_WAITn = 1'b1 ; // No Wait\r
\r
always@(posedge I_CPU_CLK or negedge I_V_BLn)\r
begin\r
   if(I_V_BLn == 1'b0)begin\r
      W_6S1_Q  <= 1'b0;\r
      W_6S1_Qn <= 1'b1;\r
   end\r
   else begin\r
      W_6S1_Q  <= ~(I_H_BL | W_8P_Q[2]);\r
      W_6S1_Qn <=   I_H_BL | W_8P_Q[2];\r
   end\r
end\r
\r
always@(negedge I_CPU_CLK)\r
begin\r
   W_6S2_Qn <= ~W_6S1_Q;\r
end\r
//------  CPU NMIn  ----------------------------------------------- \r
wire  W_V_BL = ~I_V_BLn;\r
reg   O_NMIn;\r
always@(posedge W_V_BL or negedge W_NMI_ONn)\r
begin\r
   if(~W_NMI_ONn)\r
      O_NMIn <= 1'b1;\r
   else\r
      O_NMIn <= 1'b0;\r
end\r
//----------------------------------------------------------------- \r
logic_74xx139 U_8E1(\r
\r
.I_G(I_MREQn),\r
.I_Sel(I_CPU_A[15:14]),\r
.O_Q(W_8E1_Q)\r
\r
);\r
\r
//--------   CPU_ROM CS    0000 - 3FFF  --------------------------- \r
logic_74xx139 U_8E2(\r
\r
.I_G(I_RDn),\r
.I_Sel({W_8E1_Q[0],I_CPU_A[13]}),\r
.O_Q(W_8E2_Q)\r
\r
);\r
\r
assign O_CPU_ROM_CSn = W_8E2_Q[0]&W_8E2_Q[1] ;  //   0000 - 3FFF\r
//-----------------------------------------------------------------\r
//                  ADDRESS\r
//    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE \r
//    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1\r
//    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE \r
//    W_8E1_Q[3] = C000 - FFFF\r
\r
logic_74xx138 U_8P(\r
\r
.I_G1(I_RFSHn),\r
.I_G2a(W_8E1_Q[1]),   // <= *1\r
.I_G2b(W_8E1_Q[1]),   // <= *1\r
.I_Sel(I_CPU_A[13:11]),\r
.O_Q(W_8P_Q)\r
\r
);\r
\r
logic_74xx138 U_8N(\r
\r
.I_G1(1'b1),\r
.I_G2a(I_RDn),\r
.I_G2b(W_8E1_Q[1]),   // <= *1\r
.I_Sel(I_CPU_A[13:11]),\r
.O_Q(W_8N_Q)\r
\r
);\r
\r
logic_74xx138 U_8M(\r
\r
//.I_G1(W_6S2_Qn),\r
.I_G1(1'b1), // No Wait\r
.I_G2a(I_WRn),\r
.I_G2b(W_8E1_Q[1]),   // <= *1\r
.I_Sel(I_CPU_A[13:11]),\r
.O_Q(W_8M_Q)\r
\r
);\r
\r
assign O_BD_G        = ~(W_8E1_Q[0]&W_8P_Q[0]);  //\r
assign O_OBJ_RAM_RQn = W_8P_Q[3];                //\r
\r
assign O_CPU_RAM_CSn = W_8N_Q[0]&W_8M_Q[0];      //\r
assign O_CPU_RAM_RDn = W_8N_Q[0];                //\r
assign O_CPU_RAM_WRn = W_8M_Q[0];                //\r
assign O_VID_RAM_RDn = W_8N_Q[2];                //\r
assign O_OBJ_RAM_RDn = W_8N_Q[3];                //\r
assign O_SW0_OEn     = W_8N_Q[4];                // \r
assign O_SW1_OEn     = W_8N_Q[5];                // \r
assign O_DIP_OEn     = W_8N_Q[6];                // \r
assign O_WDR_OEn     = W_8N_Q[7];                // \r
\r
assign O_VID_RAM_WRn = W_8M_Q[2];                // \r
assign O_OBJ_RAM_WRn = W_8M_Q[3];                // \r
assign O_LAMP_WEn    = W_8M_Q[4];                // \r
assign O_SOUND_WEn   = W_8M_Q[5];                // \r
\r
assign O_PITCHn      = W_8M_Q[7];                // \r
\r
//---  Parts 9N ---------\r
\r
always@(posedge I_CLK_12M or negedge I_RSTn)\r
begin\r
   if(I_RSTn == 1'b0)begin\r
      W_9N_Q <= 0;\r
   end \r
   else begin\r
      if(W_8M_Q[6] == 1'b0)begin\r
         case(I_CPU_A[2:0])\r
            3'h0 : W_9N_Q[0] <= I_CPU_D;\r
            3'h1 : W_9N_Q[1] <= I_CPU_D;\r
            3'h2 : W_9N_Q[2] <= I_CPU_D;\r
            3'h3 : W_9N_Q[3] <= I_CPU_D;\r
            3'h4 : W_9N_Q[4] <= I_CPU_D;\r
            3'h5 : W_9N_Q[5] <= I_CPU_D;\r
            3'h6 : W_9N_Q[6] <= I_CPU_D;\r
            3'h7 : W_9N_Q[7] <= I_CPU_D;\r
         endcase\r
      end\r
   end\r
end\r
\r
assign O_STARS_ON    = W_9N_Q[4];                // \r
assign O_H_FLIP      = W_9N_Q[6];                // \r
assign O_V_FLIP      = W_9N_Q[7];                // \r
\r
\r
endmodule