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[fpga-games] / galaxian / src / mc_clock.v

//---------------------------------------------------------------------\r
// FPGA MOONCRESTA   CLOCK GEN \r
//\r
// Version : 1.00\r
//\r
// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
//\r
// Important !\r
//\r
// This program is freeware for non-commercial use. \r
// An author does no guarantee about this program.\r
// You can use this under your own risk.\r
//\r
//---------------------------------------------------------------------\r
\r
\r
\r
module mc_clock(\r
\r
I_CLK_18M,\r
O_CLK_12M,\r
O_CLK_06M,\r
O_CLK_06Mn\r
\r
);\r
\r
input  I_CLK_18M;\r
output O_CLK_12M;\r
output O_CLK_06M;\r
output O_CLK_06Mn;\r
\r
// 2/3 clock divider(duty 33%)\r
reg [1:0] clk_ff1,clk_ff2;\r
//I_CLK   1010101010101010101\r
//c_ff10  0011110011110011110\r
//c_ff11  0011000011000011000\r
//c_ff20  0000110000110000110\r
//c_ff21  0110000110000110000\r
//O_12M   0000110110110110110\r
always @(posedge I_CLK_18M)\r
begin\r
   clk_ff1[0] <= ~clk_ff1[0] | clk_ff1[1];\r
   clk_ff1[1] <= ~clk_ff1[0] & ~clk_ff1[1];\r
   clk_ff2[0] <= clk_ff1[0] & clk_ff1[1];\r
end\r
always @(negedge I_CLK_18M)\r
   clk_ff2[1] <= ~clk_ff1[0] & ~clk_ff1[1];\r
\r
// 2/3 clock         (duty 66%)\r
assign O_CLK_12M = clk_ff2[0]| clk_ff2[1];\r
 \r
// 1/3 clock divider (duty 50%)\r
reg CLK_6M , CLK_6Mn;\r
always @(posedge O_CLK_12M)\r
begin\r
   CLK_6Mn <=  CLK_6M;\r
   CLK_6M  <= ~CLK_6M;\r
end\r
assign O_CLK_06M = CLK_6M;\r
assign O_CLK_06Mn = CLK_6Mn;\r
\r
\r
endmodule