projects / fpga-games / blame
| Commit | Line | Data |
|---|---|---|
| 782690d0 MG |
1 | //===============================================================================\r |
| 2 | // FPGA MOONCRESTA VIDEO-LD_PLS_GEN\r | |
| 3 | //\r | |
| 4 | // Version : 2.00\r | |
| 5 | //\r | |
| 6 | // Copyright(c) 2004 Katsumi Degawa , All rights reserved\r | |
| 7 | //\r | |
| 8 | // Important !\r | |
| 9 | //\r | |
| 10 | // This program is freeware for non-commercial use. \r | |
| 11 | // An author does no guarantee about this program.\r | |
| 12 | // You can use this under your own risk.\r | |
| 13 | //\r | |
| 14 | // 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r | |
| 15 | //================================================================================\r | |
| 16 | \r | |
| 17 | \r | |
| 18 | module mc_ld_pls(\r | |
| 19 | \r | |
| 20 | I_CLK_6M,\r | |
| 21 | I_H_CNT,\r | |
| 22 | I_3D_DI,\r | |
| 23 | \r | |
| 24 | O_LDn,\r | |
| 25 | O_CNTRLDn,\r | |
| 26 | O_CNTRCLRn,\r | |
| 27 | O_COLLn,\r | |
| 28 | O_VPLn,\r | |
| 29 | O_OBJDATALn,\r | |
| 30 | O_MLDn,\r | |
| 31 | O_SLDn\r | |
| 32 | \r | |
| 33 | );\r | |
| 34 | \r | |
| 35 | input I_CLK_6M;\r | |
| 36 | input [8:0]I_H_CNT;\r | |
| 37 | input I_3D_DI;\r | |
| 38 | \r | |
| 39 | output O_LDn;\r | |
| 40 | output O_CNTRLDn;\r | |
| 41 | output O_CNTRCLRn;\r | |
| 42 | output O_COLLn;\r | |
| 43 | output O_VPLn;\r | |
| 44 | output O_OBJDATALn;\r | |
| 45 | output O_MLDn;\r | |
| 46 | output O_SLDn;\r | |
| 47 | \r | |
| 48 | reg W_5C_Q;\r | |
| 49 | always@(posedge I_CLK_6M)\r | |
| 50 | W_5C_Q <= I_H_CNT[0];\r | |
| 51 | \r | |
| 52 | // Parts 4D\r | |
| 53 | wire W_4D1_G = ~(I_H_CNT[0]&I_H_CNT[1]&I_H_CNT[2]);\r | |
| 54 | wire [3:0]W_4D1_Q;\r | |
| 55 | wire [3:0]W_4D2_Q;\r | |
| 56 | \r | |
| 57 | logic_74xx139 U_4D1(\r | |
| 58 | \r | |
| 59 | .I_G(W_4D1_G),\r | |
| 60 | .I_Sel({I_H_CNT[8],I_H_CNT[3]}),\r | |
| 61 | .O_Q(W_4D1_Q)\r | |
| 62 | \r | |
| 63 | );\r | |
| 64 | \r | |
| 65 | logic_74xx139 U_4D2(\r | |
| 66 | \r | |
| 67 | .I_G(W_5C_Q),\r | |
| 68 | .I_Sel(I_H_CNT[2:1]),\r | |
| 69 | .O_Q(W_4D2_Q)\r | |
| 70 | \r | |
| 71 | );\r | |
| 72 | \r | |
| 73 | // Parts 4C\r | |
| 74 | wire [3:0]W_4C1_Q;\r | |
| 75 | wire [3:0]W_4C2_Q;\r | |
| 76 | \r | |
| 77 | logic_74xx139 U_4C1(\r | |
| 78 | \r | |
| 79 | .I_G(W_4D2_Q[1]),\r | |
| 80 | .I_Sel({I_H_CNT[8],I_H_CNT[3]}),\r | |
| 81 | .O_Q(W_4C1_Q)\r | |
| 82 | \r | |
| 83 | );\r | |
| 84 | \r | |
| 85 | reg W_4C1_Q3;\r | |
| 86 | always@(negedge I_CLK_6M) // 2004-9-22 added\r | |
| 87 | W_4C1_Q3 <= W_4C1_Q[3];\r | |
| 88 | \r | |
| 89 | reg W_4C2_B;\r | |
| 90 | always@(posedge W_4C1_Q3) \r | |
| 91 | W_4C2_B <= I_3D_DI;\r | |
| 92 | \r | |
| 93 | logic_74xx139 U_4C2(\r | |
| 94 | \r | |
| 95 | .I_G(W_4D1_Q[3]),\r | |
| 96 | .I_Sel({W_4C2_B,~(I_H_CNT[6]&I_H_CNT[5]&I_H_CNT[4]&I_H_CNT[3])}),\r | |
| 97 | .O_Q(W_4C2_Q)\r | |
| 98 | \r | |
| 99 | );\r | |
| 100 | \r | |
| 101 | assign O_LDn = W_4D1_G;\r | |
| 102 | assign O_CNTRLDn = W_4D1_Q[2];\r | |
| 103 | assign O_CNTRCLRn = W_4D1_Q[0];\r | |
| 104 | assign O_COLLn = W_4D2_Q[2];\r | |
| 105 | assign O_VPLn = W_4D2_Q[0];\r | |
| 106 | assign O_OBJDATALn = W_4C1_Q[2];\r | |
| 107 | assign O_MLDn = W_4C2_Q[0];\r | |
| 108 | assign O_SLDn = W_4C2_Q[1];\r | |
| 109 | \r | |
| 110 | \r | |
| 111 | endmodule\r |