[fpga-games] / galaxian / src / t80as.v

//\r
// Daniel Wallner's T80 header file for verilog\r
//\r
// Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved\r
//\r
// Important !\r
//\r
// This program is freeware for non-commercial use. \r
// An author does no guarantee about this program.\r
// You can use this under your own risk. \r
//\r
//\r
module T80as(\r
	RESET_n,CLK_n,WAIT_n,INT_n,NMI_n,BUSRQ_n,\r
	M1_n,MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,HALT_n,BUSAK_n,\r
	A,DI,DO,DOE);\r
\r
input RESET_n,CLK_n,WAIT_n,INT_n,NMI_n,BUSRQ_n;\r
output M1_n,MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,HALT_n,BUSAK_n;\r
output [15:0] A;\r
input [7:0] DI;\r
output [7:0] DO;\r
output DOE;\r
\r
endmodule\r
Commit	Line	Data
782690d0 MG	1	//\r
	2	// Daniel Wallner's T80 header file for verilog\r
	3	//\r
	4	// Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved\r
	5	//\r
	6	// Important !\r
	7	//\r
	8	// This program is freeware for non-commercial use. \r
	9	// An author does no guarantee about this program.\r
	10	// You can use this under your own risk. \r
	11	//\r
	12	//\r
	13	module T80as(\r
	14	RESET_n,CLK_n,WAIT_n,INT_n,NMI_n,BUSRQ_n,\r
	15	M1_n,MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,HALT_n,BUSAK_n,\r
	16	A,DI,DO,DOE);\r
	17	\r
	18	input RESET_n,CLK_n,WAIT_n,INT_n,NMI_n,BUSRQ_n;\r
	19	output M1_n,MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,HALT_n,BUSAK_n;\r
	20	output [15:0] A;\r
	21	input [7:0] DI;\r
	22	output [7:0] DO;\r
	23	output DOE;\r
	24	\r
	25	endmodule\r