projects / fpga-games / blame
| Commit | Line | Data |
|---|---|---|
| b884ab49 MG |
1 | CONFIG PART = XC3SD1800A-FG676-4; |
| 2 | ||
| 3 | NET I_CLK_125M TNM_NET = clk_ref_grp; | |
| 4 | TIMESPEC TS01 = PERIOD : clk_ref_grp : 8.00 : PRIORITY 1; #125 MHz | |
| 5 | ||
| 6 | TIMESPEC TS11=FROM:PADS:TO:FFS : 30 ns; | |
| 7 | TIMESPEC TS12=FROM:FFS:TO:PADS : 30 ns; | |
| 8 | ||
| 782690d0 MG |
9 | #---------- MasterClock 18.432MHz ---------- |
| 10 | NET "I_CLK_125M" LOC = "F13" | IOSTANDARD = LVCMOS33; | |
| 11 | #------------------------------------------- | |
| 12 | #---------- SW I/F ------------------------- | |
| 3fc34adf MG |
13 | NET "I_PSW<0>" LOC = "K19" | IOSTANDARD = LVTTL | PULLUP; #up |
| 14 | NET "I_PSW<1>" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP; #down | |
| 15 | NET "I_PSW<2>" LOC = "G22" | IOSTANDARD = LVTTL | PULLUP; #left | |
| 16 | NET "I_PSW<3>" LOC = "F22" | IOSTANDARD = LVTTL | PULLUP; #right | |
| 17 | NET "I_PSW<4>" LOC = "F23" | IOSTANDARD = LVTTL | PULLUP; #btn | |
| 18 | NET "I_PSW<5>" LOC = "J10" | IOSTANDARD = LVTTL | PULLDOWN; #s8 - s1 | |
| 19 | NET "I_PSW<6>" LOC = "J13" | IOSTANDARD = LVTTL | PULLDOWN; #s7 - c1 | |
| 20 | NET "I_PSW<7>" LOC = "J15" | IOSTANDARD = LVTTL | PULLDOWN; #s6 - s2 | |
| 21 | NET "I_PSW<8>" LOC = "J17" | IOSTANDARD = LVTTL | PULLDOWN; #s5 - c2 | |
| 782690d0 | 22 | #------------------------------------------- |
| 782690d0 MG |
23 | #--------- SOUND I/F ----------------------- |
| 24 | NET "O_SOUND_OUT_L" LOC = "AA22" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; | |
| 25 | NET "O_SOUND_OUT_R" LOC = "V19" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; | |
| 26 | #------------------------------------------- | |
| 27 | #--------- VIDEO I/F ----------------------- | |
| 491f582f MG |
28 | NET "O_VGA_R<0>" LOC = "L20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
| 29 | NET "O_VGA_R<1>" LOC = "K20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; | |
| 30 | NET "O_VGA_R<2>" LOC = "F25" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; | |
| 31 | NET "O_VGA_R<3>" LOC = "F24" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; | |
| 32 | NET "O_VGA_G<0>" LOC = "M19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; | |
| 33 | NET "O_VGA_G<1>" LOC = "M18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; | |
| 34 | NET "O_VGA_G<2>" LOC = "J23" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; | |
| 35 | NET "O_VGA_G<3>" LOC = "J22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; | |
| 36 | NET "O_VGA_B<0>" LOC = "L22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; | |
| 37 | NET "O_VGA_B<1>" LOC = "K21" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; | |
| 38 | NET "O_VGA_B<2>" LOC = "G23" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; | |
| 39 | NET "O_VGA_B<3>" LOC = "G24" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; | |
| 782690d0 MG |
40 | |
| 41 | NET "O_VGA_H_SYNCn" LOC = "K26" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; | |
| 42 | NET "O_VGA_V_SYNCn" LOC = "K25" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; | |
| 43 | ||
| 44 | ||
| 45 | #------------------------------------------- | |
| 46 | # | |
| 47 | #---------- Build-in ROM ------------------------------------------------------------------------------- | |
| 48 | #INST "col_rom00" INIT_00 = c6077600f007f6000700000007a0c00007c4c0003f07d8003fc01600f6000000; |