faster clock for roms

[fpga-games] / galaxian / src / mc_col_pal.v

//===============================================================================\r
// FPGA MOONCRESTA COLOR-PALETTE\r
//\r
// Version : 2.00\r
//\r
// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
//\r
// Important !\r
//\r
// This program is freeware for non-commercial use. \r
// An author does no guarantee about this program.\r
// You can use this under your own risk.\r
//\r
// 2004- 9-18 added Xilinx Device.  K.Degawa\r
//================================================================================\r
`include "src/mc_conf.v"\r
\r
module mc_col_pal(\r
\r
I_CLK_12M,\r
I_CLK_6M,\r
I_VID,\r
I_COL,\r
I_C_BLnX,\r
\r
O_C_BLX,\r
O_STARS_OFFn,\r
O_R,\r
O_G,\r
O_B\r
\r
);\r
\r
input  I_CLK_12M;\r
input  I_CLK_6M;\r
input  [1:0]I_VID;\r
input  [2:0]I_COL;\r
input  I_C_BLnX;\r
\r
output O_C_BLX;\r
output O_STARS_OFFn;\r
output [2:0]O_R;\r
output [2:0]O_G;\r
output [1:0]O_B;\r
\r
//---    Parts 6M    --------------------------------------------------------\r
wire   [6:0]W_6M_DI = {I_COL[2:0],I_VID[1:0],~(I_VID[0]|I_VID[1]),I_C_BLnX};\r
reg    [6:0]W_6M_DO;\r
\r
wire   W_6M_CLR = W_6M_DI[0]|W_6M_DO[0];\r
assign O_C_BLX = ~(W_6M_DI[0]|W_6M_DO[0]);\r
assign O_STARS_OFFn = W_6M_DO[1];\r
\r
always@(posedge I_CLK_6M or negedge W_6M_CLR)\r
begin\r
   if(W_6M_CLR==1'b0)\r
      W_6M_DO <= 7'h00;\r
   else\r
      W_6M_DO <= W_6M_DI;\r
end\r
//---    COL ROM     --------------------------------------------------------\r
wire   [4:0]W_COL_ROM_A = W_6M_DO[6:2];\r
wire   [7:0]W_COL_ROM_DO;\r
wire   W_COL_ROM_OEn = W_6M_DO[1];\r
\r
`ifdef DEVICE_CYCLONE\r
mc_col_rom COL_ROM(\r
\r
.I_CLK(I_CLK_12M),\r
.I_ADDR(W_COL_ROM_A),\r
.O_DO(W_COL_ROM_DO),\r
.I_OEn(W_COL_ROM_OEn)\r
\r
);\r
`endif\r
`ifdef DEVICE_SPARTAN2E\r
GALAXIAN_6L COL_ROM(\r
.CLK(I_CLK_12M),\r
.ADDR(W_COL_ROM_A),\r
.DATA(W_COL_ROM_DO),\r
.ENA(1'b1)\r
);\r
//RAMB4_S8 col_rom00(\r
//\r
//.CLK(I_CLK_12M),\r
//.ADDR({4'b0000,W_COL_ROM_A[4:0]}),\r
//.DI(8'h00),\r
//.DO(W_COL_ROM_DO),\r
//.EN(1'b1),\r
//.WE(1'b0),\r
//.RST(1'b0)\r
//\r
//);\r
`endif\r
//---    VID OUT     --------------------------------------------------------\r
assign O_R[0] = W_COL_ROM_DO[2];\r
assign O_R[1] = W_COL_ROM_DO[1];\r
assign O_R[2] = W_COL_ROM_DO[0];\r
\r
assign O_G[0] = W_COL_ROM_DO[5];\r
assign O_G[1] = W_COL_ROM_DO[4];\r
assign O_G[2] = W_COL_ROM_DO[3];\r
\r
assign O_B[0] = W_COL_ROM_DO[7];\r
assign O_B[1] = W_COL_ROM_DO[6];\r
\r
\r
endmodule\r