faster clock for roms

[fpga-games] / galaxian / src / mc_hv_count.v

//---------------------------------------------------------------------\r
// FPGA MOONCRESTA   H & V COUNTER \r
//\r
// Version : 2.00\r
//\r
// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
//\r
// Important !\r
//\r
// This program is freeware for non-commercial use. \r
// An author does no guarantee about this program.\r
// You can use this under your own risk.\r
//\r
// 2004- 9-22  \r
//---------------------------------------------------------------------\r
//  MoonCrest hv_count\r
//  H_CNT   0 - 255 , 384 - 511  Total 384 count\r
//  V_CNT   0 - 255 , 504 - 511  Total 264 count\r
//-----------------------------------------------------------------------------------------\r
// H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8],  \r
//    1 H     2 H      4H       8H       16 H     32H      64 H     128 H   256 H\r
//-----------------------------------------------------------------------------------------\r
// V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  \r
//    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V \r
//-----------------------------------------------------------------------------------------\r
\r
module mc_hv_count(\r
\r
I_CLK,     //  6MHz\r
I_RSTn,\r
\r
O_H_CNT,\r
O_H_SYNC,\r
O_H_BL,\r
O_V_CNT,\r
O_V_SYNC,\r
O_V_BLn,\r
O_V_BL2n,\r
O_C_BLn\r
\r
);\r
\r
input  I_CLK,I_RSTn;\r
output [8:0]O_H_CNT;\r
output O_H_SYNC;\r
output O_H_BL;\r
output O_V_BL2n;\r
output [7:0]O_V_CNT;\r
output O_V_SYNC;\r
output O_V_BLn;\r
\r
output O_C_BLn;\r
\r
//-------   H_COUNT   ----------------------------------------   \r
reg    [8:0]H_CNT;\r
always@(posedge I_CLK)\r
begin\r
   H_CNT <= H_CNT==255 ? 384 : H_CNT +1 ;\r
end\r
assign O_H_CNT  = H_CNT[8:0];\r
\r
//-------   H_SYNC     ----------------------------------------\r
\r
reg    H_SYNCn;\r
wire   H_SYNC = ~H_SYNCn;\r
always@(posedge H_CNT[4] or negedge H_CNT[8]) \r
begin\r
   if(H_CNT[8]==1'b0) H_SYNCn <= 1'b1;\r
   else   H_SYNCn <= ~(~H_CNT[6]& H_CNT[5]);\r
end\r
\r
assign O_H_SYNC = H_SYNC;\r
//-------   H_BL     ------------------------------------------\r
\r
reg    H_BL;\r
\r
always@(posedge I_CLK)\r
begin\r
   case(H_CNT[8:0])\r
      387:H_BL<=1'b1;\r
      503:H_BL<=1'b0;\r
    default:;\r
   endcase\r
end\r
\r
assign O_H_BL = H_BL;\r
//-------   V_COUNT   ----------------------------------------   \r
reg    [8:0]V_CNT;\r
always@(posedge H_SYNC or negedge I_RSTn)\r
begin\r
   if(I_RSTn==1'b0)\r
      V_CNT <= 0;\r
   else\r
      V_CNT <= V_CNT==255 ? 504 : V_CNT +1 ;\r
end\r
assign O_V_CNT  = V_CNT[7:0];\r
assign O_V_SYNC = V_CNT[8];\r
\r
//-------   V_BLn    ------------------------------------------\r
\r
reg    V_BLn;\r
always@(posedge H_SYNC)\r
begin\r
   case(V_CNT[7:0])\r
    239: V_BLn <= 0;\r
     15: V_BLn <= 1;\r
    default:;\r
   endcase\r
end\r
\r
reg    V_BL2n;\r
always@(posedge H_SYNC)\r
begin\r
   case(V_CNT[7:0])\r
    239: V_BL2n <= 0;\r
     16: V_BL2n <= 1;\r
    default:;\r
   endcase\r
end\r
\r
assign O_V_BLn  = V_BLn;\r
assign O_V_BL2n = V_BL2n;\r
//-------   C_BLn     ------------------------------------------\r
\r
assign O_C_BLn = ~(~V_BLn | H_CNT[8]);\r
\r
endmodule