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1 | //===============================================================================\r |
2 | // FPGA MOONCRESTA VIDEO-MISSILE\r | |
3 | //\r | |
4 | // Version : 2.00\r | |
5 | //\r | |
6 | // Copyright(c) 2004 Katsumi Degawa , All rights reserved\r | |
7 | //\r | |
8 | // Important !\r | |
9 | //\r | |
10 | // This program is freeware for non-commercial use. \r | |
11 | // An author does no guarantee about this program.\r | |
12 | // You can use this under your own risk.\r | |
13 | //\r | |
14 | // 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r | |
15 | //================================================================================\r | |
16 | \r | |
17 | \r | |
18 | module mc_missile(\r | |
19 | \r | |
20 | I_CLK_18M,\r | |
21 | I_CLK_6M,\r | |
22 | I_C_BLn_X,\r | |
23 | I_MLDn,\r | |
24 | I_SLDn,\r | |
25 | I_HPOS,\r | |
26 | \r | |
27 | O_MISSILEn,\r | |
28 | O_SHELLn\r | |
29 | \r | |
30 | );\r | |
31 | \r | |
32 | input I_CLK_6M,I_CLK_18M;\r | |
33 | input I_C_BLn_X;\r | |
34 | input I_MLDn;\r | |
35 | input I_SLDn;\r | |
36 | input [7:0]I_HPOS;\r | |
37 | \r | |
38 | output O_MISSILEn;\r | |
39 | output O_SHELLn;\r | |
40 | \r | |
41 | reg [7:0]W_45R_Q;\r | |
42 | \r | |
43 | always@(posedge I_CLK_6M)\r | |
44 | begin\r | |
45 | if(I_MLDn==1'b0)\r | |
46 | W_45R_Q <= I_HPOS;\r | |
47 | else begin\r | |
48 | if(I_C_BLn_X)\r | |
49 | W_45R_Q <= W_45R_Q +1;\r | |
50 | else\r | |
51 | W_45R_Q <= W_45R_Q ;\r | |
52 | end\r | |
53 | end\r | |
54 | \r | |
55 | reg W_5P1_Q;\r | |
56 | reg W_5P1_CLK; \r | |
57 | \r | |
58 | always@(posedge I_CLK_18M)\r | |
59 | W_5P1_CLK <= ~((&W_45R_Q[7:2])&W_5P1_Q);\r | |
60 | \r | |
61 | always@(posedge W_5P1_CLK or negedge I_MLDn)\r | |
62 | begin\r | |
63 | if(I_MLDn==1'b0)\r | |
64 | W_5P1_Q <= 1'b1;\r | |
65 | else\r | |
66 | W_5P1_Q <= 1'b0;\r | |
67 | end\r | |
68 | \r | |
69 | assign O_MISSILEn = W_5P1_CLK;\r | |
70 | \r | |
71 | reg [7:0]W_45S_Q;\r | |
72 | always@(posedge I_CLK_6M)\r | |
73 | begin\r | |
74 | if(I_SLDn==1'b0)\r | |
75 | W_45S_Q <= I_HPOS;\r | |
76 | else begin\r | |
77 | if(I_C_BLn_X)\r | |
78 | W_45S_Q <= W_45S_Q +1;\r | |
79 | else\r | |
80 | W_45S_Q <= W_45S_Q ;\r | |
81 | end\r | |
82 | end\r | |
83 | \r | |
84 | reg W_5P2_Q;\r | |
85 | reg W_5P2_CLK;\r | |
86 | \r | |
87 | always@(posedge I_CLK_18M)\r | |
88 | W_5P2_CLK <= ~((&W_45S_Q[7:2])&W_5P2_Q);\r | |
89 | \r | |
90 | always@(posedge W_5P2_CLK or negedge I_SLDn)\r | |
91 | begin\r | |
92 | if(I_SLDn==1'b0)\r | |
93 | W_5P2_Q <= 1'b1;\r | |
94 | else\r | |
95 | W_5P2_Q <= 1'b0;\r | |
96 | end\r | |
97 | \r | |
98 | assign O_SHELLn = W_5P2_CLK;\r | |
99 | \r | |
100 | \r | |
101 | endmodule |