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faster clock for roms
[fpga-games] / galaxian / src / psPAD_top.v
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782690d0
MG		 1//-------------------------------------------------------------------\r
2// \r
3// PLAYSTATION CONTROLLER(DUALSHOCK TYPE) INTERFACE TOP \r
4// \r
5// Version : 2.00 \r
6// \r
7// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved \r
8// \r
9// Important ! \r
10// \r
11// This program is freeware for non-commercial use. \r
12// An author does no guarantee about this program. \r
13// You can use this under your own risk.\r
14// \r
15// 2003.10.30 It is optimized for the FPGA game. \r
16// It was made an analog mode fixation.(Dualshock)\r
17// by K Degawa \r
18// \r
19//-------------------------------------------------------------------\r
20//--------- SIMULATION ---------------------------------------------- \r
21//`define SIMULATION_1 \r
22\r
23`ifdef SIMULATION_1\r
24`define Timer_siz 18 \r
25`else\r
26`define Timer_siz 12\r
27`endif\r
28//-------------------------------------------------------------------\r
29\r
30`timescale 100ps/10ps \r
31`include "src/mc_conf.v"\r
32\r
33module psPAD_top(\r
34\r
35I_CLK250K, // MAIN CLK 250KHz\r
36I_RSTn, // MAIN RESET\r
37O_psCLK, // psCLK CLK OUT\r
38O_psSEL, // psSEL OUT \r
39O_psTXD, // psTXD OUT\r
40I_psRXD, // psRXD IN\r
41O_RXD_1, // RX DATA 1 (8bit)\r
42O_RXD_2, // RX DATA 2 (8bit)\r
43O_RXD_3, // RX DATA 3 (8bit)\r
44O_RXD_4, // RX DATA 4 (8bit)\r
45O_RXD_5, // RX DATA 5 (8bit)\r
46O_RXD_6, // RX DATA 6 (8bit) \r
47I_CONF_SW, // \r
48I_MODE_SW, // \r
49I_MODE_EN, // \r
50I_VIB_SW, // Vibration SW VIB_SW[0] Small Moter OFF 0:ON 1:\r
51 // VIB_SW[1] Bic Moter OFF 0:ON 1(Dualshook Only)\r
52I_VIB_DAT // Vibration(Bic Moter)Data 8'H00-8'HFF (Dualshook Only)\r
53\r
54);\r
55\r
56input I_CLK250K,I_RSTn;\r
57input I_CONF_SW;\r
58input I_MODE_SW,I_MODE_EN;\r
59input [1:0]I_VIB_SW;\r
60input [7:0]I_VIB_DAT;\r
61input I_psRXD;\r
62output O_psCLK;\r
63output O_psSEL;\r
64output O_psTXD;\r
65output [7:0]O_RXD_1;\r
66output [7:0]O_RXD_2;\r
67output [7:0]O_RXD_3;\r
68output [7:0]O_RXD_4;\r
69output [7:0]O_RXD_5;\r
70output [7:0]O_RXD_6;\r
71\r
72wire W_scan_seq_pls;\r
73wire W_type;\r
74wire [3:0]W_byte_cnt;\r
75wire W_RXWT;\r
76wire W_TXWT;\r
77wire W_TXSET;\r
78wire W_TXEN;\r
79wire [7:0]W_TXD_DAT;\r
80wire [7:0]W_RXD_DAT;\r
81wire W_conf_ent;\r
82\r
83ps_pls_gan pls(\r
84\r
85.I_CLK(I_CLK250K),\r
86.I_RSTn(I_RSTn),\r
87.I_TYPE(W_type), // DEGITAL PAD 0: ANALOG PAD 1:\r
88\r
89.O_SCAN_SEQ_PLS(W_scan_seq_pls),\r
90.O_RXWT(W_RXWT),\r
91.O_TXWT(W_TXWT),\r
92.O_TXSET(W_TXSET),\r
93.O_TXEN(W_TXEN),\r
94.O_psCLK(O_psCLK),\r
95.O_psSEL(O_psSEL),\r
96.O_byte_cnt(W_byte_cnt),\r
97\r
98//.Timer(O_Timer)\r
99.Timer()\r
100\r
101); \r
102\r
103`ifdef Dualshock\r
104txd_commnd cmd(\r
105\r
106.I_CLK(W_TXSET),\r
107.I_RSTn(I_RSTn),\r
108.I_BYTE_CNT(W_byte_cnt),\r
109.I_MODE({I_CONF_SW,~I_MODE_EN,I_MODE_SW}),\r
110.I_VIB_SW(I_VIB_SW),\r
111.I_VIB_DAT(I_VIB_DAT),\r
112.I_RXD_DAT(W_RXD_DAT),\r
113.O_TXD_DAT(W_TXD_DAT),\r
114.O_TYPE(W_type),\r
115.O_CONF_ENT(W_conf_ent)\r
116\r
117);\r
118\r
119`else\r
120txd_commnd_EZ cmd(\r
121\r
122.I_CLK(W_TXSET),\r
123.I_RSTn(I_RSTn),\r
124.I_BYTE_CNT(W_byte_cnt),\r
125.I_MODE(),\r
126.I_VIB_SW(I_VIB_SW),\r
127.I_VIB_DAT(),\r
128.I_RXD_DAT(),\r
129.O_TXD_DAT(W_TXD_DAT),\r
130.O_TYPE(W_type),\r
131.O_CONF_ENT(W_conf_ent)\r
132\r
133);\r
134\r
135`endif\r
136\r
137ps_txd txd(\r
138\r
139.I_CLK(I_CLK250K),\r
140.I_RSTn(I_RSTn),\r
141.I_WT(W_TXWT),\r
142.I_EN(W_TXEN),\r
143.I_TXD_DAT(W_TXD_DAT),\r
144.O_psTXD(O_psTXD)\r
145\r
146);\r
147\r
148ps_rxd rxd(\r
149\r
150.I_CLK(O_psCLK),\r
151.I_RSTn(I_RSTn), \r
152.I_WT(W_RXWT),\r
153.I_psRXD(I_psRXD),\r
154.O_RXD_DAT(W_RXD_DAT)\r
155\r
156);\r
157\r
158//---------- RXD DATA DEC ----------------------------------------\r
159reg [7:0]O_RXD_1;\r
160reg [7:0]O_RXD_2;\r
161reg [7:0]O_RXD_3;\r
162reg [7:0]O_RXD_4;\r
163reg [7:0]O_RXD_5;\r
164reg [7:0]O_RXD_6;\r
165\r
166reg W_rxd_mask;\r
167always@(posedge W_scan_seq_pls) \r
168 W_rxd_mask <= ~W_conf_ent;\r
169\r
170always@(negedge W_RXWT)\r
171begin\r
172 if(W_rxd_mask)begin\r
173 case(W_byte_cnt)\r
174 3: O_RXD_1 <= W_RXD_DAT;\r
175 4: O_RXD_2 <= W_RXD_DAT;\r
176 5: O_RXD_3 <= W_RXD_DAT;\r
177 6: O_RXD_4 <= W_RXD_DAT;\r
178 7: O_RXD_5 <= W_RXD_DAT;\r
179 8: O_RXD_6 <= W_RXD_DAT;\r
180 default:;\r
181 endcase\r
182 end\r
183end\r
184\r
185endmodule\r
186\r
187module txd_commnd_EZ(\r
188\r
189I_CLK,\r
190I_RSTn,\r
191I_BYTE_CNT,\r
192I_MODE,\r
193I_VIB_SW,\r
194I_VIB_DAT,\r
195I_RXD_DAT,\r
196O_TXD_DAT,\r
197O_TYPE,\r
198O_CONF_ENT\r
199\r
200);\r
201\r
202input I_CLK,I_RSTn;\r
203input [3:0]I_BYTE_CNT;\r
204input [2:0]I_MODE;\r
205input [1:0]I_VIB_SW;\r
206input [7:0]I_VIB_DAT;\r
207input [7:0]I_RXD_DAT;\r
208output [7:0]O_TXD_DAT;\r
209output O_TYPE;\r
210output O_CONF_ENT;\r
211\r
212reg [7:0]O_TXD_DAT;\r
213\r
214assign O_TYPE = 1'b1;\r
215assign O_CONF_ENT = 1'b0;\r
216always@(posedge I_CLK or negedge I_RSTn)\r
217begin\r
218 if(! I_RSTn)begin\r
219 O_TXD_DAT <= 8'h00;\r
220 end\r
221 else begin\r
222 case(I_BYTE_CNT)\r
223 0:O_TXD_DAT <= 8'h01;\r
224 1:O_TXD_DAT <= 8'h42;\r
225 3:begin\r
226 if(I_VIB_SW) O_TXD_DAT <= 8'h40;\r
227 else O_TXD_DAT <= 8'h00;\r
228 end\r
229 4:begin\r
230 if(I_VIB_SW) O_TXD_DAT <= 8'h01;\r
231 else O_TXD_DAT <= 8'h00;\r
232 end\r
233 default: O_TXD_DAT <= 8'h00;\r
234 endcase\r
235 end\r
236end\r
237\r
238endmodule\r
239\r
240module txd_commnd(\r
241\r
242\r
243I_CLK,\r
244I_RSTn,\r
245I_BYTE_CNT,\r
246I_MODE,\r
247I_VIB_SW,\r
248I_VIB_DAT,\r
249I_RXD_DAT,\r
250O_TXD_DAT,\r
251O_TYPE,\r
252O_CONF_ENT\r
253\r
254);\r
255\r
256input I_CLK,I_RSTn;\r
257input [3:0]I_BYTE_CNT;\r
258input [2:0]I_MODE;\r
259input [1:0]I_VIB_SW;\r
260input [7:0]I_VIB_DAT;\r
261input [7:0]I_RXD_DAT;\r
262output [7:0]O_TXD_DAT;\r
263output O_TYPE;\r
264output O_CONF_ENT;\r
265\r
266reg [7:0]O_TXD_DAT;\r
267reg [2:0]conf_state;\r
268reg conf_entry;\r
269reg conf_done;\r
270reg pad_status;\r
271reg pad_id;\r
272\r
273assign O_TYPE = pad_id;\r
274assign O_CONF_ENT = conf_entry;\r
275\r
276always@(posedge I_CLK or negedge I_RSTn)\r
277begin\r
278 if(! I_RSTn) pad_id <= 1'b0; \r
279 else begin\r
280 if(I_BYTE_CNT==2)begin\r
281 case(I_RXD_DAT) //------ GET TYPE(Byte_SEQ)\r
282 8'h23: pad_id <= 1'b1;\r
283 8'h41: pad_id <= 1'b0;\r
284 8'h53: pad_id <= 1'b1;\r
285 8'h73: pad_id <= 1'b1;\r
286 8'hE3: pad_id <= 1'b1;\r
287 8'hF3: pad_id <= 1'b1;\r
288 default: pad_id <= 1'b0;\r
289 endcase\r
290 end\r
291 end\r
292end\r
293\r
294always@(posedge I_CLK or negedge I_RSTn)\r
295begin\r
296 if(! I_RSTn)begin\r
297 O_TXD_DAT <= 8'h00;\r
298 conf_entry <= 1'b0;\r
299 conf_done <= 1'b1;\r
300 conf_state <= 0;\r
301 pad_status <= 0; \r
302 end\r
303 else begin\r
304//---------- nomal mode --------------------------------------------------------\r
305//----------------- read_data_and_vibrate_ex 01,42,00,WW,PP(,00,00,00,00)\r
306// --,ID,SS,XX,XX(,XX,XX,XX,XX)\r
307 if(~conf_entry)begin\r
308 case(I_BYTE_CNT)\r
309 0:O_TXD_DAT <= 8'h01;\r
310 1:O_TXD_DAT <= 8'h42;\r
311 3:begin\r
312 if(pad_status)begin\r
313 if(I_VIB_SW[0]) O_TXD_DAT <= 8'h01;\r
314 else O_TXD_DAT <= 8'h00;\r
315 end\r
316 else begin\r
317 if(I_VIB_SW[0]|I_VIB_SW[1]) O_TXD_DAT <= 8'h40;\r
318 else O_TXD_DAT <= 8'h00; \r
319 end\r
320 end\r
321 4:begin\r
322 if(pad_status)begin\r
323 if(I_VIB_SW[1]) O_TXD_DAT <= I_VIB_DAT;\r
324 else O_TXD_DAT <= 8'h00;\r
325 end\r
326 else begin\r
327 if(I_VIB_SW[0]|I_VIB_SW[1]) O_TXD_DAT <= 8'h01;\r
328 else O_TXD_DAT <= 8'h00; \r
329 end\r
330 if(pad_id==0)begin\r
331 if(conf_state == 0)\r
332 conf_entry <= 1'b1;\r
333 end\r
334 end\r
335 8:begin\r
336 O_TXD_DAT <= 8'h00;\r
337 if(pad_id==1)begin\r
338 if(conf_state == 0)\r
339 conf_entry <= 1'b1;\r
340 end\r
341 end \r
342 default: O_TXD_DAT <= 8'h00;\r
343 endcase\r
344 end\r
345//---------- confg mode --------------------------------------------------------\r
346 else begin\r
347 case(conf_state)\r
348 //-------- config_mode_enter (43): 01,43,00,01,00(,00 x 4 or XX x 16)\r
349 // --,ID,SS,XX,XX(,XX x 4 or XX x 16) \r
350 0:begin\r
351 case(I_BYTE_CNT)\r
352 0:begin\r
353 O_TXD_DAT <= 8'h01;\r
354 conf_done <= 1'b0;\r
355 end\r
356 1:O_TXD_DAT <= 8'h43;\r
357 3:O_TXD_DAT <= 8'h01;\r
358 4:begin\r
359 O_TXD_DAT <= 8'h00;\r
360 if(pad_id==0)begin\r
361 conf_state <= 1; \r
362 end\r
363 end\r
364 8:begin\r
365 O_TXD_DAT <= 8'h00;\r
366 if(pad_id==1)begin\r
367 conf_state <= 1; \r
368 end\r
369 end \r
370 default:O_TXD_DAT <= 8'h00;\r
371 endcase\r
372 end\r
373 //-------- set_mode_and_lock (44): 01,44,00,XX,YY,00,00,00,00\r
374 // \r
375 1:begin\r
376 case(I_BYTE_CNT)\r
377 0:O_TXD_DAT <= 8'h01;\r
378 1:O_TXD_DAT <= 8'h44;\r
379 2:begin\r
380 O_TXD_DAT <= 8'h00;\r
381 if(I_RXD_DAT == 8'hF3)begin\r
382 conf_done <= 1'b0;\r
383 pad_status <= 1'b1;\r
384 end\r
385 else begin\r
386 conf_done <= 1'b1;\r
387 pad_status <= 1'b0;\r
388 end\r
389 end\r
390 3:O_TXD_DAT <= 8'h01;\r
391 4:begin\r
392 O_TXD_DAT <= 8'h03;\r
393 if(pad_id==0 && conf_done==1'b1)begin\r
394 conf_state <= 7;\r
395 conf_entry <= 1'b0;\r
396 end\r
397 end\r
398 8:begin\r
399 O_TXD_DAT <= 8'h00;\r
400 conf_state <= 3;\r
401 if(pad_id==1 && conf_done==1'b1)begin\r
402 conf_state <= 7;\r
403 conf_entry <= 1'b0;\r
404 end \r
405 end \r
406 default:O_TXD_DAT <= 8'h00;\r
407 endcase\r
408 end\r
409 //-------- query_model_and_mode (45): 01,45,00,5A,5A,5A,5A,5A,5A\r
410 // FF,F3,5A,TT,02,MM,VV,01,00\r
411/*\r
412 1:begin\r
413 case(I_BYTE_CNT)\r
414 0:O_TXD_DAT <= 8'h01;\r
415 1:O_TXD_DAT <= 8'h45;\r
416 2:begin\r
417 O_TXD_DAT <= 8'h00;\r
418 conf_done <= (I_RXD_DAT == 8'hF3)? 1'b0:1'b1;\r
419 end\r
420 4:begin\r
421 O_TXD_DAT <= 8'h00;\r
422 if(I_RXD_DAT==8'h01 || I_RXD_DAT==8'h03) pad_status <= 1;\r
423 if(pad_id==0 && conf_done==1'b1)begin\r
424 conf_state <= 7;\r
425 conf_entry <= 1'b0;\r
426 end\r
427 end\r
428 8:begin\r
429 O_TXD_DAT <= 8'h00;\r
430 conf_state <= 2;\r
431 if(pad_id==1 && conf_done==1'b1)begin\r
432 conf_state <= 7;\r
433 conf_entry <= 1'b0;\r
434 end \r
435 end \r
436 default:O_TXD_DAT <= 8'h00;\r
437 endcase\r
438 end\r
439 //-------- set_mode_and_lock (44): 01,44,00,XX,YY,00,00,00,00\r
440 // --,F3,5A,00,00,00,00,00,00\r
441 2:begin\r
442 case(I_BYTE_CNT)\r
443 0:O_TXD_DAT <= 8'h01;\r
444 1:O_TXD_DAT <= 8'h44;\r
445 3:O_TXD_DAT <= 8'h01;\r
446 4:O_TXD_DAT <= 8'h03;\r
447 8:begin\r
448 O_TXD_DAT <= 8'h00;\r
449 conf_state<= 3;\r
450 end\r
451 default:O_TXD_DAT <= 8'h00;\r
452 endcase\r
453 end\r
454*/\r
455 //-------- vibration_enable (4D): 01,4D,00,00,01,FF,FF,FF,FF\r
456 // --,F3,5A,XX,YY,FF,FF,FF,FF\r
457 3:begin\r
458 case(I_BYTE_CNT)\r
459 0:O_TXD_DAT <= 8'h01;\r
460 1:O_TXD_DAT <= 8'h4D;\r
461 2,3:O_TXD_DAT <= 8'h00;\r
462 4:O_TXD_DAT <= 8'h01;\r
463 8:begin\r
464 O_TXD_DAT <= 8'hFF; \r
465 conf_state<= 6;\r
466 end\r
467 default:O_TXD_DAT <= 8'hFF;\r
468 endcase\r
469 end\r
470 //-------- config_mode_exit (43): 01,43,00,00,00,00,00,00,00\r
471 // --,F3,5A,00,00,00,00,00,00\r
472 6:begin\r
473 case(I_BYTE_CNT)\r
474 0:O_TXD_DAT <= 8'h01;\r
475 1:O_TXD_DAT <= 8'h43;\r
476 2,3:O_TXD_DAT <= 8'h00;\r
477 8:begin\r
478 O_TXD_DAT <= 8'h00;\r
479 conf_state<= 7;\r
480 conf_entry<= 1'b0;\r
481 conf_done <= 1'b1; \r
482 end\r
483 default:O_TXD_DAT <= 8'h00;\r
484 endcase\r
485 end\r
486 default:;\r
487 endcase\r
488 end\r
489 end\r
490end\r
491\r
492endmodule\r
493\r
494module ps_pls_gan(\r
495\r
496I_CLK,\r
497I_RSTn,\r
498I_TYPE,\r
499\r
500O_SCAN_SEQ_PLS,\r
501O_RXWT,\r
502O_TXWT,\r
503O_TXSET,\r
504O_TXEN,\r
505O_psCLK,\r
506O_psSEL,\r
507O_byte_cnt,\r
508\r
509Timer\r
510\r
511);\r
512\r
513parameter Timer_size = `Timer_siz;\r
514\r
515input I_CLK,I_RSTn;\r
516input I_TYPE;\r
517output O_SCAN_SEQ_PLS;\r
518output O_RXWT;\r
519output O_TXWT;\r
520output O_TXSET;\r
521output O_TXEN;\r
522output O_psCLK;\r
523output O_psSEL;\r
524output [3:0]O_byte_cnt;\r
525\r
526output [Timer_size-1:0]Timer;\r
527reg [Timer_size-1:0]Timer;\r
528\r
529reg O_SCAN_SEQ_PLS;\r
530reg RXWT;\r
531reg TXWT;\r
532reg TXSET;\r
533reg psCLK_gate;\r
534reg psSEL;\r
535reg [3:0]O_byte_cnt;\r
536\r
537always@(posedge I_CLK or negedge I_RSTn)\r
538begin\r
539 if(! I_RSTn) Timer <= 0;\r
540 else Timer <= Timer+1;\r
541end\r
542\r
543always@(posedge I_CLK or negedge I_RSTn)\r
544begin\r
545 if(! I_RSTn) \r
546 O_SCAN_SEQ_PLS <= 0;\r
547 else begin\r
548 if(Timer == 0) O_SCAN_SEQ_PLS <= 1; \r
549 else O_SCAN_SEQ_PLS <= 0; \r
550 end\r
551end\r
552\r
553always@(posedge I_CLK or negedge I_RSTn)\r
554begin\r
555 if(! I_RSTn)\r
556 begin\r
557 psCLK_gate <= 1;\r
558 RXWT <= 0;\r
559 TXWT <= 0;\r
560 TXSET <= 0;\r
561 end\r
562 else begin\r
563 case(Timer[4:0])\r
564 6: TXSET <= 1;\r
565 8: TXSET <= 0;\r
566 9: TXWT <= 1;\r
567 11: TXWT <= 0;\r
568 12: psCLK_gate <= 0;\r
569 20: psCLK_gate <= 1;\r
570 21: RXWT <= 1;\r
571 23: RXWT <= 0;\r
572 default:;\r
573 endcase\r
574 end\r
575end\r
576\r
577always@(posedge I_CLK or negedge I_RSTn)\r
578begin \r
579 if(! I_RSTn)\r
580 psSEL <= 1;\r
581 else begin \r
582 if(O_SCAN_SEQ_PLS == 1)\r
583 psSEL <= 0;\r
584 else if((I_TYPE == 0)&&(Timer == 158))\r
585 psSEL <= 1;\r
586 else if((I_TYPE == 1)&&(Timer == 286))\r
587 psSEL <= 1;\r
588 end\r
589end\r
590\r
591always@(posedge I_CLK or negedge I_RSTn)\r
592begin \r
593 if(! I_RSTn)\r
594 O_byte_cnt <= 0;\r
595 else begin\r
596 if( O_SCAN_SEQ_PLS == 1)\r
597 O_byte_cnt <= 0;\r
598 else begin \r
599 if( Timer[4:0] == 5'b11111)begin\r
600 if(I_TYPE == 0 && O_byte_cnt == 5)\r
601 O_byte_cnt <= O_byte_cnt;\r
602 else if(I_TYPE == 1 && O_byte_cnt == 9)\r
603 O_byte_cnt <= O_byte_cnt;\r
604 else\r
605 O_byte_cnt <= O_byte_cnt+1;\r
606 end \r
607 end\r
608 end\r
609end\r
610\r
611assign O_psCLK = psCLK_gate | I_CLK | psSEL;\r
612assign O_psSEL = psSEL;\r
613assign O_RXWT = ~psSEL&RXWT;\r
614assign O_TXSET = ~psSEL&TXSET;\r
615assign O_TXWT = ~psSEL&TXWT;\r
616assign O_TXEN = ~psSEL&(~psCLK_gate);\r
617\r
618endmodule\r
619\r
620module ps_rxd(\r
621\r
622I_CLK,\r
623I_RSTn, \r
624I_WT,\r
625I_psRXD,\r
626O_RXD_DAT\r
627\r
628);\r
629\r
630input I_CLK,I_RSTn,I_WT;\r
631input I_psRXD;\r
632output [7:0]O_RXD_DAT;\r
633reg [7:0]O_RXD_DAT;\r
634reg [7:0]sp;\r
635\r
636always@(posedge I_CLK or negedge I_RSTn)\r
637 if(! I_RSTn) sp <= 1;\r
638 else sp <= { I_psRXD, sp[7:1]};\r
639always@(posedge I_WT or negedge I_RSTn)\r
640 if(! I_RSTn) O_RXD_DAT <= 1;\r
641 else O_RXD_DAT <= sp;\r
642\r
643endmodule\r
644\r
645module ps_txd(\r
646\r
647I_CLK,\r
648I_RSTn,\r
649I_WT,\r
650I_EN,\r
651I_TXD_DAT,\r
652O_psTXD\r
653\r
654);\r
655\r
656input I_CLK,I_RSTn;\r
657input I_WT,I_EN;\r
658input [7:0]I_TXD_DAT;\r
659output O_psTXD;\r
660reg O_psTXD;\r
661reg [7:0]ps;\r
662\r
663always@(negedge I_CLK or negedge I_RSTn)\r
664begin\r
665 if(! I_RSTn)begin \r
666 O_psTXD <= 1;\r
667 ps <= 0;\r
668 end\r
669 else begin\r
670 if(I_WT)\r
671 ps <= I_TXD_DAT;\r
672 else begin\r
673 if(I_EN)begin\r
674 O_psTXD <= ps[0];\r
675 ps <= {1'b1, ps[7:1]};\r
676 end\r
677 else begin\r
678 O_psTXD <= 1'd1;\r
679 ps <= ps;\r
680 end\r
681 end\r
682 end \r
683end\r
684\r
685endmodule
Arcade Games for FPGAs (currently only galaxian)
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