cvs.zerfleddert.de Git - fpga-games/blame_incremental - galaxian/src/dcm.v

// Module mc_dcm
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI
// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.89 ns
`timescale 1ns / 1ps

module mc_dcm(CLKIN_IN,
           RST_IN,
           CLKFX_OUT,
           CLKIN_IBUFG_OUT,
           CLK0_OUT,
           LOCKED_OUT);

    input CLKIN_IN;
    input RST_IN;
   output CLKFX_OUT;
   output CLKIN_IBUFG_OUT;
   output CLK0_OUT;
   output LOCKED_OUT;

   wire CLKFB_IN;
   wire CLKFX_BUF;
   wire CLKIN_IBUFG;
   wire CLK0_BUF;
   wire GND_BIT;

   assign GND_BIT = 0;
   assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
   assign CLK0_OUT = CLKFB_IN;
   BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
                         .O(CLKFX_OUT));
   IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
                           .O(CLKIN_IBUFG));
   BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
                        .O(CLKFB_IN));
   DCM_SP DCM_SP_INST (.CLKFB(CLKFB_IN),
                       .CLKIN(CLKIN_IBUFG),
                       .DSSEN(GND_BIT),
                       .PSCLK(GND_BIT),
                       .PSEN(GND_BIT),
                       .PSINCDEC(GND_BIT),
                       .RST(RST_IN),
                       .CLKDV(),
                       .CLKFX(CLKFX_BUF),
                       .CLKFX180(),
                       .CLK0(CLK0_BUF),
                       .CLK2X(),
                       .CLK2X180(),
                       .CLK90(),
                       .CLK180(),
                       .CLK270(),
                       .LOCKED(LOCKED_OUT),
                       .PSDONE(),
                       .STATUS());
   defparam DCM_SP_INST.CLK_FEEDBACK = "1X";
   defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
   defparam DCM_SP_INST.CLKFX_DIVIDE = 13;
   defparam DCM_SP_INST.CLKFX_MULTIPLY = 4;
   defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
   defparam DCM_SP_INST.CLKIN_PERIOD = 8.000;
   defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
   defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
   defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
   defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
   defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
   defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
   defparam DCM_SP_INST.PHASE_SHIFT = 0;
   defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";
endmodule
Commit	Line	Data
	1	// Module mc_dcm
	2	// Generated by Xilinx Architecture Wizard
	3	// Written for synthesis tool: XST
	4	// Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI
	5	// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.89 ns
	6	`timescale 1ns / 1ps
	7
	8	module mc_dcm(CLKIN_IN,
	9	RST_IN,
	10	CLKFX_OUT,
	11	CLKIN_IBUFG_OUT,
	12	CLK0_OUT,
	13	LOCKED_OUT);
	14
	15	input CLKIN_IN;
	16	input RST_IN;
	17	output CLKFX_OUT;
	18	output CLKIN_IBUFG_OUT;
	19	output CLK0_OUT;
	20	output LOCKED_OUT;
	21
	22	wire CLKFB_IN;
	23	wire CLKFX_BUF;
	24	wire CLKIN_IBUFG;
	25	wire CLK0_BUF;
	26	wire GND_BIT;
	27
	28	assign GND_BIT = 0;
	29	assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
	30	assign CLK0_OUT = CLKFB_IN;
	31	BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
	32	.O(CLKFX_OUT));
	33	IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
	34	.O(CLKIN_IBUFG));
	35	BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
	36	.O(CLKFB_IN));
	37	DCM_SP DCM_SP_INST (.CLKFB(CLKFB_IN),
	38	.CLKIN(CLKIN_IBUFG),
	39	.DSSEN(GND_BIT),
	40	.PSCLK(GND_BIT),
	41	.PSEN(GND_BIT),
	42	.PSINCDEC(GND_BIT),
	43	.RST(RST_IN),
	44	.CLKDV(),
	45	.CLKFX(CLKFX_BUF),
	46	.CLKFX180(),
	47	.CLK0(CLK0_BUF),
	48	.CLK2X(),
	49	.CLK2X180(),
	50	.CLK90(),
	51	.CLK180(),
	52	.CLK270(),
	53	.LOCKED(LOCKED_OUT),
	54	.PSDONE(),
	55	.STATUS());
	56	defparam DCM_SP_INST.CLK_FEEDBACK = "1X";
	57	defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
	58	defparam DCM_SP_INST.CLKFX_DIVIDE = 13;
	59	defparam DCM_SP_INST.CLKFX_MULTIPLY = 4;
	60	defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
	61	defparam DCM_SP_INST.CLKIN_PERIOD = 8.000;
	62	defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
	63	defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
	64	defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
	65	defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
	66	defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
	67	defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
	68	defparam DCM_SP_INST.PHASE_SHIFT = 0;
	69	defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";
	70	endmodule