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1 | //===============================================================================\r | |
2 | // FPGA MOONCRESTA SOUND I/F\r | |
3 | //\r | |
4 | // Version : 1.00\r | |
5 | //\r | |
6 | // Copyright(c) 2004 Katsumi Degawa , All rights reserved\r | |
7 | //\r | |
8 | // Important !\r | |
9 | //\r | |
10 | // This program is freeware for non-commercial use. \r | |
11 | // An author does no guarantee about this program.\r | |
12 | // You can use this under your own risk.\r | |
13 | //\r | |
14 | //================================================================================\r | |
15 | \r | |
16 | \r | |
17 | module mc_sound_a(\r | |
18 | \r | |
19 | I_CLK_12M,\r | |
20 | I_CLK_6M,\r | |
21 | I_H_CNT1,\r | |
22 | I_BD,\r | |
23 | I_PITCHn,\r | |
24 | I_VOL1,\r | |
25 | I_VOL2,\r | |
26 | \r | |
27 | O_SDAT,\r | |
28 | O_DO\r | |
29 | \r | |
30 | );\r | |
31 | \r | |
32 | input I_CLK_12M;\r | |
33 | input I_CLK_6M;\r | |
34 | input I_H_CNT1;\r | |
35 | input [7:0]I_BD;\r | |
36 | input I_PITCHn;\r | |
37 | input I_VOL1;\r | |
38 | input I_VOL2;\r | |
39 | \r | |
40 | output [3:0]O_DO;\r | |
41 | output [7:0]O_SDAT;\r | |
42 | \r | |
43 | reg W_PITCHn;\r | |
44 | reg W_89K_LDn;\r | |
45 | reg [7:0]W_89K_Q;\r | |
46 | reg [7:0]W_89K_LDATA;\r | |
47 | reg [3:0]W_6T_Q;\r | |
48 | \r | |
49 | always@(posedge I_CLK_12M) \r | |
50 | begin\r | |
51 | W_PITCHn <= I_PITCHn;\r | |
52 | W_89K_LDn <= ~(&W_89K_Q[7:0]);\r | |
53 | end\r | |
54 | \r | |
55 | // Parts 9J\r | |
56 | always@(posedge W_PITCHn) W_89K_LDATA <= I_BD;\r | |
57 | \r | |
58 | always@(posedge I_H_CNT1)\r | |
59 | begin\r | |
60 | if(~W_89K_LDn)\r | |
61 | W_89K_Q <= W_89K_LDATA;\r | |
62 | else\r | |
63 | W_89K_Q <= W_89K_Q + 1; \r | |
64 | end\r | |
65 | \r | |
66 | always@(negedge W_89K_LDn) W_6T_Q <= W_6T_Q + 1;\r | |
67 | assign O_DO = W_6T_Q;\r | |
68 | \r | |
69 | reg [7:0]W_SDAT0;\r | |
70 | reg [7:0]W_SDAT2;\r | |
71 | reg [7:0]W_SDAT3;\r | |
72 | always@(posedge I_CLK_6M)\r | |
73 | begin\r | |
74 | W_SDAT0 <= W_6T_Q[0]==1'b0 ? 8'd0 : 8'd42 ;\r | |
75 | W_SDAT2 <= W_6T_Q[2]==1'b0 ? 8'd0 : I_VOL1 ? 8'd105 : 8'd57 ;\r | |
76 | W_SDAT3 <= W_6T_Q[3]==1'b0 ? 8'd0 : I_VOL2 ? 8'd72 : 8'd0 ;\r | |
77 | end\r | |
78 | \r | |
79 | assign O_SDAT = W_SDAT0 + W_SDAT2 + W_SDAT3 + 8'd20 ;\r | |
80 | \r | |
81 | \r | |
82 | endmodule |