impact 11 renamed the intel flash...

[fpga-games] / galaxian / src / mc_stars.v

//===============================================================================\r
// FPGA MOONCRESTA STARS\r
//\r
// Version : 2.00\r
//\r
// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
//\r
// Important !\r
//\r
// This program is freeware for non-commercial use. \r
// An author does no guarantee about this program.\r
// You can use this under your own risk.\r
//\r
// 2004- 9-22 \r
//================================================================================\r
\r
\r
module mc_stars(\r
\r
I_CLK_18M,\r
I_CLK_6M,\r
I_H_FLIP,\r
I_V_SYNC,\r
I_8HF,\r
I_256HnX,\r
I_1VF,\r
I_2V,\r
I_STARS_ON,\r
I_STARS_OFFn,\r
\r
O_R,\r
O_G,\r
O_B,\r
O_NOISE\r
\r
);\r
\r
input  I_CLK_18M;\r
input  I_CLK_6M;\r
input  I_H_FLIP;\r
input  I_V_SYNC;\r
input  I_8HF;\r
input  I_256HnX;\r
input  I_1VF;\r
input  I_2V;\r
input  I_STARS_ON;\r
input  I_STARS_OFFn;\r
\r
output [2:0]O_R;\r
output [2:0]O_G;\r
output [1:0]O_B;\r
output O_NOISE;\r
\r
wire    W_V_SYNCn = ~I_V_SYNC;\r
\r
wire    CLK_1C = ~(I_CLK_18M & I_CLK_6M & W_V_SYNCn & I_256HnX);\r
\r
reg     W_1C_Q1,W_1C_Q2;\r
always@(posedge CLK_1C or negedge W_V_SYNCn)\r
begin\r
   if(W_V_SYNCn==1'b0)begin\r
      W_1C_Q1 <= 1'b0;\r
      W_1C_Q2 <= 1'b0;\r
   end\r
   else begin\r
      W_1C_Q1 <= 1'b1;\r
      W_1C_Q2 <= W_1C_Q1;\r
   end\r
end\r
\r
wire    CLK_1AB = ~(CLK_1C |(~(I_H_FLIP|W_1C_Q2))) ;\r
\r
reg     [15:0]W_1AB_Q;\r
reg     W_2D_Qn;\r
wire    W_3B = W_2D_Qn^W_1AB_Q[4];\r
\r
always@(posedge CLK_1AB or negedge I_STARS_ON)\r
begin\r
   if(I_STARS_ON==1'b0)begin\r
      W_1AB_Q <= 0;\r
      W_2D_Qn <= 1'b1;\r
   end\r
   else begin\r
      W_1AB_Q <= {W_1AB_Q[14:0],W_3B};\r
      W_2D_Qn <= ~W_1AB_Q[15];\r
   end\r
end\r
\r
wire    W_2A = ~(& W_1AB_Q[7:0]);\r
wire    W_4P = ~(( I_8HF ^ I_1VF ) & W_2D_Qn & I_STARS_OFFn);\r
\r
assign  O_R[2] = 1'b0 ; \r
assign  O_R[1] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[8] ; \r
assign  O_R[0] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[9] ; \r
\r
assign  O_G[2] = 1'b0 ; \r
assign  O_G[1] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[10] ; \r
assign  O_G[0] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[11] ; \r
\r
assign  O_B[1] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[12] ; \r
assign  O_B[0] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[13] ; \r
\r
reg     noise;\r
always@(posedge I_2V) noise <= W_2D_Qn ;\r
assign  O_NOISE = noise ;\r
\r
\r
endmodule