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1 | //===============================================================================\r | |
2 | // FPGA MOONCRESTA LOGIC IP MODULE\r | |
3 | //\r | |
4 | // Version : 1.00\r | |
5 | //\r | |
6 | // Copyright(c) 2004 Katsumi Degawa , All rights reserved\r | |
7 | //\r | |
8 | // Important !\r | |
9 | //\r | |
10 | // This program is freeware for non-commercial use. \r | |
11 | // An author does no guarantee about this program.\r | |
12 | // You can use this under your own risk.\r | |
13 | //\r | |
14 | //================================================================================\r | |
15 | \r | |
16 | \r | |
17 | //================================================\r | |
18 | // 74xx138\r | |
19 | // 3-to-8 line decoder\r | |
20 | //================================================\r | |
21 | module logic_74xx138(\r | |
22 | \r | |
23 | I_G1,\r | |
24 | I_G2a,\r | |
25 | I_G2b,\r | |
26 | I_Sel,\r | |
27 | O_Q\r | |
28 | \r | |
29 | );\r | |
30 | \r | |
31 | input I_G1,I_G2a,I_G2b;\r | |
32 | input [2:0]I_Sel;\r | |
33 | output [7:0]O_Q;\r | |
34 | \r | |
35 | reg [7:0]O_Q;\r | |
36 | wire [2:0]I_G = {I_G1,I_G2a,I_G2b};\r | |
37 | always@(I_G or I_Sel or O_Q)\r | |
38 | begin\r | |
39 | if(I_G == 3'b100 )begin\r | |
40 | case(I_Sel)\r | |
41 | 3'b000: O_Q = 8'b11111110;\r | |
42 | 3'b001: O_Q = 8'b11111101;\r | |
43 | 3'b010: O_Q = 8'b11111011;\r | |
44 | 3'b011: O_Q = 8'b11110111;\r | |
45 | 3'b100: O_Q = 8'b11101111;\r | |
46 | 3'b101: O_Q = 8'b11011111;\r | |
47 | 3'b110: O_Q = 8'b10111111;\r | |
48 | 3'b111: O_Q = 8'b01111111;\r | |
49 | endcase\r | |
50 | end\r | |
51 | else begin\r | |
52 | O_Q = 8'b11111111;\r | |
53 | end\r | |
54 | end\r | |
55 | \r | |
56 | endmodule\r | |
57 | \r | |
58 | //================================================\r | |
59 | // 74xx139\r | |
60 | // 2-to-4 line decoder\r | |
61 | //================================================\r | |
62 | module logic_74xx139(\r | |
63 | \r | |
64 | I_G,\r | |
65 | I_Sel,\r | |
66 | O_Q\r | |
67 | \r | |
68 | );\r | |
69 | \r | |
70 | input I_G;\r | |
71 | input [1:0]I_Sel;\r | |
72 | output [3:0]O_Q;\r | |
73 | \r | |
74 | reg [3:0]O_Q;\r | |
75 | always@(I_G or I_Sel or O_Q)\r | |
76 | begin\r | |
77 | if(I_G == 1'b0 )begin\r | |
78 | case(I_Sel)\r | |
79 | 2'b00: O_Q = 4'b1110;\r | |
80 | 2'b01: O_Q = 4'b1101;\r | |
81 | 2'b10: O_Q = 4'b1011;\r | |
82 | 2'b11: O_Q = 4'b0111;\r | |
83 | endcase\r | |
84 | end\r | |
85 | else begin\r | |
86 | O_Q = 4'b1111;\r | |
87 | end\r | |
88 | end\r | |
89 | \r | |
90 | endmodule\r |