change timing for rom access

[fpga-games] / galaxian / src / mc_top.v

diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v
index c382b640ee6ffd53a20bce5f67cb8093cd51cac8..08d25de4ef664de7ede434cb4ca714faff45c9d7 100644 (file)
--- a/galaxian/src/mc_top.v
+++ b/galaxian/src/mc_top.v
@@ -95,9 +95,9 @@ output  O_SOUND_OUT_L;
 output  O_SOUND_OUT_R;\r
 \r
 //    VGA (VIDEO) IF\r
-output [2:0]O_VGA_R;\r
-output [2:0]O_VGA_G;\r
-output [1:0]O_VGA_B;\r
+output [3:0]O_VGA_R;\r
+output [3:0]O_VGA_G;\r
+output [3:0]O_VGA_B;\r
 output O_VGA_H_SYNCn;\r
 output O_VGA_V_SYNCn;\r
 \r
@@ -107,11 +107,13 @@ wire   I_CLK_18432M;
 wire   W_CLK_12M,WB_CLK_12M;\r
 wire   W_CLK_6M,WB_CLK_6M;\r
 wire   W_STARS_CLK;\r
+wire   W_ROM_CLK;\r
 \r
-dcm clockgen(\r
+mc_dcm clockgen(\r
 .CLKIN_IN(I_CLK_125M),\r
 .RST_IN(! W_RESETn),\r
-.CLKFX_OUT(I_CLK_18432M)\r
+.CLKFX_OUT(I_CLK_18432M),\r
+.CLK0_OUT(W_ROM_CLK)\r
 );\r
 \r
 //------ H&V COUNTER -------------------------\r
@@ -425,8 +427,7 @@ wire   [7:0]ROM_D; // = I_ROM_DB;
 //assign O_ROM_WEn = 1'b1;\r
 \r
 galaxian_roms ROMS(\r
-.I_CLK_18432M(I_CLK_18432M),\r
-.I_CLK_12M(WB_CLK_12M),\r
+.I_ROM_CLK(W_ROM_CLK),\r
 .I_ADDR(ROM_A),\r
 .O_DATA(ROM_D)\r
 );\r
@@ -442,38 +443,34 @@ begin
    seq <= (~clk_d[1] & clk_d[0]) ? 0 : seq+1;\r
    case(seq)\r
       0:begin\r
-        //sound\r
         ROM_A <= W_WAV_A0;\r
         W_CPU_ROM_DO <= ROM_D;\r
         end\r
       2:begin\r
-        //sound\r
         ROM_A <= W_WAV_A1;\r
         W_WAV_D0 <= ROM_D;\r
         end\r
       4:begin\r
-        //sound\r
         ROM_A <= {3'h0,W_A[15:0]};\r
         W_WAV_D1 <= ROM_D;\r
         end\r
       6:begin\r
-        //sound\r
         ROM_A <= W_WAV_A2;\r
         W_CPU_ROM_DO <= ROM_D;\r
         end\r
-      8:W_WAV_D2 <= ROM_D; //sound\r
+      8:W_WAV_D2 <= ROM_D;\r
      10:ROM_A <= {3'h0,W_A[15:0]};\r
      12:W_CPU_ROM_DO <= ROM_D;\r
-     16:ROM_A <= {3'h0,W_A[15:0]};\r
-     18:begin\r
+     14:ROM_A <= {3'h0,W_A[15:0]};\r
+     16:begin\r
         ROM_A <= {3'h0,4'h4,1'b0,W_OBJ_ROM_A};\r
         W_CPU_ROM_DO <= ROM_D;\r
         end\r
-     20:begin\r
+     18:begin\r
         ROM_A <= {3'h0,4'h5,1'b0,W_OBJ_ROM_A};\r
         W_OBJ_ROM_A_D <= ROM_D;\r
         end\r
-     22:begin\r
+     20:begin\r
         ROM_A <= {3'h0,W_A[15:0]};\r
         W_OBJ_ROM_B_D <= ROM_D;\r
         end\r
@@ -621,6 +618,10 @@ mc_vedio_mix MIX(
 \r
 );\r
 \r
+wire [2:0]W_VGA_R;\r
+wire [2:0]W_VGA_G;\r
+wire [1:0]W_VGA_B;\r
+\r
 `ifdef VGA_USE\r
 mc_vga_if  VGA(\r
 \r
@@ -633,9 +634,9 @@ mc_vga_if  VGA(
 .I_H_SYNC(W_H_SYNC),\r
 .I_V_SYNC(W_V_SYNC),\r
 // output\r
-.O_R(O_VGA_R),\r
-.O_G(O_VGA_G),\r
-.O_B(O_VGA_B),\r
+.O_R(W_VGA_R),\r
+.O_G(W_VGA_G),\r
+.O_B(W_VGA_B),\r
 .O_H_SYNCn(O_VGA_H_SYNCn),\r
 .O_V_SYNCn(O_VGA_V_SYNCn)\r
 \r
@@ -643,11 +644,11 @@ mc_vga_if  VGA(
 \r
 `else\r
 \r
-assign O_VGA_R[2:0] = W_R;\r
+assign W_VGA_R[2:0] = W_R;\r
 \r
-assign O_VGA_G[2:0] = W_G;\r
+assign W_VGA_G[2:0] = W_G;\r
 \r
-assign O_VGA_B[1:0] = W_B;\r
+assign W_VGA_B[1:0] = W_B;\r
 \r
 //assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ;  //  AKIDUKI LCD USED\r
 assign O_VGA_H_SYNCn = ~W_H_SYNC ;\r
@@ -655,6 +656,12 @@ assign O_VGA_V_SYNCn = ~W_V_SYNC ;
 \r
 `endif\r
 \r
+assign O_VGA_R[3:0] = {W_VGA_R[0], W_VGA_R[1], W_VGA_R[2], 1'b0};\r
+\r
+assign O_VGA_G[3:0] = {W_VGA_G[0], W_VGA_G[1], W_VGA_G[2], 1'b0};\r
+\r
+assign O_VGA_B[3:0] = {W_VGA_B[0], W_VGA_B[1], 2'b0};\r
+\r
 wire   [7:0]W_SDAT_A;\r
 \r
 mc_sound_a MC_SOUND_A(\r