output O_SLDn;\r
\r
reg W_5C_Q;\r
-always@(posedge I_CLK_6M)\r
+always@(negedge I_CLK_6M)\r
W_5C_Q <= I_H_CNT[0];\r
\r
// Parts 4D\r
);\r
\r
reg W_4C1_Q3;\r
-always@(negedge I_CLK_6M) // 2004-9-22 added\r
+always@(posedge I_CLK_6M) // 2004-9-22 added\r
W_4C1_Q3 <= W_4C1_Q[3];\r
\r
reg W_4C2_B;\r