X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/fpga-games/blobdiff_plain/782690d0b2046d5fa0ae296c2fb3f411d668b5dc..49502d5f0b235a30ac00eb83dfefe27ae18cd956:/galaxian/src/roms.v?ds=sidebyside

diff --git a/galaxian/src/roms.v b/galaxian/src/roms.v
index 403302d..84c5a8c 100644
--- a/galaxian/src/roms.v
+++ b/galaxian/src/roms.v
@@ -1,89 +1,60 @@
 module galaxian_roms(
-I_CLK_18432M,
-I_CLK_12M,
+I_ROM_CLK,
 I_ADDR,
 O_DATA
 );
 
-input I_CLK_12M;
-input I_CLK_18432M;
+input I_ROM_CLK;
 input [18:0]I_ADDR;
 output [7:0]O_DATA;
 
 //CPU-Roms
 wire [7:0]U_ROM_D;
-reg [10:0]U_ROM_A;
 
 GALAXIAN_U U_ROM(
-.CLK(I_CLK_12M),
-.ADDR(U_ROM_A),
+.CLK(I_ROM_CLK),
+.ADDR(I_ADDR[10:0]),
 .DATA(U_ROM_D),
 .ENA(1'b1)
 );
 
 wire [7:0]V_ROM_D;
-reg [10:0]V_ROM_A;
 
 GALAXIAN_V V_ROM(
-.CLK(I_CLK_12M),
-.ADDR(V_ROM_A),
+.CLK(I_ROM_CLK),
+.ADDR(I_ADDR[10:0]),
 .DATA(V_ROM_D),
 .ENA(1'b1)
 );
 
 wire [7:0]W_ROM_D;
-reg [10:0]W_ROM_A;
 
 GALAXIAN_W W_ROM(
-.CLK(I_CLK_12M),
-.ADDR(W_ROM_A),
+.CLK(I_ROM_CLK),
+.ADDR(I_ADDR[10:0]),
 .DATA(W_ROM_D),
 .ENA(1'b1)
 );
 
 wire [7:0]Y_ROM_D;
-reg [10:0]Y_ROM_A;
 
 GALAXIAN_Y Y_ROM(
-.CLK(YB_CLK_12M),
-.ADDR(Y_ROM_A),
+.CLK(I_ROM_CLK),
+.ADDR(I_ADDR[10:0]),
 .DATA(Y_ROM_D),
 .ENA(1'b1)
 );
 
 //7L CPU-Rom
 wire [7:0]L_ROM_D;
-reg [10:0]L_ROM_A;
 
 GALAXIAN_7L L_ROM(
-.CLK(LB_CLK_12M),
-.ADDR(L_ROM_A),
+.CLK(I_ROM_CLK),
+.ADDR(I_ADDR[10:0]),
 .DATA(L_ROM_D),
 .ENA(1'b1)
 );
 
-//1K VID-Rom
-wire [7:0]K_ROM_D;
-reg [10:0]K_ROM_A;
-
-GALAXIAN_1K K_ROM(
-.CLK(KB_CLK_12M),
-.ADDR(K_ROM_A),
-.DATA(K_ROM_D),
-.ENA(1'b1)
-);
-
-//1H VID-Rom
-wire [7:0]H_ROM_D;
-reg [10:0]H_ROM_A;
-
-GALAXIAN_1H H_ROM(
-.CLK(HB_CLK_12M),
-.ADDR(H_ROM_A),
-.DATA(H_ROM_D),
-.ENA(1'b1)
-);
-
 reg [7:0]DATA_OUT;
 
 //    address map
@@ -96,42 +67,30 @@ reg [7:0]DATA_OUT;
 // 0x04000 - 0x047FF       1k.bin           VID-ROM
 // 0x05000 - 0x057FF       1h.bin           VID-ROM
 // 0x10000 - 0x3FFFF       mc_wav_2.bin     Sound(Wav)Data
-always @(posedge I_CLK_18432M)
+always@(posedge I_ROM_CLK)
 begin
 	if (I_ADDR <= 18'h7ff) begin
 		//u
-		U_ROM_A <= I_ADDR[10:0];
 		DATA_OUT <= U_ROM_D;
 	end
 	else if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
 		//v
-		V_ROM_A <= I_ADDR[10:0];
 		DATA_OUT <= V_ROM_D;
 	end
 	else if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
 		//w
-		W_ROM_A <= I_ADDR[10:0];
 		DATA_OUT <= W_ROM_D;
 	end
 	else if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
 		//y
-		Y_ROM_A <= I_ADDR[10:0];
 		DATA_OUT <= Y_ROM_D;
 	end
 	else if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
 		//7l
-		L_ROM_A <= I_ADDR[10:0];
 		DATA_OUT <= L_ROM_D;
 	end
-	else if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin
-		//1k
-		K_ROM_A <= I_ADDR[10:0];
-		DATA_OUT <= K_ROM_D;
-	end
-	else if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin
-		//1h
-		H_ROM_A <= I_ADDR[10:0];
-		DATA_OUT <= H_ROM_D;
+	else begin
+		DATA_OUT <= DATA_OUT;
 	end
 end