X-Git-Url: http://cvs.zerfleddert.de/cgi-bin/gitweb.cgi/fpga-games/blobdiff_plain/c3bcc38aaf21ce2036ea66b9e5f764e6d3e7ac7f..4b3ff7d86485dea579af0d8fd983a36a1e9295ea:/galaxian/src/mc_clock.v

diff --git a/galaxian/src/mc_clock.v b/galaxian/src/mc_clock.v
index a88d95c..36925f3 100644
--- a/galaxian/src/mc_clock.v
+++ b/galaxian/src/mc_clock.v
@@ -20,7 +20,8 @@ module mc_clock(
 I_CLK_36M,
 O_CLK_18M,
 O_CLK_12M,
-O_CLK_06M
+O_CLK_06M,
+O_CLK_06Mn
 
 );
 
@@ -28,6 +29,7 @@ input I_CLK_36M;
 output O_CLK_18M;
 output O_CLK_12M;
 output O_CLK_06M;
+output O_CLK_06Mn;
 
 // 2/3 clock divider(duty 33%)
 //I_CLK   1010101010101010101
@@ -42,7 +44,7 @@ initial state = 0;
 initial clk_12m = 0;
 
 // 2/3 clock         (duty 66%)
-always @(negedge I_CLK_36M)
+always @(posedge I_CLK_36M)
 begin
    case (state)
       2'd0: state <= 2'd1;
@@ -52,9 +54,9 @@ begin
    endcase
 
    if (state == 2'd2)
-      clk_12m = 1;
-   else
       clk_12m = 0;
+   else
+      clk_12m = 1;
 end
 
 assign O_CLK_12M = clk_12m;
@@ -68,10 +70,15 @@ assign O_CLK_18M = CLK_18M;
 
 // 1/3 clock divider (duty 50%)
 reg CLK_6M;
+reg CLK_6Mn;
+
 always @(posedge O_CLK_12M)
 begin
    CLK_6M  <= ~CLK_6M;
+   CLK_6Mn <= CLK_6M;
 end
+
 assign O_CLK_06M = CLK_6M;
+assign O_CLK_06Mn = CLK_6Mn;
 
 endmodule