| c5f1f439 |
1 | TTL C:\pocket\test\asm.cpp\r |
| 2 | \r |
| 3 | AREA |.drectve|, DRECTVE\r |
| 4 | DCB "-defaultlib:coredll.lib "\r |
| 5 | DCB "-defaultlib:corelibc.lib "\r |
| 6 | \r |
| 7 | EXPORT |?do_it@@YAXXZ| ; do_it\r |
| 8 | AREA |.pdata|, PDATA\r |
| 9 | |$T222| DCD |?do_it@@YAXXZ|\r |
| 10 | DCD 0x40000100\r |
| 11 | AREA |.text|, CODE\r |
| 12 | |?do_it@@YAXXZ| PROC ; do_it\r |
| 13 | |$M220|\r |
| 14 | \r |
| 15 | mcr p15, 0, r0, c7, c5, 0 ;/* invalidate i cache & BTB */\r |
| 16 | ; CPWAIT r0\r |
| 17 | mrc p15, 0, r0, c2, c0, 0\r |
| 18 | mov r0, r0\r |
| 19 | sub pc, pc, #4 \r |
| 20 | ; ldr r9, =0xa1300100\r |
| 21 | \r |
| 22 | mov r9, r1 ; add r9, r1, #0x100 \r |
| 23 | ldr r5, =0xa0000100 ; ldr r5, =0xa0000100\r |
| 24 | ldr r7, =0xa0100000\r |
| 25 | label ldr r8, [r9]\r |
| 26 | str r8, [r5]\r |
| 27 | add r9, r9, #4 \r |
| 28 | add r5, r5, #4 \r |
| 29 | cmp r5, r7\r |
| 30 | blt label\r |
| 31 | \r |
| 32 | crash b crash\r |
| 33 | \r |
| 34 | MOV r4, #0xA0000000\r |
| 35 | add r2,r4,#0x8000\r |
| 36 | \r |
| 37 | mov r11,r2\r |
| 38 | ldr r10,=337\r |
| 39 | \r |
| 40 | ; mcr p15, 0, r0, c7, c10, 4 ;/* drain the write buffer*/\r |
| 41 | \r |
| 42 | ; CPWAIT r0\r |
| 43 | ; mrc p15, 0, r0, c2, c0, 0\r |
| 44 | ; mov r0, r0\r |
| 45 | ; sub pc, pc, #4 \r |
| 46 | \r |
| 47 | \r |
| 48 | mcr p15, 0, r0, c8, c7, 0x00 ;/* invalidate I+D TLB */\r |
| 49 | ; CPWAIT r0\r |
| 50 | mrc p15, 0, r0, c2, c0, 0\r |
| 51 | mov r0, r0\r |
| 52 | sub pc, pc, #4 \r |
| 53 | \r |
| 54 | ; //; they skipped this, unnecessary? seems like we need to do this\r |
| 55 | mcr p15, 0, r0, c7, c5, 0 ;/* invalidate i cache & BTB */\r |
| 56 | \r |
| 57 | ; S bit set, p and d bit set (no 26 bit mode)\r |
| 58 | ; mov r3, #0x120 ; xscale says p needs to be 0 ???\r |
| 59 | ; mcr p15, 0, r3, c1, c0, 0 ;/* disable the MMU */\r |
| 60 | \r |
| 61 | ; CPWAIT r0\r |
| 62 | ; mrc p15, 0, r0, c2, c0, 0\r |
| 63 | ; mov r0, r0\r |
| 64 | ; sub pc, pc, #4 \r |
| 65 | \r |
| 66 | \r |
| 67 | ; /*; make sure the pipeline is emptied*/\r |
| 68 | mov r0,#0\r |
| 69 | mov r0,r0\r |
| 70 | mov r0,r0\r |
| 71 | mov r0,r0\r |
| 72 | \r |
| 73 | ; /* zero PID in Process ID Virtual Address Map register. */\r |
| 74 | ; mov r0, #0\r |
| 75 | mcr p15, 0, r0, c13, c0, 0\r |
| 76 | \r |
| 77 | \r |
| 78 | ; CPWAIT r0\r |
| 79 | mrc p15, 0, r0, c2, c0, 0\r |
| 80 | mov r0, r0\r |
| 81 | sub pc, pc, #4 \r |
| 82 | \r |
| 83 | ; ldr r5, =0xA00512F5\r |
| 84 | ; ldr r8, =0xefef0000\r |
| 85 | ; str r8, [r5] \r |
| 86 | \r |
| 87 | \r |
| 88 | mov r0, #0\r |
| 89 | mov r1, r10\r |
| 90 | ldr r2, [r2, #0]\r |
| 91 | mov r2, #0\r |
| 92 | mov pc, r11 \r |
| 93 | \r |
| 94 | \r |
| 95 | |$M221|\r |
| 96 | \r |
| 97 | ENDP ; |?do_it@@YAXXZ|, do_it\r |
| 98 | \r |
| 99 | END\r |
projects / linexec-j720 / blame