[ms2-kexec] / cache-v7.S

/*
 *  linux/arch/arm/mm/cache-v7.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *  Copyright (C) 2005 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/unwind.h>

#include "proc-macros.S"

/*
 *	v7_flush_dcache_all()
 *
 *	Flush the whole D-cache.
 *
 *	Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
 *
 *	- mm    - mm_struct describing address space
 */
ENTRY(v7_flush_dcache_all)
	dmb					@ ensure ordering with previous memory accesses
	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
	ands	r3, r0, #0x7000000		@ extract loc from clidr
	mov	r3, r3, lsr #23			@ left align loc bit field
	beq	finished			@ if loc is 0, then no need to clean
	mov	r10, #0				@ start clean at cache level 0
loop1:
	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
	and	r1, r1, #7			@ mask of the bits for current cache only
	cmp	r1, #2				@ see what cache we have at this level
	blt	skip				@ skip if no cache, or just i-cache
	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
	isb					@ isb to sych the new cssr&csidr
	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
	and	r2, r1, #7			@ extract the length of the cache lines
	add	r2, r2, #4			@ add 4 (line length offset)
	ldr	r4, =0x3ff
	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
	clz	r5, r4				@ find bit position of way size increment
	ldr	r7, =0x7fff
	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
loop2:
	mov	r9, r4				@ create working copy of max way size
loop3:
 ARM(	orr	r11, r10, r9, lsl r5	)	@ factor way and cache number into r11
 THUMB(	lsl	r6, r9, r5		)
 THUMB(	orr	r11, r10, r6		)	@ factor way and cache number into r11
 ARM(	orr	r11, r11, r7, lsl r2	)	@ factor index number into r11
 THUMB(	lsl	r6, r7, r2		)
 THUMB(	orr	r11, r11, r6		)	@ factor index number into r11
	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
	subs	r9, r9, #1			@ decrement the way
	bge	loop3
	subs	r7, r7, #1			@ decrement the index
	bge	loop2
skip:
	add	r10, r10, #2			@ increment cache number
	cmp	r3, r10
	bgt	loop1
finished:
	mov	r10, #0				@ swith back to cache level 0
	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
	dsb
	isb
	mov	pc, lr
ENDPROC(v7_flush_dcache_all)

/*
 *	v7_flush_cache_all()
 *
 *	Flush the entire cache system.
 *  The data cache flush is now achieved using atomic clean / invalidates
 *  working outwards from L1 cache. This is done using Set/Way based cache
 *  maintainance instructions.
 *  The instruction cache can still be invalidated back to the point of
 *  unification in a single instruction.
 *
 */
ENTRY(v7_flush_kern_cache_all)
 ARM(	stmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
 THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
	bl	v7_flush_dcache_all
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
 ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
 THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
	mov	pc, lr
ENDPROC(v7_flush_kern_cache_all)

/*
 *	v7_flush_cache_all()
 *
 *	Flush all TLB entries in a particular address space
 *
 *	- mm    - mm_struct describing address space
 */
ENTRY(v7_flush_user_cache_all)
	/*FALLTHROUGH*/

/*
 *	v7_flush_cache_range(start, end, flags)
 *
 *	Flush a range of TLB entries in the specified address space.
 *
 *	- start - start address (may not be aligned)
 *	- end   - end address (exclusive, may not be aligned)
 *	- flags	- vm_area_struct flags describing address space
 *
 *	It is assumed that:
 *	- we have a VIPT cache.
 */
ENTRY(v7_flush_user_cache_range)
	mov	pc, lr
ENDPROC(v7_flush_user_cache_all)
ENDPROC(v7_flush_user_cache_range)

/*
 *	v7_coherent_kern_range(start,end)
 *
 *	Ensure that the I and D caches are coherent within specified
 *	region.  This is typically used when code has been written to
 *	a memory region, and will be executed.
 *
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 *
 *	It is assumed that:
 *	- the Icache does not read data from the write buffer
 */
ENTRY(v7_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	v7_coherent_user_range(start,end)
 *
 *	Ensure that the I and D caches are coherent within specified
 *	region.  This is typically used when code has been written to
 *	a memory region, and will be executed.
 *
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 *
 *	It is assumed that:
 *	- the Icache does not read data from the write buffer
 */
ENTRY(v7_coherent_user_range)
 UNWIND(.fnstart		)
	dcache_line_size r2, r3
	sub	r3, r2, #1
	bic	r0, r0, r3
1:
 USER(	mcr	p15, 0, r0, c7, c11, 1	)	@ clean D line to the point of unification
	dsb
 USER(	mcr	p15, 0, r0, c7, c5, 1	)	@ invalidate I line
	add	r0, r0, r2
2:
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
	dsb
	isb
	mov	pc, lr

/*
 * Fault handling for the cache operation above. If the virtual address in r0
 * isn't mapped, just try the next page.
 */
9001:
	mov	r0, r0, lsr #12
	mov	r0, r0, lsl #12
	add	r0, r0, #4096
	b	2b
 UNWIND(.fnend		)
ENDPROC(v7_coherent_kern_range)
ENDPROC(v7_coherent_user_range)

/*
 *	v7_flush_kern_dcache_page(kaddr)
 *
 *	Ensure that the data held in the page kaddr is written back
 *	to the page in question.
 *
 *	- kaddr   - kernel address (guaranteed to be page aligned)
 */
ENTRY(v7_flush_kern_dcache_page)
	dcache_line_size r2, r3
	add	r1, r0, #PAGE_SZ
1:
	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line / unified line
	add	r0, r0, r2
	cmp	r0, r1
	blo	1b
	dsb
	mov	pc, lr
ENDPROC(v7_flush_kern_dcache_page)

/*
 *	v7_dma_inv_range(start,end)
 *
 *	Invalidate the data cache within the specified region; we will
 *	be performing a DMA operation in this region and we want to
 *	purge old data in the cache.
 *
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 */
ENTRY(v7_dma_inv_range)
	dcache_line_size r2, r3
	sub	r3, r2, #1
	tst	r0, r3
	bic	r0, r0, r3
	mcrne	p15, 0, r0, c7, c14, 1		@ clean & invalidate D / U line

	tst	r1, r3
	bic	r1, r1, r3
	mcrne	p15, 0, r1, c7, c14, 1		@ clean & invalidate D / U line
1:
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D / U line
	add	r0, r0, r2
	cmp	r0, r1
	blo	1b
	dsb
	mov	pc, lr
ENDPROC(v7_dma_inv_range)

/*
 *	v7_dma_clean_range(start,end)
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 */
ENTRY(v7_dma_clean_range)
	dcache_line_size r2, r3
	sub	r3, r2, #1
	bic	r0, r0, r3
1:
	mcr	p15, 0, r0, c7, c10, 1		@ clean D / U line
	add	r0, r0, r2
	cmp	r0, r1
	blo	1b
	dsb
	mov	pc, lr
ENDPROC(v7_dma_clean_range)

/*
 *	v7_dma_flush_range(start,end)
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 */
ENTRY(v7_dma_flush_range)
	dcache_line_size r2, r3
	sub	r3, r2, #1
	bic	r0, r0, r3
1:
	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D / U line
	add	r0, r0, r2
	cmp	r0, r1
	blo	1b
	dsb
	mov	pc, lr
ENDPROC(v7_dma_flush_range)

	__INITDATA

	.type	v7_cache_fns, #object
ENTRY(v7_cache_fns)
	.long	v7_flush_kern_cache_all
	.long	v7_flush_user_cache_all
	.long	v7_flush_user_cache_range
	.long	v7_coherent_kern_range
	.long	v7_coherent_user_range
	.long	v7_flush_kern_dcache_page
	.long	v7_dma_inv_range
	.long	v7_dma_clean_range
	.long	v7_dma_flush_range
	.size	v7_cache_fns, . - v7_cache_fns
Commit	Line	Data
4e93cb00 MG	1	/*
	2	* linux/arch/arm/mm/cache-v7.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	* Copyright (C) 2005 ARM Ltd.
4e93cb00 MG	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This is the "shell" of the ARMv7 processor support.
	12	*/
	13	#include <linux/linkage.h>
	14	#include <linux/init.h>
	15	#include <asm/assembler.h>
5db3fe53	16	#include <asm/unwind.h>
4e93cb00 MG	17
	18	#include "proc-macros.S"
	19
	20	/*
	21	* v7_flush_dcache_all()
	22	*
	23	* Flush the whole D-cache.
	24	*
5db3fe53	25	* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
4e93cb00 MG	26	*
	27	* - mm - mm_struct describing address space
	28	*/
	29	ENTRY(v7_flush_dcache_all)
	30	dmb @ ensure ordering with previous memory accesses
	31	mrc p15, 1, r0, c0, c0, 1 @ read clidr
	32	ands r3, r0, #0x7000000 @ extract loc from clidr
	33	mov r3, r3, lsr #23 @ left align loc bit field
	34	beq finished @ if loc is 0, then no need to clean
	35	mov r10, #0 @ start clean at cache level 0
	36	loop1:
	37	add r2, r10, r10, lsr #1 @ work out 3x current cache level
	38	mov r1, r0, lsr r2 @ extract cache type bits from clidr
	39	and r1, r1, #7 @ mask of the bits for current cache only
	40	cmp r1, #2 @ see what cache we have at this level
	41	blt skip @ skip if no cache, or just i-cache
	42	mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
	43	isb @ isb to sych the new cssr&csidr
	44	mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
	45	and r2, r1, #7 @ extract the length of the cache lines
	46	add r2, r2, #4 @ add 4 (line length offset)
	47	ldr r4, =0x3ff
	48	ands r4, r4, r1, lsr #3 @ find maximum number on the way size
	49	clz r5, r4 @ find bit position of way size increment
	50	ldr r7, =0x7fff
	51	ands r7, r7, r1, lsr #13 @ extract max number of the index size
	52	loop2:
	53	mov r9, r4 @ create working copy of max way size
	54	loop3:
5db3fe53 MG	55	ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
	56	THUMB( lsl r6, r9, r5 )
	57	THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
	58	ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
	59	THUMB( lsl r6, r7, r2 )
	60	THUMB( orr r11, r11, r6 ) @ factor index number into r11
4e93cb00 MG	61	mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
	62	subs r9, r9, #1 @ decrement the way
	63	bge loop3
	64	subs r7, r7, #1 @ decrement the index
	65	bge loop2
	66	skip:
	67	add r10, r10, #2 @ increment cache number
	68	cmp r3, r10
	69	bgt loop1
	70	finished:
	71	mov r10, #0 @ swith back to cache level 0
	72	mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
	73	dsb
	74	isb
	75	mov pc, lr
	76	ENDPROC(v7_flush_dcache_all)
	77
	78	/*
	79	* v7_flush_cache_all()
	80	*
	81	* Flush the entire cache system.
	82	* The data cache flush is now achieved using atomic clean / invalidates
	83	* working outwards from L1 cache. This is done using Set/Way based cache
	84	* maintainance instructions.
	85	* The instruction cache can still be invalidated back to the point of
	86	* unification in a single instruction.
	87	*
	88	*/
	89	ENTRY(v7_flush_kern_cache_all)
5db3fe53 MG	90	ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
5db3fe53 MG	91	THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
4e93cb00 MG	92	bl v7_flush_dcache_all
	93	mov r0, #0
	94	mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
5db3fe53 MG	95	ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
5db3fe53 MG	96	THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
4e93cb00 MG	97	mov pc, lr
	98	ENDPROC(v7_flush_kern_cache_all)
	99
	100	/*
	101	* v7_flush_cache_all()
	102	*
	103	* Flush all TLB entries in a particular address space
	104	*
	105	* - mm - mm_struct describing address space
	106	*/
	107	ENTRY(v7_flush_user_cache_all)
	108	/FALLTHROUGH/
	109
	110	/*
	111	* v7_flush_cache_range(start, end, flags)
	112	*
	113	* Flush a range of TLB entries in the specified address space.
	114	*
	115	* - start - start address (may not be aligned)
	116	* - end - end address (exclusive, may not be aligned)
	117	* - flags - vm_area_struct flags describing address space
	118	*
	119	* It is assumed that:
	120	* - we have a VIPT cache.
	121	*/
	122	ENTRY(v7_flush_user_cache_range)
	123	mov pc, lr
	124	ENDPROC(v7_flush_user_cache_all)
	125	ENDPROC(v7_flush_user_cache_range)
	126
	127	/*
	128	* v7_coherent_kern_range(start,end)
	129	*
	130	* Ensure that the I and D caches are coherent within specified
	131	* region. This is typically used when code has been written to
	132	* a memory region, and will be executed.
	133	*
	134	* - start - virtual start address of region
	135	* - end - virtual end address of region
	136	*
	137	* It is assumed that:
	138	* - the Icache does not read data from the write buffer
	139	*/
	140	ENTRY(v7_coherent_kern_range)
	141	/* FALLTHROUGH */
	142
	143	/*
	144	* v7_coherent_user_range(start,end)
	145	*
	146	* Ensure that the I and D caches are coherent within specified
	147	* region. This is typically used when code has been written to
	148	* a memory region, and will be executed.
	149	*
	150	* - start - virtual start address of region
	151	* - end - virtual end address of region
	152	*
	153	* It is assumed that:
	154	* - the Icache does not read data from the write buffer
	155	*/
	156	ENTRY(v7_coherent_user_range)
5db3fe53	157	UNWIND(.fnstart )
4e93cb00 MG	158	dcache_line_size r2, r3
	159	sub r3, r2, #1
	160	bic r0, r0, r3
5db3fe53 MG	161	1:
5db3fe53 MG	162	USER( mcr p15, 0, r0, c7, c11, 1 ) @ clean D line to the point of unification
4e93cb00	163	dsb
5db3fe53	164	USER( mcr p15, 0, r0, c7, c5, 1 ) @ invalidate I line
4e93cb00	165	add r0, r0, r2
5db3fe53	166	2:
4e93cb00 MG	167	cmp r0, r1
	168	blo 1b
	169	mov r0, #0
	170	mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
	171	dsb
	172	isb
	173	mov pc, lr
5db3fe53 MG	174
	175	/*
	176	* Fault handling for the cache operation above. If the virtual address in r0
	177	* isn't mapped, just try the next page.
	178	*/
	179	9001:
	180	mov r0, r0, lsr #12
	181	mov r0, r0, lsl #12
	182	add r0, r0, #4096
	183	b 2b
	184	UNWIND(.fnend )
4e93cb00 MG	185	ENDPROC(v7_coherent_kern_range)
	186	ENDPROC(v7_coherent_user_range)
	187
	188	/*
	189	* v7_flush_kern_dcache_page(kaddr)
	190	*
	191	* Ensure that the data held in the page kaddr is written back
	192	* to the page in question.
	193	*
	194	* - kaddr - kernel address (guaranteed to be page aligned)
	195	*/
	196	ENTRY(v7_flush_kern_dcache_page)
	197	dcache_line_size r2, r3
	198	add r1, r0, #PAGE_SZ
	199	1:
	200	mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
	201	add r0, r0, r2
	202	cmp r0, r1
	203	blo 1b
	204	dsb
	205	mov pc, lr
	206	ENDPROC(v7_flush_kern_dcache_page)
	207
	208	/*
	209	* v7_dma_inv_range(start,end)
	210	*
	211	* Invalidate the data cache within the specified region; we will
	212	* be performing a DMA operation in this region and we want to
	213	* purge old data in the cache.
	214	*
	215	* - start - virtual start address of region
	216	* - end - virtual end address of region
	217	*/
	218	ENTRY(v7_dma_inv_range)
	219	dcache_line_size r2, r3
	220	sub r3, r2, #1
	221	tst r0, r3
	222	bic r0, r0, r3
	223	mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
	224
	225	tst r1, r3
	226	bic r1, r1, r3
	227	mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line
	228	1:
	229	mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line
	230	add r0, r0, r2
	231	cmp r0, r1
	232	blo 1b
	233	dsb
	234	mov pc, lr
	235	ENDPROC(v7_dma_inv_range)
	236
	237	/*
	238	* v7_dma_clean_range(start,end)
	239	* - start - virtual start address of region
	240	* - end - virtual end address of region
	241	*/
	242	ENTRY(v7_dma_clean_range)
	243	dcache_line_size r2, r3
	244	sub r3, r2, #1
	245	bic r0, r0, r3
	246	1:
	247	mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
	248	add r0, r0, r2
249	cmp r0, r1
250	blo 1b
251	dsb
252	mov pc, lr
253	ENDPROC(v7_dma_clean_range)
254
255	/*
256	* v7_dma_flush_range(start,end)
257	* - start - virtual start address of region
258	* - end - virtual end address of region
259	*/
260	ENTRY(v7_dma_flush_range)
261	dcache_line_size r2, r3
262	sub r3, r2, #1
263	bic r0, r0, r3
264	1:
265	mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
266	add r0, r0, r2
267	cmp r0, r1
268	blo 1b
269	dsb
270	mov pc, lr
271	ENDPROC(v7_dma_flush_range)
272
273	__INITDATA
274
275	.type v7_cache_fns, #object
276	ENTRY(v7_cache_fns)
277	.long v7_flush_kern_cache_all
278	.long v7_flush_user_cache_all
279	.long v7_flush_user_cache_range
280	.long v7_coherent_kern_range
281	.long v7_coherent_user_range
282	.long v7_flush_kern_dcache_page
283	.long v7_dma_inv_range
284	.long v7_dma_clean_range
285	.long v7_dma_flush_range
286	.size v7_cache_fns, . - v7_cache_fns