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1 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H |
2 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H | |
3 | ||
4 | /* | |
5 | * OMAP3430 Power/Reset Management register bits | |
6 | * | |
7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | |
8 | * Copyright (C) 2007-2008 Nokia Corporation | |
9 | * | |
10 | * Written by Paul Walmsley | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
17 | #include "prm.h" | |
18 | ||
19 | /* Shared register bits */ | |
20 | ||
21 | /* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */ | |
22 | #define OMAP3430_ON_SHIFT 24 | |
23 | #define OMAP3430_ON_MASK (0xff << 24) | |
24 | #define OMAP3430_ONLP_SHIFT 16 | |
25 | #define OMAP3430_ONLP_MASK (0xff << 16) | |
26 | #define OMAP3430_RET_SHIFT 8 | |
27 | #define OMAP3430_RET_MASK (0xff << 8) | |
28 | #define OMAP3430_OFF_SHIFT 0 | |
29 | #define OMAP3430_OFF_MASK (0xff << 0) | |
30 | ||
31 | /* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */ | |
32 | #define OMAP3430_ERROROFFSET_SHIFT 24 | |
33 | #define OMAP3430_ERROROFFSET_MASK (0xff << 24) | |
34 | #define OMAP3430_ERRORGAIN_SHIFT 16 | |
35 | #define OMAP3430_ERRORGAIN_MASK (0xff << 16) | |
36 | #define OMAP3430_INITVOLTAGE_SHIFT 8 | |
37 | #define OMAP3430_INITVOLTAGE_MASK (0xff << 8) | |
38 | #define OMAP3430_TIMEOUTEN (1 << 3) | |
39 | #define OMAP3430_INITVDD (1 << 2) | |
40 | #define OMAP3430_FORCEUPDATE (1 << 1) | |
41 | #define OMAP3430_VPENABLE (1 << 0) | |
42 | ||
43 | /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */ | |
44 | #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 | |
45 | #define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8) | |
46 | #define OMAP3430_VSTEPMIN_SHIFT 0 | |
47 | #define OMAP3430_VSTEPMIN_MASK (0xff << 0) | |
48 | ||
49 | /* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */ | |
50 | #define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8 | |
51 | #define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8) | |
52 | #define OMAP3430_VSTEPMAX_SHIFT 0 | |
53 | #define OMAP3430_VSTEPMAX_MASK (0xff << 0) | |
54 | ||
55 | /* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */ | |
56 | #define OMAP3430_VDDMAX_SHIFT 24 | |
57 | #define OMAP3430_VDDMAX_MASK (0xff << 24) | |
58 | #define OMAP3430_VDDMIN_SHIFT 16 | |
59 | #define OMAP3430_VDDMIN_MASK (0xff << 16) | |
60 | #define OMAP3430_TIMEOUT_SHIFT 0 | |
61 | #define OMAP3430_TIMEOUT_MASK (0xffff << 0) | |
62 | ||
63 | /* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */ | |
64 | #define OMAP3430_VPVOLTAGE_SHIFT 0 | |
65 | #define OMAP3430_VPVOLTAGE_MASK (0xff << 0) | |
66 | ||
67 | /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */ | |
68 | #define OMAP3430_VPINIDLE (1 << 0) | |
69 | ||
70 | /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ | |
71 | #define OMAP3430_EN_PER_SHIFT 7 | |
72 | #define OMAP3430_EN_PER_MASK (1 << 7) | |
73 | ||
74 | /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ | |
75 | #define OMAP3430_MEMORYCHANGE (1 << 3) | |
76 | ||
77 | /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */ | |
78 | #define OMAP3430_LOGICSTATEST (1 << 2) | |
79 | ||
80 | /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ | |
81 | #define OMAP3430_LASTLOGICSTATEENTERED (1 << 2) | |
82 | ||
83 | /* | |
84 | * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, | |
85 | * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM, | |
86 | * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits | |
87 | */ | |
88 | #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0 | |
89 | #define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) | |
90 | ||
91 | /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */ | |
92 | #define OMAP3630_ABB_LDO_TRANXDONE_MASK (1 << 26) | |
93 | #define OMAP3630_ABB_LDO_TRANXDONE_ST (1 << 26) | |
94 | #define OMAP3430_WKUP_ST (1 << 0) | |
95 | ||
96 | /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */ | |
97 | #define OMAP3430_WKUP_EN (1 << 0) | |
98 | ||
99 | /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */ | |
100 | #define OMAP3430_GRPSEL_MMC2 (1 << 25) | |
101 | #define OMAP3430_GRPSEL_MMC1 (1 << 24) | |
102 | #define OMAP3430_GRPSEL_MCSPI4 (1 << 21) | |
103 | #define OMAP3430_GRPSEL_MCSPI3 (1 << 20) | |
104 | #define OMAP3430_GRPSEL_MCSPI2 (1 << 19) | |
105 | #define OMAP3430_GRPSEL_MCSPI1 (1 << 18) | |
106 | #define OMAP3430_GRPSEL_I2C3 (1 << 17) | |
107 | #define OMAP3430_GRPSEL_I2C2 (1 << 16) | |
108 | #define OMAP3430_GRPSEL_I2C1 (1 << 15) | |
109 | #define OMAP3430_GRPSEL_UART2 (1 << 14) | |
110 | #define OMAP3430_GRPSEL_UART1 (1 << 13) | |
111 | #define OMAP3430_GRPSEL_GPT11 (1 << 12) | |
112 | #define OMAP3430_GRPSEL_GPT10 (1 << 11) | |
113 | #define OMAP3430_GRPSEL_MCBSP5 (1 << 10) | |
114 | #define OMAP3430_GRPSEL_MCBSP1 (1 << 9) | |
115 | #define OMAP3430_GRPSEL_HSOTGUSB (1 << 4) | |
116 | #define OMAP3430_GRPSEL_D2D (1 << 3) | |
117 | ||
118 | /* | |
119 | * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, | |
120 | * PM_PWSTCTRL_PER shared bits | |
121 | */ | |
122 | #define OMAP3430_MEMONSTATE_SHIFT 16 | |
123 | #define OMAP3430_MEMONSTATE_MASK (0x3 << 16) | |
124 | #define OMAP3430_MEMRETSTATE (1 << 8) | |
125 | ||
126 | /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ | |
127 | #define OMAP3430_GRPSEL_GPIO6 (1 << 17) | |
128 | #define OMAP3430_GRPSEL_GPIO5 (1 << 16) | |
129 | #define OMAP3430_GRPSEL_GPIO4 (1 << 15) | |
130 | #define OMAP3430_GRPSEL_GPIO3 (1 << 14) | |
131 | #define OMAP3430_GRPSEL_GPIO2 (1 << 13) | |
132 | #define OMAP3430_GRPSEL_UART3 (1 << 11) | |
133 | #define OMAP3430_GRPSEL_GPT9 (1 << 10) | |
134 | #define OMAP3430_GRPSEL_GPT8 (1 << 9) | |
135 | #define OMAP3430_GRPSEL_GPT7 (1 << 8) | |
136 | #define OMAP3430_GRPSEL_GPT6 (1 << 7) | |
137 | #define OMAP3430_GRPSEL_GPT5 (1 << 6) | |
138 | #define OMAP3430_GRPSEL_GPT4 (1 << 5) | |
139 | #define OMAP3430_GRPSEL_GPT3 (1 << 4) | |
140 | #define OMAP3430_GRPSEL_GPT2 (1 << 3) | |
141 | #define OMAP3430_GRPSEL_MCBSP4 (1 << 2) | |
142 | #define OMAP3430_GRPSEL_MCBSP3 (1 << 1) | |
143 | #define OMAP3430_GRPSEL_MCBSP2 (1 << 0) | |
144 | ||
145 | /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */ | |
146 | #define OMAP3430_GRPSEL_IO (1 << 8) | |
147 | #define OMAP3430_GRPSEL_SR2 (1 << 7) | |
148 | #define OMAP3430_GRPSEL_SR1 (1 << 6) | |
149 | #define OMAP3430_GRPSEL_GPIO1 (1 << 3) | |
150 | #define OMAP3430_GRPSEL_GPT12 (1 << 1) | |
151 | #define OMAP3430_GRPSEL_GPT1 (1 << 0) | |
152 | ||
153 | /* Bits specific to each register */ | |
154 | ||
155 | /* RM_RSTCTRL_IVA2 */ | |
156 | #define OMAP3430_RST3_IVA2 (1 << 2) | |
157 | #define OMAP3430_RST2_IVA2 (1 << 1) | |
158 | #define OMAP3430_RST1_IVA2 (1 << 0) | |
159 | ||
160 | /* RM_RSTST_IVA2 specific bits */ | |
161 | #define OMAP3430_EMULATION_VSEQ_RST (1 << 13) | |
162 | #define OMAP3430_EMULATION_VHWA_RST (1 << 12) | |
163 | #define OMAP3430_EMULATION_IVA2_RST (1 << 11) | |
164 | #define OMAP3430_IVA2_SW_RST3 (1 << 10) | |
165 | #define OMAP3430_IVA2_SW_RST2 (1 << 9) | |
166 | #define OMAP3430_IVA2_SW_RST1 (1 << 8) | |
167 | ||
168 | /* PM_WKDEP_IVA2 specific bits */ | |
169 | ||
170 | /* PM_PWSTCTRL_IVA2 specific bits */ | |
171 | #define OMAP3430_L2FLATMEMONSTATE_SHIFT 22 | |
172 | #define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22) | |
173 | #define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20 | |
174 | #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20) | |
175 | #define OMAP3430_L1FLATMEMONSTATE_SHIFT 18 | |
176 | #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) | |
177 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16 | |
178 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) | |
179 | #define OMAP3430_L2FLATMEMRETSTATE (1 << 11) | |
180 | #define OMAP3430_SHAREDL2CACHEFLATRETSTATE (1 << 10) | |
181 | #define OMAP3430_L1FLATMEMRETSTATE (1 << 9) | |
182 | #define OMAP3430_SHAREDL1CACHEFLATRETSTATE (1 << 8) | |
183 | ||
184 | /* PM_PWSTST_IVA2 specific bits */ | |
185 | #define OMAP3430_L2FLATMEMSTATEST_SHIFT 10 | |
186 | #define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10) | |
187 | #define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8 | |
188 | #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8) | |
189 | #define OMAP3430_L1FLATMEMSTATEST_SHIFT 6 | |
190 | #define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6) | |
191 | #define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4 | |
192 | #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4) | |
193 | ||
194 | /* PM_PREPWSTST_IVA2 specific bits */ | |
195 | #define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10 | |
196 | #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10) | |
197 | #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8 | |
198 | #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8) | |
199 | #define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6 | |
200 | #define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6) | |
201 | #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4 | |
202 | #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4) | |
203 | ||
204 | /* PRM_IRQSTATUS_IVA2 specific bits */ | |
205 | #define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST (1 << 2) | |
206 | #define OMAP3430_FORCEWKUP_ST (1 << 1) | |
207 | ||
208 | /* PRM_IRQENABLE_IVA2 specific bits */ | |
209 | #define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN (1 << 2) | |
210 | #define OMAP3430_FORCEWKUP_EN (1 << 1) | |
211 | ||
212 | /* PRM_REVISION specific bits */ | |
213 | ||
214 | /* PRM_SYSCONFIG specific bits */ | |
215 | ||
216 | /* PRM_IRQSTATUS_MPU specific bits */ | |
217 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 | |
218 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST (1 << 25) | |
219 | #define OMAP3430_VC_TIMEOUTERR_ST (1 << 24) | |
220 | #define OMAP3430_VC_RAERR_ST (1 << 23) | |
221 | #define OMAP3430_VC_SAERR_ST (1 << 22) | |
222 | #define OMAP3430_VP2_TRANXDONE_ST (1 << 21) | |
223 | #define OMAP3430_VP2_EQVALUE_ST (1 << 20) | |
224 | #define OMAP3430_VP2_NOSMPSACK_ST (1 << 19) | |
225 | #define OMAP3430_VP2_MAXVDD_ST (1 << 18) | |
226 | #define OMAP3430_VP2_MINVDD_ST (1 << 17) | |
227 | #define OMAP3430_VP2_OPPCHANGEDONE_ST (1 << 16) | |
228 | #define OMAP3430_VP1_TRANXDONE_ST (1 << 15) | |
229 | #define OMAP3430_VP1_EQVALUE_ST (1 << 14) | |
230 | #define OMAP3430_VP1_NOSMPSACK_ST (1 << 13) | |
231 | #define OMAP3430_VP1_MAXVDD_ST (1 << 12) | |
232 | #define OMAP3430_VP1_MINVDD_ST (1 << 11) | |
233 | #define OMAP3430_VP1_OPPCHANGEDONE_ST (1 << 10) | |
234 | #define OMAP3430_IO_ST (1 << 9) | |
235 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST (1 << 8) | |
236 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 | |
237 | #define OMAP3430_MPU_DPLL_ST (1 << 7) | |
238 | #define OMAP3430_MPU_DPLL_ST_SHIFT 7 | |
239 | #define OMAP3430_PERIPH_DPLL_ST (1 << 6) | |
240 | #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 | |
241 | #define OMAP3430_CORE_DPLL_ST (1 << 5) | |
242 | #define OMAP3430_CORE_DPLL_ST_SHIFT 5 | |
243 | #define OMAP3430_TRANSITION_ST (1 << 4) | |
244 | #define OMAP3430_EVGENOFF_ST (1 << 3) | |
245 | #define OMAP3430_EVGENON_ST (1 << 2) | |
246 | #define OMAP3430_FS_USB_WKUP_ST (1 << 1) | |
247 | ||
248 | /* PRM_IRQENABLE_MPU specific bits */ | |
249 | #define OMAP3630_VC_BYPASS_ACK_EN (1 << 28) | |
250 | #define OMAP3630_VC_VP1_ACK_EN (1 << 27) | |
251 | #define OMAP3630_ABB_LDO_TRANXDONE_EN (1 << 26) | |
252 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 | |
253 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN (1 << 25) | |
254 | #define OMAP3430_VC_TIMEOUTERR_EN (1 << 24) | |
255 | #define OMAP3430_VC_RAERR_EN (1 << 23) | |
256 | #define OMAP3430_VC_SAERR_EN (1 << 22) | |
257 | #define OMAP3430_VP2_TRANXDONE_EN (1 << 21) | |
258 | #define OMAP3430_VP2_EQVALUE_EN (1 << 20) | |
259 | #define OMAP3430_VP2_NOSMPSACK_EN (1 << 19) | |
260 | #define OMAP3430_VP2_MAXVDD_EN (1 << 18) | |
261 | #define OMAP3430_VP2_MINVDD_EN (1 << 17) | |
262 | #define OMAP3430_VP2_OPPCHANGEDONE_EN (1 << 16) | |
263 | #define OMAP3430_VP1_TRANXDONE_EN (1 << 15) | |
264 | #define OMAP3430_VP1_EQVALUE_EN (1 << 14) | |
265 | #define OMAP3430_VP1_NOSMPSACK_EN (1 << 13) | |
266 | #define OMAP3430_VP1_MAXVDD_EN (1 << 12) | |
267 | #define OMAP3430_VP1_MINVDD_EN (1 << 11) | |
268 | #define OMAP3430_VP1_OPPCHANGEDONE_EN (1 << 10) | |
269 | #define OMAP3430_IO_EN (1 << 9) | |
270 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN (1 << 8) | |
271 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 | |
272 | #define OMAP3430_MPU_DPLL_RECAL_EN (1 << 7) | |
273 | #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 | |
274 | #define OMAP3430_PERIPH_DPLL_RECAL_EN (1 << 6) | |
275 | #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 | |
276 | #define OMAP3430_CORE_DPLL_RECAL_EN (1 << 5) | |
277 | #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 | |
278 | #define OMAP3430_TRANSITION_EN (1 << 4) | |
279 | #define OMAP3430_EVGENOFF_EN (1 << 3) | |
280 | #define OMAP3430_EVGENON_EN (1 << 2) | |
281 | #define OMAP3430_FS_USB_WKUP_EN (1 << 1) | |
282 | ||
283 | /* RM_RSTST_MPU specific bits */ | |
284 | #define OMAP3430_EMULATION_MPU_RST (1 << 11) | |
285 | ||
286 | /* PM_WKDEP_MPU specific bits */ | |
287 | #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5 | |
288 | #define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5) | |
289 | #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2 | |
290 | #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2) | |
291 | ||
292 | /* PM_EVGENCTRL_MPU */ | |
293 | #define OMAP3430_OFFLOADMODE_SHIFT 3 | |
294 | #define OMAP3430_OFFLOADMODE_MASK (0x3 << 3) | |
295 | #define OMAP3430_ONLOADMODE_SHIFT 1 | |
296 | #define OMAP3430_ONLOADMODE_MASK (0x3 << 1) | |
297 | #define OMAP3430_ENABLE (1 << 0) | |
298 | ||
299 | /* PM_EVGENONTIM_MPU */ | |
300 | #define OMAP3430_ONTIMEVAL_SHIFT 0 | |
301 | #define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0) | |
302 | ||
303 | /* PM_EVGENOFFTIM_MPU */ | |
304 | #define OMAP3430_OFFTIMEVAL_SHIFT 0 | |
305 | #define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0) | |
306 | ||
307 | /* PM_PWSTCTRL_MPU specific bits */ | |
308 | #define OMAP3430_L2CACHEONSTATE_SHIFT 16 | |
309 | #define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16) | |
310 | #define OMAP3430_L2CACHERETSTATE (1 << 8) | |
311 | #define OMAP3430_LOGICL1CACHERETSTATE (1 << 2) | |
312 | ||
313 | /* PM_PWSTST_MPU specific bits */ | |
314 | #define OMAP3430_L2CACHESTATEST_SHIFT 6 | |
315 | #define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6) | |
316 | #define OMAP3430_LOGICL1CACHESTATEST (1 << 2) | |
317 | ||
318 | /* PM_PREPWSTST_MPU specific bits */ | |
319 | #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6 | |
320 | #define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6) | |
321 | #define OMAP3430_LASTLOGICL1CACHESTATEENTERED (1 << 2) | |
322 | ||
323 | /* RM_RSTCTRL_CORE */ | |
324 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON (1 << 1) | |
325 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST (1 << 0) | |
326 | ||
327 | /* RM_RSTST_CORE specific bits */ | |
328 | #define OMAP3430_MODEM_SECURITY_VIOL_RST (1 << 10) | |
329 | #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON (1 << 9) | |
330 | #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST (1 << 8) | |
331 | ||
332 | /* PM_WKEN1_CORE specific bits */ | |
333 | ||
334 | /* PM_MPUGRPSEL1_CORE specific bits */ | |
335 | #define OMAP3430_GRPSEL_FSHOSTUSB (1 << 5) | |
336 | ||
337 | /* PM_IVA2GRPSEL1_CORE specific bits */ | |
338 | ||
339 | /* PM_WKST1_CORE specific bits */ | |
340 | ||
341 | /* PM_PWSTCTRL_CORE specific bits */ | |
342 | #define OMAP3430_MEM2ONSTATE_SHIFT 18 | |
343 | #define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18) | |
344 | #define OMAP3430_MEM1ONSTATE_SHIFT 16 | |
345 | #define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16) | |
346 | #define OMAP3430_MEM2RETSTATE (1 << 9) | |
347 | #define OMAP3430_MEM1RETSTATE (1 << 8) | |
348 | ||
349 | /* PM_PWSTST_CORE specific bits */ | |
350 | #define OMAP3430_MEM2STATEST_SHIFT 6 | |
351 | #define OMAP3430_MEM2STATEST_MASK (0x3 << 6) | |
352 | #define OMAP3430_MEM1STATEST_SHIFT 4 | |
353 | #define OMAP3430_MEM1STATEST_MASK (0x3 << 4) | |
354 | ||
355 | /* PM_PREPWSTST_CORE specific bits */ | |
356 | #define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6 | |
357 | #define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6) | |
358 | #define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4 | |
359 | #define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4) | |
360 | ||
361 | /* RM_RSTST_GFX specific bits */ | |
362 | ||
363 | /* PM_WKDEP_GFX specific bits */ | |
364 | #define OMAP3430_PM_WKDEP_GFX_EN_IVA2 (1 << 2) | |
365 | ||
366 | /* PM_PWSTCTRL_GFX specific bits */ | |
367 | ||
368 | /* PM_PWSTST_GFX specific bits */ | |
369 | ||
370 | /* PM_PREPWSTST_GFX specific bits */ | |
371 | ||
372 | /* PM_WKEN_WKUP specific bits */ | |
373 | #define OMAP3430_EN_IO_CHAIN (1 << 16) | |
374 | #define OMAP3430_EN_IO (1 << 8) | |
375 | #define OMAP3430_EN_GPIO1 (1 << 3) | |
376 | ||
377 | /* PM_MPUGRPSEL_WKUP specific bits */ | |
378 | ||
379 | /* PM_IVA2GRPSEL_WKUP specific bits */ | |
380 | ||
381 | /* PM_WKST_WKUP specific bits */ | |
382 | #define OMAP3430_ST_IO_CHAIN (1 << 16) | |
383 | #define OMAP3430_ST_IO (1 << 8) | |
384 | ||
385 | /* PRM_CLKSEL */ | |
386 | #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 | |
387 | #define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) | |
388 | ||
389 | /* PRM_CLKOUT_CTRL */ | |
390 | #define OMAP3430_CLKOUT_EN (1 << 7) | |
391 | #define OMAP3430_CLKOUT_EN_SHIFT 7 | |
392 | ||
393 | /* RM_RSTST_DSS specific bits */ | |
394 | ||
395 | /* PM_WKEN_DSS */ | |
396 | #define OMAP3430_PM_WKEN_DSS_EN_DSS (1 << 0) | |
397 | ||
398 | /* PM_WKDEP_DSS specific bits */ | |
399 | #define OMAP3430_PM_WKDEP_DSS_EN_IVA2 (1 << 2) | |
400 | ||
401 | /* PM_PWSTCTRL_DSS specific bits */ | |
402 | ||
403 | /* PM_PWSTST_DSS specific bits */ | |
404 | ||
405 | /* PM_PREPWSTST_DSS specific bits */ | |
406 | ||
407 | /* RM_RSTST_CAM specific bits */ | |
408 | ||
409 | /* PM_WKDEP_CAM specific bits */ | |
410 | #define OMAP3430_PM_WKDEP_CAM_EN_IVA2 (1 << 2) | |
411 | ||
412 | /* PM_PWSTCTRL_CAM specific bits */ | |
413 | ||
414 | /* PM_PWSTST_CAM specific bits */ | |
415 | ||
416 | /* PM_PREPWSTST_CAM specific bits */ | |
417 | ||
418 | /* PM_PWSTCTRL_USBHOST specific bits */ | |
419 | #define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4 | |
420 | ||
421 | /* RM_RSTST_PER specific bits */ | |
422 | ||
423 | /* PM_WKEN_PER specific bits */ | |
424 | ||
425 | /* PM_MPUGRPSEL_PER specific bits */ | |
426 | ||
427 | /* PM_IVA2GRPSEL_PER specific bits */ | |
428 | ||
429 | /* PM_WKST_PER specific bits */ | |
430 | ||
431 | /* PM_WKDEP_PER specific bits */ | |
432 | #define OMAP3430_PM_WKDEP_PER_EN_IVA2 (1 << 2) | |
433 | ||
434 | /* PM_PWSTCTRL_PER specific bits */ | |
435 | ||
436 | /* PM_PWSTST_PER specific bits */ | |
437 | ||
438 | /* PM_PREPWSTST_PER specific bits */ | |
439 | ||
440 | /* RM_RSTST_EMU specific bits */ | |
441 | ||
442 | /* PM_PWSTST_EMU specific bits */ | |
443 | ||
444 | /* PRM_VC_SMPS_SA */ | |
445 | #define OMAP3430_SMPS_SA1_SHIFT 16 | |
446 | #define OMAP3430_SMPS_SA1_MASK (0x7f << 16) | |
447 | #define OMAP3430_SMPS_SA0_SHIFT 0 | |
448 | #define OMAP3430_SMPS_SA0_MASK (0x7f << 0) | |
449 | ||
450 | /* PRM_VC_SMPS_VOL_RA */ | |
451 | #define OMAP3430_VOLRA1_SHIFT 16 | |
452 | #define OMAP3430_VOLRA1_MASK (0xff << 16) | |
453 | #define OMAP3430_VOLRA0_SHIFT 0 | |
454 | #define OMAP3430_VOLRA0_MASK (0xff << 0) | |
455 | ||
456 | /* PRM_VC_SMPS_CMD_RA */ | |
457 | #define OMAP3430_CMDRA1_SHIFT 16 | |
458 | #define OMAP3430_CMDRA1_MASK (0xff << 16) | |
459 | #define OMAP3430_CMDRA0_SHIFT 0 | |
460 | #define OMAP3430_CMDRA0_MASK (0xff << 0) | |
461 | ||
462 | /* PRM_VC_CMD_VAL specific bits */ | |
463 | #define OMAP3430_VC_CMD_ON_SHIFT 24 | |
464 | #define OMAP3430_VC_CMD_ON_MASK (0xff << 24) | |
465 | #define OMAP3430_VC_CMD_ONLP_SHIFT 16 | |
466 | #define OMAP3430_VC_CMD_ONLP_MASK (0xff << 16) | |
467 | #define OMAP3430_VC_CMD_RET_SHIFT 8 | |
468 | #define OMAP3430_VC_CMD_RET_MASK (0xff << 8) | |
469 | #define OMAP3430_VC_CMD_OFF_SHIFT 0 | |
470 | #define OMAP3430_VC_CMD_OFF_MASK (0xff << 0) | |
471 | ||
472 | /* PRM_VC_CH_CONF */ | |
473 | #define OMAP3430_CMD1 (1 << 20) | |
474 | #define OMAP3430_RACEN1 (1 << 19) | |
475 | #define OMAP3430_RAC1 (1 << 18) | |
476 | #define OMAP3430_RAV1 (1 << 17) | |
477 | #define OMAP3430_PRM_VC_CH_CONF_SA1 (1 << 16) | |
478 | #define OMAP3430_CMD0 (1 << 4) | |
479 | #define OMAP3430_RACEN0 (1 << 3) | |
480 | #define OMAP3430_RAC0 (1 << 2) | |
481 | #define OMAP3430_RAV0 (1 << 1) | |
482 | #define OMAP3430_PRM_VC_CH_CONF_SA0 (1 << 0) | |
483 | ||
484 | /* PRM_VC_I2C_CFG */ | |
485 | #define OMAP3430_HSMASTER (1 << 5) | |
486 | #define OMAP3430_SREN (1 << 4) | |
487 | #define OMAP3430_HSEN (1 << 3) | |
488 | #define OMAP3430_MCODE_SHIFT 0 | |
489 | #define OMAP3430_MCODE_MASK (0x7 << 0) | |
490 | ||
491 | /* PRM_VC_BYPASS_VAL */ | |
492 | #define OMAP3430_VALID (1 << 24) | |
493 | #define OMAP3430_DATA_SHIFT 16 | |
494 | #define OMAP3430_DATA_MASK (0xff << 16) | |
495 | #define OMAP3430_REGADDR_SHIFT 8 | |
496 | #define OMAP3430_REGADDR_MASK (0xff << 8) | |
497 | #define OMAP3430_SLAVEADDR_SHIFT 0 | |
498 | #define OMAP3430_SLAVEADDR_MASK (0x7f << 0) | |
499 | ||
500 | /* PRM_RSTCTRL */ | |
501 | #define OMAP3430_RST_DPLL3 (1 << 2) | |
502 | #define OMAP3430_RST_GS (1 << 1) | |
503 | ||
504 | /* PRM_RSTTIME */ | |
505 | #define OMAP3430_RSTTIME2_SHIFT 8 | |
506 | #define OMAP3430_RSTTIME2_MASK (0x1f << 8) | |
507 | #define OMAP3430_RSTTIME1_SHIFT 0 | |
508 | #define OMAP3430_RSTTIME1_MASK (0xff << 0) | |
509 | ||
510 | /* PRM_RSTST */ | |
511 | #define OMAP3430_ICECRUSHER_RST (1 << 10) | |
512 | #define OMAP3430_ICEPICK_RST (1 << 9) | |
513 | #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST (1 << 8) | |
514 | #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST (1 << 7) | |
515 | #define OMAP3430_EXTERNAL_WARM_RST (1 << 6) | |
516 | #define OMAP3430_SECURE_WD_RST (1 << 5) | |
517 | #define OMAP3430_MPU_WD_RST (1 << 4) | |
518 | #define OMAP3430_SECURITY_VIOL_RST (1 << 3) | |
519 | #define OMAP3430_GLOBAL_SW_RST (1 << 1) | |
520 | #define OMAP3430_GLOBAL_COLD_RST (1 << 0) | |
521 | ||
522 | /* PRM_VOLTCTRL */ | |
523 | #define OMAP3430_SEL_VMODE (1 << 4) | |
524 | #define OMAP3430_SEL_OFF (1 << 3) | |
525 | #define OMAP3430_AUTO_OFF (1 << 2) | |
526 | #define OMAP3430_AUTO_RET (1 << 1) | |
527 | #define OMAP3430_AUTO_SLEEP (1 << 0) | |
528 | ||
529 | /* PRM_SRAM_PCHARGE */ | |
530 | #define OMAP3430_PCHARGE_TIME_SHIFT 0 | |
531 | #define OMAP3430_PCHARGE_TIME_MASK (0xff << 0) | |
532 | ||
533 | /* PRM_CLKSRC_CTRL */ | |
534 | #define OMAP3430_SYSCLKDIV_SHIFT 6 | |
535 | #define OMAP3430_SYSCLKDIV_MASK (0x3 << 6) | |
536 | #define OMAP3430_AUTOEXTCLKMODE_SHIFT 3 | |
537 | #define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3) | |
538 | #define OMAP3430_SYSCLKSEL_SHIFT 0 | |
539 | #define OMAP3430_SYSCLKSEL_MASK (0x3 << 0) | |
540 | ||
541 | /* PRM_VOLTSETUP1 */ | |
542 | #define OMAP3430_SETUP_TIME2_SHIFT 16 | |
543 | #define OMAP3430_SETUP_TIME2_MASK (0xffff << 16) | |
544 | #define OMAP3430_SETUP_TIME1_SHIFT 0 | |
545 | #define OMAP3430_SETUP_TIME1_MASK (0xffff << 0) | |
546 | ||
547 | /* PRM_VOLTOFFSET */ | |
548 | #define OMAP3430_OFFSET_TIME_SHIFT 0 | |
549 | #define OMAP3430_OFFSET_TIME_MASK (0xffff << 0) | |
550 | ||
551 | /* PRM_CLKSETUP */ | |
552 | #define OMAP3430_SETUP_TIME_SHIFT 0 | |
553 | #define OMAP3430_SETUP_TIME_MASK (0xffff << 0) | |
554 | ||
555 | /* PRM_POLCTRL */ | |
556 | #define OMAP3430_OFFMODE_POL (1 << 3) | |
557 | #define OMAP3430_CLKOUT_POL (1 << 2) | |
558 | #define OMAP3430_CLKREQ_POL (1 << 1) | |
559 | #define OMAP3430_EXTVOL_POL (1 << 0) | |
560 | ||
561 | /* PRM_VOLTSETUP2 */ | |
562 | #define OMAP3430_OFFMODESETUPTIME_SHIFT 0 | |
563 | #define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0) | |
564 | ||
565 | /* PRM_VP1_CONFIG specific bits */ | |
566 | ||
567 | /* PRM_VP1_VSTEPMIN specific bits */ | |
568 | ||
569 | /* PRM_VP1_VSTEPMAX specific bits */ | |
570 | ||
571 | /* PRM_VP1_VLIMITTO specific bits */ | |
572 | ||
573 | /* PRM_VP1_VOLTAGE specific bits */ | |
574 | ||
575 | /* PRM_VP1_STATUS specific bits */ | |
576 | ||
577 | /* PRM_VP2_CONFIG specific bits */ | |
578 | ||
579 | /* PRM_VP2_VSTEPMIN specific bits */ | |
580 | ||
581 | /* PRM_VP2_VSTEPMAX specific bits */ | |
582 | ||
583 | /* PRM_VP2_VLIMITTO specific bits */ | |
584 | ||
585 | /* PRM_VP2_VOLTAGE specific bits */ | |
586 | ||
587 | /* PRM_VP2_STATUS specific bits */ | |
588 | ||
589 | /* PRM_LDO_ABB_SETUP */ | |
590 | #define OMAP3630_SR2_IN_TRANSITION (1 << 6) | |
591 | #define OMAP3630_SR2_STATUS_SHIFT 3 | |
592 | #define OMAP3630_SR2_STATUS_MASK (0x3 << 3) | |
593 | #define OMAP3630_OPP_CHANGE (1 << 2) | |
594 | #define OMAP3630_OPP_SEL_SHIFT 0 | |
595 | #define OMAP3630_OPP_SEL_MASK (0x3 << 0) | |
596 | ||
597 | /* PRM_LDO_ABB_CTRL */ | |
598 | #define OMAP3630_SR2_WTCNT_VALUE_SHIFT 8 | |
599 | #define OMAP3630_SR2_WTCNT_VALUE_MASK (0xff << 8) | |
600 | #define OMAP3630_SLEEP_RBB_SEL (1 << 3) | |
601 | #define OMAP3630_ACTIVE_FBB_SEL (1 << 2) | |
602 | #define OMAP3630_ACTIVE_RBB_SEL (1 << 1) | |
603 | #define OMAP3630_SR2EN (1 << 0) | |
604 | ||
605 | /* RM_RSTST_NEON specific bits */ | |
606 | ||
607 | /* PM_WKDEP_NEON specific bits */ | |
608 | ||
609 | /* PM_PWSTCTRL_NEON specific bits */ | |
610 | ||
611 | /* PM_PWSTST_NEON specific bits */ | |
612 | ||
613 | /* PM_PREPWSTST_NEON specific bits */ | |
614 | ||
615 | #endif |