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(parent: 1a093c1) | patch
Updated logic in lo_read.v so it's much tidier now, better timing.
authord18c7db <d18c7db@ef4ab9da-24cd-11de-8aaa-f3a34680c41f>
Thu, 16 Apr 2009 23:09:21 +0000 (23:09 +0000)
committerd18c7db <d18c7db@ef4ab9da-24cd-11de-8aaa-f3a34680c41f>
Thu, 16 Apr 2009 23:09:21 +0000 (23:09 +0000)
commit1c38843b3f0b808f06a468162667bf96d235363d
treeae80f4452d5b18dca0235b8a5f317300725406f3tree | snapshot
parent1a093c19b52e541d3cfe21e0d31e3c199da441d7commit | diff
Updated logic in lo_read.v so it's much tidier now, better timing.
Commented source and recompiled FPGA to new fpgaimg.c
armsrc/fpgaimg.c diff | blob | blame | history
fpga/lo_read.v diff | blob | blame | history
fpga/testbed_lo_read.v diff | blob | blame | history
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