[proxmark3-svn] / armsrc / fpga.c

//-----------------------------------------------------------------------------\r
// Routines to load the FPGA image, and then to configure the FPGA's major\r
// mode once it is configured.\r
//\r
// Jonathan Westhues, April 2006\r
//-----------------------------------------------------------------------------\r
#include <proxmark3.h>\r
#include "apps.h"\r
\r
//-----------------------------------------------------------------------------\r
// Set up the Serial Peripheral Interface as master\r
// Used to write the FPGA config word\r
// May also be used to write to other SPI attached devices like an LCD\r
//-----------------------------------------------------------------------------\r
void SetupSpi(int mode)\r
{\r
	// PA10 -> SPI_NCS2 chip select (LCD)\r
	// PA11 -> SPI_NCS0 chip select (FPGA)\r
	// PA12 -> SPI_MISO Master-In Slave-Out\r
	// PA13 -> SPI_MOSI Master-Out Slave-In\r
	// PA14 -> SPI_SPCK Serial Clock\r
\r
	// Disable PIO control of the following pins, allows use by the SPI peripheral\r
	PIO_DISABLE			 =	(1 << GPIO_NCS0)	|\r
							(1 << GPIO_NCS2) 	|\r
							(1 << GPIO_MISO)	|\r
							(1 << GPIO_MOSI)	|\r
							(1 << GPIO_SPCK);\r
\r
	PIO_PERIPHERAL_A_SEL =	(1 << GPIO_NCS0)	|\r
							(1 << GPIO_MISO)	|\r
							(1 << GPIO_MOSI)	|\r
							(1 << GPIO_SPCK);\r
\r
	PIO_PERIPHERAL_B_SEL =	(1 << GPIO_NCS2);\r
\r
	//enable the SPI Peripheral clock\r
	PMC_PERIPHERAL_CLK_ENABLE = (1<<PERIPH_SPI);\r
	// Enable SPI\r
	SPI_CONTROL = SPI_CONTROL_ENABLE;\r
\r
	switch (mode) {\r
		case SPI_FPGA_MODE:\r
			SPI_MODE =\r
				( 0 << 24)	|	// Delay between chip selects (take default: 6 MCK periods)\r
				(14 << 16)	|	// Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)\r
				( 0 << 7)	|	// Local Loopback Disabled\r
				( 1 << 4)	|	// Mode Fault Detection disabled\r
				( 0 << 2)	|	// Chip selects connected directly to peripheral\r
				( 0 << 1) 	|	// Fixed Peripheral Select\r
				( 1 << 0);		// Master Mode\r
			SPI_FOR_CHIPSEL_0 =\r
				( 1 << 24)	|	// Delay between Consecutive Transfers (32 MCK periods)\r
				( 1 << 16)	|	// Delay Before SPCK (1 MCK period)\r
				( 6 << 8)	|	// Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
				( 8 << 4)	|	// Bits per Transfer (16 bits)\r
				( 0 << 3)	|	// Chip Select inactive after transfer\r
				( 1 << 1)	|	// Clock Phase data captured on leading edge, changes on following edge\r
				( 0 << 0);		// Clock Polarity inactive state is logic 0\r
			break;\r
		case SPI_LCD_MODE:\r
			SPI_MODE =\r
				( 0 << 24)	|	// Delay between chip selects (take default: 6 MCK periods)\r
				(11 << 16)	|	// Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)\r
				( 0 << 7)	|	// Local Loopback Disabled\r
				( 1 << 4)	|	// Mode Fault Detection disabled\r
				( 0 << 2)	|	// Chip selects connected directly to peripheral\r
				( 0 << 1) 	|	// Fixed Peripheral Select\r
				( 1 << 0);		// Master Mode\r
			SPI_FOR_CHIPSEL_2 =\r
				( 1 << 24)	|	// Delay between Consecutive Transfers (32 MCK periods)\r
				( 1 << 16)	|	// Delay Before SPCK (1 MCK period)\r
				( 6 << 8)	|	// Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
				( 1 << 4)	|	// Bits per Transfer (9 bits)\r
				( 0 << 3)	|	// Chip Select inactive after transfer\r
				( 1 << 1)	|	// Clock Phase data captured on leading edge, changes on following edge\r
				( 0 << 0);		// Clock Polarity inactive state is logic 0\r
			break;\r
		default:				// Disable SPI\r
			SPI_CONTROL = SPI_CONTROL_DISABLE;\r
			break;\r
	}\r
}\r
\r
//-----------------------------------------------------------------------------\r
// Set up the synchronous serial port, with the one set of options that we\r
// always use when we are talking to the FPGA. Both RX and TX are enabled.\r
//-----------------------------------------------------------------------------\r
void FpgaSetupSsc(void)\r
{\r
	// First configure the GPIOs, and get ourselves a clock.\r
	PIO_PERIPHERAL_A_SEL =	(1 << GPIO_SSC_FRAME)	|\r
							(1 << GPIO_SSC_DIN)		|\r
							(1 << GPIO_SSC_DOUT)	|\r
							(1 << GPIO_SSC_CLK);\r
	PIO_DISABLE = (1 << GPIO_SSC_DOUT);\r
\r
	PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_SSC);\r
\r
	// Now set up the SSC proper, starting from a known state.\r
	SSC_CONTROL = SSC_CONTROL_RESET;\r
\r
	// RX clock comes from TX clock, RX starts when TX starts, data changes\r
	// on RX clock rising edge, sampled on falling edge\r
	SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);\r
\r
	// 8 bits per transfer, no loopback, MSB first, 1 transfer per sync\r
	// pulse, no output sync, start on positive-going edge of sync\r
	SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(8) |\r
		SSC_FRAME_MODE_MSB_FIRST | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);\r
\r
	// clock comes from TK pin, no clock output, outputs change on falling\r
	// edge of TK, start on rising edge of TF\r
	SSC_TRANSMIT_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(2) |\r
		SSC_CLOCK_MODE_START(5);\r
\r
	// tx framing is the same as the rx framing\r
	SSC_TRANSMIT_FRAME_MODE = SSC_RECEIVE_FRAME_MODE;\r
\r
	SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;\r
}\r
\r
//-----------------------------------------------------------------------------\r
// Set up DMA to receive samples from the FPGA. We will use the PDC, with\r
// a single buffer as a circular buffer (so that we just chain back to\r
// ourselves, not to another buffer). The stuff to manipulate those buffers\r
// is in apps.h, because it should be inlined, for speed.\r
//-----------------------------------------------------------------------------\r
void FpgaSetupSscDma(BYTE *buf, int len)\r
{\r
	PDC_RX_POINTER(SSC_BASE) = (DWORD)buf;\r
	PDC_RX_COUNTER(SSC_BASE) = len;\r
	PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD)buf;\r
	PDC_RX_NEXT_COUNTER(SSC_BASE) = len;\r
	PDC_CONTROL(SSC_BASE) = PDC_RX_ENABLE;\r
}\r
\r
//-----------------------------------------------------------------------------\r
// Download the FPGA image stored in flash (slave serial).\r
//-----------------------------------------------------------------------------\r
void FpgaDownloadAndGo(void)\r
{\r
	// FPGA image lives in FLASH at base address 0x2000\r
	// The current board design can not accomodate anything bigger than a XC2S30\r
	// FPGA and the config file size is fixed at 336,768 bits = 10,524 DWORDs\r
	const DWORD *FpgaImage=((DWORD *)0x2000);\r
	const DWORD FpgaImageLen=10524;\r
\r
	int i, j;\r
\r
	PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);\r
	PIO_ENABLE = (1 << GPIO_FPGA_ON);\r
	PIO_OUTPUT_DATA_SET = (1 << GPIO_FPGA_ON);\r
\r
	SpinDelay(50);\r
\r
	LED_D_ON();\r
\r
	HIGH(GPIO_FPGA_NPROGRAM);\r
	LOW(GPIO_FPGA_CCLK);\r
	LOW(GPIO_FPGA_DIN);\r
	PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM)	|\r
						(1 << GPIO_FPGA_CCLK)		|\r
						(1 << GPIO_FPGA_DIN);\r
	SpinDelay(1);\r
\r
	LOW(GPIO_FPGA_NPROGRAM);\r
	SpinDelay(50);\r
	HIGH(GPIO_FPGA_NPROGRAM);\r
\r
	for(i = 0; i < FpgaImageLen; i++) {\r
		DWORD v = FpgaImage[i];\r
		for(j = 0; j < 32; j++) {\r
			if(v & 0x80000000) {\r
				HIGH(GPIO_FPGA_DIN);\r
			} else {\r
				LOW(GPIO_FPGA_DIN);\r
			}\r
			HIGH(GPIO_FPGA_CCLK);\r
			LOW(GPIO_FPGA_CCLK);\r
			v <<= 1;\r
		}\r
	}\r
\r
	LED_D_OFF();\r
}\r
\r
//-----------------------------------------------------------------------------\r
// Send a 16 bit command/data pair to the FPGA.\r
// The bit format is:  C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0\r
// where C is the 4 bit command and D is the 12 bit data\r
//-----------------------------------------------------------------------------\r
void FpgaSendCommand(WORD cmd, WORD v)\r
{\r
	SetupSpi(SPI_FPGA_MODE);\r
	while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0);		// wait for the transfer to complete\r
	SPI_TX_DATA = SPI_CONTROL_LAST_TRANSFER | cmd | v;		// send the data\r
}\r
//-----------------------------------------------------------------------------\r
// Write the FPGA setup word (that determines what mode the logic is in, read\r
// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to\r
// avoid changing this function's occurence everywhere in the source code.\r
//-----------------------------------------------------------------------------\r
void FpgaWriteConfWord(BYTE v)\r
{\r
	FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);\r
}\r
\r
//-----------------------------------------------------------------------------\r
// Set up the CMOS switches that mux the ADC: four switches, independently\r
// closable, but should only close one at a time. Not an FPGA thing, but\r
// the samples from the ADC always flow through the FPGA.\r
//-----------------------------------------------------------------------------\r
void SetAdcMuxFor(int whichGpio)\r
{\r
	PIO_OUTPUT_ENABLE = (1 << GPIO_MUXSEL_HIPKD) |\r
						(1 << GPIO_MUXSEL_LOPKD) |\r
						(1 << GPIO_MUXSEL_LORAW) |\r
						(1 << GPIO_MUXSEL_HIRAW);\r
\r
	PIO_ENABLE		=	(1 << GPIO_MUXSEL_HIPKD) |\r
						(1 << GPIO_MUXSEL_LOPKD) |\r
						(1 << GPIO_MUXSEL_LORAW) |\r
						(1 << GPIO_MUXSEL_HIRAW);\r
\r
	LOW(GPIO_MUXSEL_HIPKD);\r
	LOW(GPIO_MUXSEL_HIRAW);\r
	LOW(GPIO_MUXSEL_LORAW);\r
	LOW(GPIO_MUXSEL_LOPKD);\r
\r
	HIGH(whichGpio);\r
}\r
Commit	Line	Data
6658905f	1	//-----------------------------------------------------------------------------\r
	2	// Routines to load the FPGA image, and then to configure the FPGA's major\r
	3	// mode once it is configured.\r
	4	//\r
	5	// Jonathan Westhues, April 2006\r
	6	//-----------------------------------------------------------------------------\r
	7	#include <proxmark3.h>\r
	8	#include "apps.h"\r
	9	\r
	10	//-----------------------------------------------------------------------------\r
	11	// Set up the Serial Peripheral Interface as master\r
	12	// Used to write the FPGA config word\r
	13	// May also be used to write to other SPI attached devices like an LCD\r
	14	//-----------------------------------------------------------------------------\r
	15	void SetupSpi(int mode)\r
	16	{\r
	17	// PA10 -> SPI_NCS2 chip select (LCD)\r
	18	// PA11 -> SPI_NCS0 chip select (FPGA)\r
	19	// PA12 -> SPI_MISO Master-In Slave-Out\r
	20	// PA13 -> SPI_MOSI Master-Out Slave-In\r
	21	// PA14 -> SPI_SPCK Serial Clock\r
	22	\r
	23	// Disable PIO control of the following pins, allows use by the SPI peripheral\r
	24	PIO_DISABLE = (1 << GPIO_NCS0) \|\r
	25	(1 << GPIO_NCS2) \|\r
	26	(1 << GPIO_MISO) \|\r
	27	(1 << GPIO_MOSI) \|\r
	28	(1 << GPIO_SPCK);\r
	29	\r
	30	PIO_PERIPHERAL_A_SEL = (1 << GPIO_NCS0) \|\r
	31	(1 << GPIO_MISO) \|\r
	32	(1 << GPIO_MOSI) \|\r
	33	(1 << GPIO_SPCK);\r
	34	\r
	35	PIO_PERIPHERAL_B_SEL = (1 << GPIO_NCS2);\r
	36	\r
	37	//enable the SPI Peripheral clock\r
	38	PMC_PERIPHERAL_CLK_ENABLE = (1<<PERIPH_SPI);\r
	39	// Enable SPI\r
	40	SPI_CONTROL = SPI_CONTROL_ENABLE;\r
	41	\r
	42	switch (mode) {\r
	43	case SPI_FPGA_MODE:\r
	44	SPI_MODE =\r
	45	( 0 << 24) \| // Delay between chip selects (take default: 6 MCK periods)\r
	46	(14 << 16) \| // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)\r
	47	( 0 << 7) \| // Local Loopback Disabled\r
	48	( 1 << 4) \| // Mode Fault Detection disabled\r
	49	( 0 << 2) \| // Chip selects connected directly to peripheral\r
	50	( 0 << 1) \| // Fixed Peripheral Select\r
	51	( 1 << 0); // Master Mode\r
	52	SPI_FOR_CHIPSEL_0 =\r
	53	( 1 << 24) \| // Delay between Consecutive Transfers (32 MCK periods)\r
	54	( 1 << 16) \| // Delay Before SPCK (1 MCK period)\r
	55	( 6 << 8) \| // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
30f2a7d3	56	( 8 << 4) \| // Bits per Transfer (16 bits)\r
6658905f	57	( 0 << 3) \| // Chip Select inactive after transfer\r
	58	( 1 << 1) \| // Clock Phase data captured on leading edge, changes on following edge\r
	59	( 0 << 0); // Clock Polarity inactive state is logic 0\r
	60	break;\r
	61	case SPI_LCD_MODE:\r
	62	SPI_MODE =\r
	63	( 0 << 24) \| // Delay between chip selects (take default: 6 MCK periods)\r
	64	(11 << 16) \| // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)\r
	65	( 0 << 7) \| // Local Loopback Disabled\r
	66	( 1 << 4) \| // Mode Fault Detection disabled\r
	67	( 0 << 2) \| // Chip selects connected directly to peripheral\r
	68	( 0 << 1) \| // Fixed Peripheral Select\r
	69	( 1 << 0); // Master Mode\r
	70	SPI_FOR_CHIPSEL_2 =\r
	71	( 1 << 24) \| // Delay between Consecutive Transfers (32 MCK periods)\r
	72	( 1 << 16) \| // Delay Before SPCK (1 MCK period)\r
	73	( 6 << 8) \| // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
	74	( 1 << 4) \| // Bits per Transfer (9 bits)\r
	75	( 0 << 3) \| // Chip Select inactive after transfer\r
	76	( 1 << 1) \| // Clock Phase data captured on leading edge, changes on following edge\r
	77	( 0 << 0); // Clock Polarity inactive state is logic 0\r
	78	break;\r
	79	default: // Disable SPI\r
	80	SPI_CONTROL = SPI_CONTROL_DISABLE;\r
	81	break;\r
	82	}\r
	83	}\r
	84	\r
	85	//-----------------------------------------------------------------------------\r
	86	// Set up the synchronous serial port, with the one set of options that we\r
	87	// always use when we are talking to the FPGA. Both RX and TX are enabled.\r
	88	//-----------------------------------------------------------------------------\r
	89	void FpgaSetupSsc(void)\r
	90	{\r
	91	// First configure the GPIOs, and get ourselves a clock.\r
	92	PIO_PERIPHERAL_A_SEL = (1 << GPIO_SSC_FRAME) \|\r
	93	(1 << GPIO_SSC_DIN) \|\r
	94	(1 << GPIO_SSC_DOUT) \|\r
	95	(1 << GPIO_SSC_CLK);\r
	96	PIO_DISABLE = (1 << GPIO_SSC_DOUT);\r
	97	\r
	98	PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_SSC);\r
	99	\r
	100	// Now set up the SSC proper, starting from a known state.\r
	101	SSC_CONTROL = SSC_CONTROL_RESET;\r
	102	\r
	103	// RX clock comes from TX clock, RX starts when TX starts, data changes\r
	104	// on RX clock rising edge, sampled on falling edge\r
	105	SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(1) \| SSC_CLOCK_MODE_START(1);\r
	106	\r
	107	// 8 bits per transfer, no loopback, MSB first, 1 transfer per sync\r
	108	// pulse, no output sync, start on positive-going edge of sync\r
	109	SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(8) \|\r
	110	SSC_FRAME_MODE_MSB_FIRST \| SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);\r
	111	\r
	112	// clock comes from TK pin, no clock output, outputs change on falling\r
	113	// edge of TK, start on rising edge of TF\r
	114	SSC_TRANSMIT_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(2) \|\r
	115	SSC_CLOCK_MODE_START(5);\r
	116	\r
	117	// tx framing is the same as the rx framing\r
	118	SSC_TRANSMIT_FRAME_MODE = SSC_RECEIVE_FRAME_MODE;\r
	119	\r
	120	SSC_CONTROL = SSC_CONTROL_RX_ENABLE \| SSC_CONTROL_TX_ENABLE;\r
121	}\r
122	\r
123	//-----------------------------------------------------------------------------\r
124	// Set up DMA to receive samples from the FPGA. We will use the PDC, with\r
125	// a single buffer as a circular buffer (so that we just chain back to\r
126	// ourselves, not to another buffer). The stuff to manipulate those buffers\r
127	// is in apps.h, because it should be inlined, for speed.\r
128	//-----------------------------------------------------------------------------\r
129	void FpgaSetupSscDma(BYTE *buf, int len)\r
130	{\r
131	PDC_RX_POINTER(SSC_BASE) = (DWORD)buf;\r
132	PDC_RX_COUNTER(SSC_BASE) = len;\r
133	PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD)buf;\r
134	PDC_RX_NEXT_COUNTER(SSC_BASE) = len;\r
135	PDC_CONTROL(SSC_BASE) = PDC_RX_ENABLE;\r
136	}\r
137	\r
138	//-----------------------------------------------------------------------------\r
139	// Download the FPGA image stored in flash (slave serial).\r
140	//-----------------------------------------------------------------------------\r
141	void FpgaDownloadAndGo(void)\r
142	{\r
143	// FPGA image lives in FLASH at base address 0x2000\r
144	// The current board design can not accomodate anything bigger than a XC2S30\r
145	// FPGA and the config file size is fixed at 336,768 bits = 10,524 DWORDs\r
146	const DWORD FpgaImage=((DWORD )0x2000);\r
147	const DWORD FpgaImageLen=10524;\r
148	\r
149	int i, j;\r
150	\r
151	PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);\r
152	PIO_ENABLE = (1 << GPIO_FPGA_ON);\r
153	PIO_OUTPUT_DATA_SET = (1 << GPIO_FPGA_ON);\r
154	\r
155	SpinDelay(50);\r
156	\r
157	LED_D_ON();\r
158	\r
159	HIGH(GPIO_FPGA_NPROGRAM);\r
160	LOW(GPIO_FPGA_CCLK);\r
161	LOW(GPIO_FPGA_DIN);\r
162	PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM) \|\r
163	(1 << GPIO_FPGA_CCLK) \|\r
164	(1 << GPIO_FPGA_DIN);\r
165	SpinDelay(1);\r
166	\r
167	LOW(GPIO_FPGA_NPROGRAM);\r
168	SpinDelay(50);\r
169	HIGH(GPIO_FPGA_NPROGRAM);\r
170	\r
171	for(i = 0; i < FpgaImageLen; i++) {\r
172	DWORD v = FpgaImage[i];\r
173	for(j = 0; j < 32; j++) {\r
174	if(v & 0x80000000) {\r
175	HIGH(GPIO_FPGA_DIN);\r
176	} else {\r
177	LOW(GPIO_FPGA_DIN);\r
178	}\r
179	HIGH(GPIO_FPGA_CCLK);\r
180	LOW(GPIO_FPGA_CCLK);\r
181	v <<= 1;\r
182	}\r
183	}\r
184	\r
185	LED_D_OFF();\r
186	}\r
187	\r
30f2a7d3	188	//-----------------------------------------------------------------------------\r
	189	// Send a 16 bit command/data pair to the FPGA.\r
	190	// The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0\r
	191	// where C is the 4 bit command and D is the 12 bit data\r
	192	//-----------------------------------------------------------------------------\r
	193	void FpgaSendCommand(WORD cmd, WORD v)\r
	194	{\r
	195	SetupSpi(SPI_FPGA_MODE);\r
	196	while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0); // wait for the transfer to complete\r
	197	SPI_TX_DATA = SPI_CONTROL_LAST_TRANSFER \| cmd \| v; // send the data\r
	198	}\r
6658905f	199	//-----------------------------------------------------------------------------\r
6658905f	200	// Write the FPGA setup word (that determines what mode the logic is in, read\r
30f2a7d3	201	// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to\r
30f2a7d3	202	// avoid changing this function's occurence everywhere in the source code.\r
6658905f	203	//-----------------------------------------------------------------------------\r
	204	void FpgaWriteConfWord(BYTE v)\r
	205	{\r
30f2a7d3	206	FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);\r
6658905f	207	}\r
	208	\r
	209	//-----------------------------------------------------------------------------\r
	210	// Set up the CMOS switches that mux the ADC: four switches, independently\r
	211	// closable, but should only close one at a time. Not an FPGA thing, but\r
	212	// the samples from the ADC always flow through the FPGA.\r
	213	//-----------------------------------------------------------------------------\r
	214	void SetAdcMuxFor(int whichGpio)\r
	215	{\r
	216	PIO_OUTPUT_ENABLE = (1 << GPIO_MUXSEL_HIPKD) \|\r
	217	(1 << GPIO_MUXSEL_LOPKD) \|\r
	218	(1 << GPIO_MUXSEL_LORAW) \|\r
	219	(1 << GPIO_MUXSEL_HIRAW);\r
	220	\r
	221	PIO_ENABLE = (1 << GPIO_MUXSEL_HIPKD) \|\r
	222	(1 << GPIO_MUXSEL_LOPKD) \|\r
	223	(1 << GPIO_MUXSEL_LORAW) \|\r
	224	(1 << GPIO_MUXSEL_HIRAW);\r
	225	\r
	226	LOW(GPIO_MUXSEL_HIPKD);\r
	227	LOW(GPIO_MUXSEL_HIRAW);\r
	228	LOW(GPIO_MUXSEL_LORAW);\r
	229	LOW(GPIO_MUXSEL_LOPKD);\r
	230	\r
	231	HIGH(whichGpio);\r
	232	}\r