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1 | //----------------------------------------------------------------------------- |
2 | // The FPGA is responsible for interfacing between the A/D, the coil drivers, |
3 | // and the ARM. In the low-frequency modes it passes the data straight |
4 | // through, so that the ARM gets raw A/D samples over the SSP. In the high- |
5 | // frequency modes, the FPGA might perform some demodulation first, to |
6 | // reduce the amount of data that we must send to the ARM. |
7 | // |
8 | // I am not really an FPGA/ASIC designer, so I am sure that a lot of this |
9 | // could be improved. |
10 | // |
11 | // Jonathan Westhues, March 2006 |
12 | // Added ISO14443-A support by Gerhard de Koning Gans, April 2008 |
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13 | // iZsh <izsh at fail0verflow.com>, June 2014 |
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14 | //----------------------------------------------------------------------------- |
15 | |
16 | `include "hi_read_tx.v" |
17 | `include "hi_read_rx_xcorr.v" |
18 | `include "hi_simulate.v" |
19 | `include "hi_iso14443a.v" |
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20 | `include "hi_sniffer.v" |
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21 | `include "util.v" |
22 | |
23 | module fpga_hf( |
24 | input spck, output miso, input mosi, input ncs, |
25 | input pck0, input ck_1356meg, input ck_1356megb, |
26 | output pwr_lo, output pwr_hi, |
27 | output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4, |
28 | input [7:0] adc_d, output adc_clk, output adc_noe, |
29 | output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk, |
30 | input cross_hi, input cross_lo, |
31 | output dbg |
32 | ); |
33 | |
34 | //----------------------------------------------------------------------------- |
35 | // The SPI receiver. This sets up the configuration word, which the rest of |
36 | // the logic looks at to determine how to connect the A/D and the coil |
37 | // drivers (i.e., which section gets it). Also assign some symbolic names |
38 | // to the configuration bits, for use below. |
39 | //----------------------------------------------------------------------------- |
40 | |
41 | reg [15:0] shift_reg; |
42 | reg [7:0] conf_word; |
43 | |
44 | // We switch modes between transmitting to the 13.56 MHz tag and receiving |
45 | // from it, which means that we must make sure that we can do so without |
46 | // glitching, or else we will glitch the transmitted carrier. |
47 | always @(posedge ncs) |
48 | begin |
49 | case(shift_reg[15:12]) |
50 | 4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG |
51 | endcase |
52 | end |
53 | |
54 | always @(posedge spck) |
55 | begin |
56 | if(~ncs) |
57 | begin |
58 | shift_reg[15:1] <= shift_reg[14:0]; |
59 | shift_reg[0] <= mosi; |
60 | end |
61 | end |
62 | |
63 | wire [2:0] major_mode; |
64 | assign major_mode = conf_word[7:5]; |
65 | |
66 | // For the high-frequency transmit configuration: modulation depth, either |
67 | // 100% (just quite driving antenna, steady LOW), or shallower (tri-state |
68 | // some fraction of the buffers) |
69 | wire hi_read_tx_shallow_modulation = conf_word[0]; |
70 | |
71 | // For the high-frequency receive correlator: frequency against which to |
72 | // correlate. |
73 | wire hi_read_rx_xcorr_848 = conf_word[0]; |
74 | // and whether to drive the coil (reader) or just short it (snooper) |
75 | wire hi_read_rx_xcorr_snoop = conf_word[1]; |
76 | |
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77 | // For the high-frequency simulated tag: what kind of modulation to use. |
78 | wire [2:0] hi_simulate_mod_type = conf_word[2:0]; |
79 | |
80 | //----------------------------------------------------------------------------- |
81 | // And then we instantiate the modules corresponding to each of the FPGA's |
82 | // major modes, and use muxes to connect the outputs of the active mode to |
83 | // the output pins. |
84 | //----------------------------------------------------------------------------- |
85 | |
86 | hi_read_tx ht( |
87 | pck0, ck_1356meg, ck_1356megb, |
88 | ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4, |
89 | adc_d, ht_adc_clk, |
90 | ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk, |
91 | cross_hi, cross_lo, |
92 | ht_dbg, |
93 | hi_read_tx_shallow_modulation |
94 | ); |
95 | |
96 | hi_read_rx_xcorr hrxc( |
97 | pck0, ck_1356meg, ck_1356megb, |
98 | hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4, |
99 | adc_d, hrxc_adc_clk, |
100 | hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk, |
101 | cross_hi, cross_lo, |
102 | hrxc_dbg, |
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103 | hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop |
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104 | ); |
105 | |
106 | hi_simulate hs( |
107 | pck0, ck_1356meg, ck_1356megb, |
108 | hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4, |
109 | adc_d, hs_adc_clk, |
110 | hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk, |
111 | cross_hi, cross_lo, |
112 | hs_dbg, |
113 | hi_simulate_mod_type |
114 | ); |
115 | |
116 | hi_iso14443a hisn( |
117 | pck0, ck_1356meg, ck_1356megb, |
118 | hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4, |
119 | adc_d, hisn_adc_clk, |
120 | hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk, |
121 | cross_hi, cross_lo, |
122 | hisn_dbg, |
123 | hi_simulate_mod_type |
124 | ); |
125 | |
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126 | hi_sniffer he( |
127 | pck0, ck_1356meg, ck_1356megb, |
128 | he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4, |
129 | adc_d, he_adc_clk, |
130 | he_ssp_frame, he_ssp_din, ssp_dout, he_ssp_clk, |
131 | cross_hi, cross_lo, |
132 | he_dbg, |
133 | hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter |
134 | ); |
135 | |
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136 | // Major modes: |
137 | |
138 | // 000 -- HF reader, transmitting to tag; modulation depth selectable |
139 | // 001 -- HF reader, receiving from tag, correlating as it goes; frequency selectable |
140 | // 010 -- HF simulated tag |
141 | // 011 -- HF ISO14443-A |
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142 | // 100 -- HF Snoop |
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143 | // 111 -- everything off |
144 | |
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145 | mux8 mux_ssp_clk (major_mode, ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, 1'b0, 1'b0, 1'b0); |
146 | mux8 mux_ssp_din (major_mode, ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, 1'b0, 1'b0, 1'b0); |
147 | mux8 mux_ssp_frame (major_mode, ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, 1'b0, 1'b0, 1'b0); |
148 | mux8 mux_pwr_oe1 (major_mode, pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, 1'b0, 1'b0, 1'b0); |
149 | mux8 mux_pwr_oe2 (major_mode, pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, 1'b0, 1'b0, 1'b0); |
150 | mux8 mux_pwr_oe3 (major_mode, pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, 1'b0, 1'b0, 1'b0); |
151 | mux8 mux_pwr_oe4 (major_mode, pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, 1'b0, 1'b0, 1'b0); |
152 | mux8 mux_pwr_lo (major_mode, pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, 1'b0, 1'b0, 1'b0); |
153 | mux8 mux_pwr_hi (major_mode, pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, 1'b0, 1'b0, 1'b0); |
154 | mux8 mux_adc_clk (major_mode, adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, 1'b0, 1'b0, 1'b0); |
155 | mux8 mux_dbg (major_mode, dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, he_dbg, 1'b0, 1'b0, 1'b0); |
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156 | |
157 | // In all modes, let the ADC's outputs be enabled. |
158 | assign adc_noe = 1'b0; |
159 | |
160 | endmodule |