[proxmark3-svn] / armsrc / legicrf.c

/*
 * LEGIC RF simulation code
 *  
 * (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
 */

#include <proxmark3.h>

#include "apps.h"
#include "legicrf.h"
#include <stdint.h>

#include "legic_prng.h"
#include "crc.h"

static struct legic_frame {
	int bits;
	uint32_t data;
} current_frame;

static crc_t legic_crc;

AT91PS_TC timer;

static void setup_timer(void)
{
	/* Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
	 * this it won't be terribly accurate but should be good enough.
	 */
	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
	timer = AT91C_BASE_TC1;
	timer->TC_CCR = AT91C_TC_CLKDIS;
	timer->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK3;
	timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;

/* At TIMER_CLOCK3 (MCK/32) */
#define	RWD_TIME_1 150     /* RWD_TIME_PAUSE off, 80us on = 100us */
#define RWD_TIME_0 90      /* RWD_TIME_PAUSE off, 40us on = 60us */
#define RWD_TIME_PAUSE 30  /* 20us */
#define RWD_TIME_FUZZ 20   /* rather generous 13us, since the peak detector + hysteresis fuzz quite a bit */
#define TAG_TIME_BIT 150   /* 100us for every bit */
#define TAG_TIME_WAIT 490  /* time from RWD frame end to tag frame start, experimentally determined */

}

#define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))

/* Send a frame in reader mode, the FPGA must have been set up by
 * LegicRfReader
 */
static void frame_send_rwd(uint32_t data, int bits)
{
	/* Start clock */
	timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
	while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
	
	int i;
	for(i=0; i<bits; i++) {
		int starttime = timer->TC_CV;
		int pause_end = starttime + RWD_TIME_PAUSE, bit_end;
		int bit = data & 1;
		data = data >> 1;

		if(bit ^ legic_prng_get_bit()) {
			bit_end = starttime + RWD_TIME_1;
		} else {
			bit_end = starttime + RWD_TIME_0;
		}
		
		/* RWD_TIME_PAUSE time off, then some time on, so that the complete bit time is
		 * RWD_TIME_x, where x is the bit to be transmitted */
		AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
		while(timer->TC_CV < pause_end) ;
		AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
		legic_prng_forward(1); /* bit duration is longest. use this time to forward the lfsr */
		
		while(timer->TC_CV < bit_end) ;
	}
	
	{
		/* One final pause to mark the end of the frame */
		int pause_end = timer->TC_CV + RWD_TIME_PAUSE;
		AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
		while(timer->TC_CV < pause_end) ;
		AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
	}
	
	/* Reset the timer, to measure time until the start of the tag frame */
	timer->TC_CCR = AT91C_TC_SWTRG;
	while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
}

/* Receive a frame from the card in reader emulation mode, the FPGA and
 * timer must have been set up by LegicRfReader and frame_send_rwd.
 * 
 * The LEGIC RF protocol from card to reader does not include explicit
 * frame start/stop information or length information. The reader must
 * know beforehand how many bits it wants to receive. (Notably: a card
 * sending a stream of 0-bits is indistinguishable from no card present.)
 * 
 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
 * for edges. Count the edges in each bit interval. If they are approximately
 * 0 this was a 0-bit, if they are approximately equal to the number of edges
 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
 * timer that's still running from frame_send_rwd in order to get a synchronization
 * with the frame that we just sent.
 * 
 * FIXME: Because we're relying on the hysteresis to just do the right thing 
 * the range is severely reduced (and you'll probably also need a good antenna).
 * So this should be fixed some time in the future for a proper receiver. 
 */
static void frame_receive_rwd(struct legic_frame * const f, int bits, int crypt)
{
	uint32_t the_bit = 1;  /* Use a bitmask to save on shifts */
	uint32_t data=0;
	int i, old_level=0, edges=0;
	int next_bit_at = TAG_TIME_WAIT;
	
	
	if(bits > 16)
		bits = 16;

	AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
	AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;

	/* we have some time now, precompute the cipher
         * since we cannot compute it on the fly while reading */
	legic_prng_forward(2);

	if(crypt)
	{
		for(i=0; i<bits; i++) {
			data |= legic_prng_get_bit() << i;
			legic_prng_forward(1);
		}
	}

	while(timer->TC_CV < next_bit_at) ;

	next_bit_at += TAG_TIME_BIT;
	
	for(i=0; i<bits; i++) {
		edges = 0;

		while(timer->TC_CV < next_bit_at) {
			int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
			if(level != old_level)
				edges++;
			old_level = level;
		}
		next_bit_at += TAG_TIME_BIT;
		
		if(edges > 20 && edges < 60) { /* expected are 42 edges */
			data ^= the_bit;
		}

		the_bit <<= 1;
	}
	
	f->data = data;
	f->bits = bits;
	
	/* Reset the timer, to synchronize the next frame */
	timer->TC_CCR = AT91C_TC_SWTRG;
	while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
}

static void frame_clean(struct legic_frame * const f)
{
	f->data = 0;
	f->bits = 0;
}

static uint32_t perform_setup_phase_rwd(int iv)
{
	
	/* Switch on carrier and let the tag charge for 1ms */
	AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
	SpinDelay(1);
	
	legic_prng_init(0); /* no keystream yet */
	frame_send_rwd(iv, 7);
        legic_prng_init(iv);
	
	frame_clean(&current_frame);
	frame_receive_rwd(&current_frame, 6, 1);
	legic_prng_forward(1); /* we wait anyways */
	while(timer->TC_CV < 387) ; /* ~ 258us */
	frame_send_rwd(0x19, 6);

	return current_frame.data;
}

static void LegicCommonInit(void) {
	SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
	FpgaSetupSsc();
	FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
	
	/* Bitbang the transmitter */
	AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
	AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
	AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
	
	setup_timer();
	
	crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
}

static void switch_off_tag_rwd(void)
{
	/* Switch off carrier, make sure tag is reset */
	AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
	SpinDelay(10);
	
	WDT_HIT();
}
/* calculate crc for a legic command */
static int LegicCRC(int byte_index, int value, int cmd_sz) {
	crc_clear(&legic_crc);
	crc_update(&legic_crc, 1, 1); /* CMD_READ */
	crc_update(&legic_crc, byte_index, cmd_sz-1);
	crc_update(&legic_crc, value, 8);
	return crc_finish(&legic_crc);
}

int legic_read_byte(int byte_index, int cmd_sz) {
	int byte;

	legic_prng_forward(4); /* we wait anyways */
    	while(timer->TC_CV < 387) ; /* ~ 258us + 100us*delay */

	frame_send_rwd(1 | (byte_index << 1), cmd_sz);
	frame_clean(&current_frame);

	frame_receive_rwd(&current_frame, 12, 1);

	byte = current_frame.data & 0xff;
	if( LegicCRC(byte_index, byte, cmd_sz) != (current_frame.data >> 8) ) {
		Dbprintf("!!! crc mismatch: expected %x but got %x !!!", LegicCRC(byte_index, current_frame.data & 0xff, cmd_sz), current_frame.data >> 8);
		return -1;
	}

	return byte;
}

/* legic_write_byte() is not included, however it's trivial to implement
 * and here are some hints on what remains to be done:
 *
 *  * assemble a write_cmd_frame with crc and send it
 *  * wait until the tag sends back an ACK ('1' bit unencrypted)
 *  * forward the prng based on the timing
 */


void LegicRfReader(int offset, int bytes) {
	int byte_index=0, cmd_sz=0, card_sz=0;
	
	LegicCommonInit();

	memset(BigBuf, 0, 1024);
	
	DbpString("setting up legic card");
	uint32_t tag_type = perform_setup_phase_rwd(0x55);
	switch(tag_type) {
		case 0x1d:
			DbpString("MIM 256 card found, reading card ...");
	                cmd_sz = 9;
			card_sz = 256;
			break;
		case 0x3d:
			DbpString("MIM 1024 card found, reading card ...");
	                cmd_sz = 11;
			card_sz = 1024;
			break;
		default:
			Dbprintf("Unknown card format: %x",tag_type);
 			switch_off_tag_rwd();
	                return;
	}
	if(bytes == -1) {
		bytes = card_sz;
	}
        if(bytes+offset >= card_sz) {
		bytes = card_sz-offset;
        }

	switch_off_tag_rwd(); //we lost to mutch time with dprintf
	perform_setup_phase_rwd(0x55);

	while(byte_index < bytes) {
                int r = legic_read_byte(byte_index+offset, cmd_sz);
                if(r == -1) {
			Dbprintf("aborting");
 			switch_off_tag_rwd();
	                return;
		}
		((uint8_t*)BigBuf)[byte_index] = r;
		byte_index++;
	}
	switch_off_tag_rwd();
	Dbprintf("Card read, use 'hf legic decode' or 'data hexsamples %d' to view results", (bytes+7) & ~7);
}
Commit	Line	Data
a7247d85	1	/*
	2	* LEGIC RF simulation code
	3	*
	4	* (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
	5	*/
	6
	7	#include <proxmark3.h>
	8
	9	#include "apps.h"
	10	#include "legicrf.h"
5e174a51	11	#include <stdint.h>
a7247d85	12
8e220a91	13	#include "legic_prng.h"
	14	#include "crc.h"
	15
a7247d85	16	static struct legic_frame {
ccedd6ae	17	int bits;
a2b1414f	18	uint32_t data;
a7247d85	19	} current_frame;
8e220a91	20
	21	static crc_t legic_crc;
	22
add16a62	23	AT91PS_TC timer;
	24
	25	static void setup_timer(void)
	26	{
	27	/* Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
	28	* this it won't be terribly accurate but should be good enough.
	29	*/
	30	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
	31	timer = AT91C_BASE_TC1;
	32	timer->TC_CCR = AT91C_TC_CLKDIS;
	33	timer->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK3;
	34	timer->TC_CCR = AT91C_TC_CLKEN \| AT91C_TC_SWTRG;
	35
	36	/* At TIMER_CLOCK3 (MCK/32) */
	37	#define RWD_TIME_1 150 /* RWD_TIME_PAUSE off, 80us on = 100us */
	38	#define RWD_TIME_0 90 /* RWD_TIME_PAUSE off, 40us on = 60us */
	39	#define RWD_TIME_PAUSE 30 /* 20us */
	40	#define RWD_TIME_FUZZ 20 /* rather generous 13us, since the peak detector + hysteresis fuzz quite a bit */
	41	#define TAG_TIME_BIT 150 /* 100us for every bit */
	42	#define TAG_TIME_WAIT 490 /* time from RWD frame end to tag frame start, experimentally determined */
	43
	44	}
	45
	46	#define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
aac23b24	47
dcc10e5e	48	/* Send a frame in reader mode, the FPGA must have been set up by
	49	* LegicRfReader
	50	*/
8e220a91	51	static void frame_send_rwd(uint32_t data, int bits)
dcc10e5e	52	{
	53	/* Start clock */
	54	timer->TC_CCR = AT91C_TC_CLKEN \| AT91C_TC_SWTRG;
	55	while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
	56
	57	int i;
	58	for(i=0; i<bits; i++) {
	59	int starttime = timer->TC_CV;
	60	int pause_end = starttime + RWD_TIME_PAUSE, bit_end;
	61	int bit = data & 1;
	62	data = data >> 1;
8e220a91	63
8e220a91	64	if(bit ^ legic_prng_get_bit()) {
dcc10e5e	65	bit_end = starttime + RWD_TIME_1;
	66	} else {
	67	bit_end = starttime + RWD_TIME_0;
	68	}
	69
	70	/* RWD_TIME_PAUSE time off, then some time on, so that the complete bit time is
	71	* RWD_TIME_x, where x is the bit to be transmitted */
	72	AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
	73	while(timer->TC_CV < pause_end) ;
	74	AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
8e220a91	75	legic_prng_forward(1); /* bit duration is longest. use this time to forward the lfsr */
8e220a91	76
dcc10e5e	77	while(timer->TC_CV < bit_end) ;
	78	}
	79
	80	{
	81	/* One final pause to mark the end of the frame */
	82	int pause_end = timer->TC_CV + RWD_TIME_PAUSE;
	83	AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
	84	while(timer->TC_CV < pause_end) ;
	85	AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
	86	}
	87
	88	/* Reset the timer, to measure time until the start of the tag frame */
	89	timer->TC_CCR = AT91C_TC_SWTRG;
2561caa2	90	while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
dcc10e5e	91	}
	92
	93	/* Receive a frame from the card in reader emulation mode, the FPGA and
	94	* timer must have been set up by LegicRfReader and frame_send_rwd.
	95	*
	96	* The LEGIC RF protocol from card to reader does not include explicit
	97	* frame start/stop information or length information. The reader must
	98	* know beforehand how many bits it wants to receive. (Notably: a card
	99	* sending a stream of 0-bits is indistinguishable from no card present.)
	100	*
	101	* Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
	102	* I'm not smart enough to use it. Instead I have patched hi_read_tx to output
	103	* the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
	104	* for edges. Count the edges in each bit interval. If they are approximately
	105	* 0 this was a 0-bit, if they are approximately equal to the number of edges
	106	* expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
	107	* timer that's still running from frame_send_rwd in order to get a synchronization
	108	* with the frame that we just sent.
	109	*
	110	* FIXME: Because we're relying on the hysteresis to just do the right thing
	111	* the range is severely reduced (and you'll probably also need a good antenna).
	112	* So this should be fixed some time in the future for a proper receiver.
	113	*/
8e220a91	114	static void frame_receive_rwd(struct legic_frame * const f, int bits, int crypt)
dcc10e5e	115	{
a2b1414f	116	uint32_t the_bit = 1; /* Use a bitmask to save on shifts */
a2b1414f	117	uint32_t data=0;
dcc10e5e	118	int i, old_level=0, edges=0;
	119	int next_bit_at = TAG_TIME_WAIT;
	120
	121
	122	if(bits > 16)
	123	bits = 16;
	124
	125	AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
	126	AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
	127
8e220a91	128	/* we have some time now, precompute the cipher
	129	* since we cannot compute it on the fly while reading */
	130	legic_prng_forward(2);
	131
	132	if(crypt)
	133	{
	134	for(i=0; i<bits; i++) {
	135	data \|= legic_prng_get_bit() << i;
	136	legic_prng_forward(1);
	137	}
	138	}
	139
dcc10e5e	140	while(timer->TC_CV < next_bit_at) ;
8e220a91	141
dcc10e5e	142	next_bit_at += TAG_TIME_BIT;
	143
	144	for(i=0; i<bits; i++) {
	145	edges = 0;
8e220a91	146
dcc10e5e	147	while(timer->TC_CV < next_bit_at) {
	148	int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
	149	if(level != old_level)
	150	edges++;
	151	old_level = level;
	152	}
	153	next_bit_at += TAG_TIME_BIT;
	154
	155	if(edges > 20 && edges < 60) { /* expected are 42 edges */
8e220a91	156	data ^= the_bit;
dcc10e5e	157	}
8e220a91	158
dcc10e5e	159	the_bit <<= 1;
	160	}
	161
	162	f->data = data;
	163	f->bits = bits;
2561caa2	164
	165	/* Reset the timer, to synchronize the next frame */
	166	timer->TC_CCR = AT91C_TC_SWTRG;
	167	while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
dcc10e5e	168	}
dcc10e5e	169
ccedd6ae	170	static void frame_clean(struct legic_frame * const f)
a7247d85	171	{
ccedd6ae	172	f->data = 0;
ccedd6ae	173	f->bits = 0;
a7247d85	174	}
a7247d85	175
a2b1414f	176	static uint32_t perform_setup_phase_rwd(int iv)
2561caa2	177	{
	178
	179	/* Switch on carrier and let the tag charge for 1ms */
	180	AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
	181	SpinDelay(1);
	182
8e220a91	183	legic_prng_init(0); /* no keystream yet */
	184	frame_send_rwd(iv, 7);
	185	legic_prng_init(iv);
	186
2561caa2	187	frame_clean(&current_frame);
8e220a91	188	frame_receive_rwd(&current_frame, 6, 1);
8e220a91	189	legic_prng_forward(1); /* we wait anyways */
2561caa2	190	while(timer->TC_CV < 387) ; /* ~ 258us */
8e220a91	191	frame_send_rwd(0x19, 6);
2561caa2	192
8e220a91	193	return current_frame.data;
2561caa2	194	}
2561caa2	195
8e220a91	196	static void LegicCommonInit(void) {
dcc10e5e	197	SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
	198	FpgaSetupSsc();
	199	FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
	200
	201	/* Bitbang the transmitter */
	202	AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
	203	AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
	204	AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
	205
	206	setup_timer();
	207
8e220a91	208	crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
	209	}
	210
	211	static void switch_off_tag_rwd(void)
	212	{
	213	/* Switch off carrier, make sure tag is reset */
	214	AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
	215	SpinDelay(10);
2561caa2	216
8e220a91	217	WDT_HIT();
	218	}
	219	/* calculate crc for a legic command */
a2b1414f	220	static int LegicCRC(int byte_index, int value, int cmd_sz) {
8e220a91	221	crc_clear(&legic_crc);
8e220a91	222	crc_update(&legic_crc, 1, 1); /* CMD_READ */
a2b1414f	223	crc_update(&legic_crc, byte_index, cmd_sz-1);
8e220a91	224	crc_update(&legic_crc, value, 8);
	225	return crc_finish(&legic_crc);
	226	}
	227
a2b1414f	228	int legic_read_byte(int byte_index, int cmd_sz) {
8e220a91	229	int byte;
	230
	231	legic_prng_forward(4); /* we wait anyways */
	232	while(timer->TC_CV < 387) ; /* ~ 258us + 100usdelay /
	233
a2b1414f	234	frame_send_rwd(1 \| (byte_index << 1), cmd_sz);
8e220a91	235	frame_clean(&current_frame);
	236
	237	frame_receive_rwd(&current_frame, 12, 1);
	238
	239	byte = current_frame.data & 0xff;
a2b1414f	240	if( LegicCRC(byte_index, byte, cmd_sz) != (current_frame.data >> 8) ) {
	241	Dbprintf("!!! crc mismatch: expected %x but got %x !!!", LegicCRC(byte_index, current_frame.data & 0xff, cmd_sz), current_frame.data >> 8);
	242	return -1;
	243	}
8e220a91	244
	245	return byte;
	246	}
	247
	248	/* legic_write_byte() is not included, however it's trivial to implement
	249	* and here are some hints on what remains to be done:
	250	*
	251	* * assemble a write_cmd_frame with crc and send it
	252	* * wait until the tag sends back an ACK ('1' bit unencrypted)
	253	* * forward the prng based on the timing
	254	*/
	255
	256
	257	void LegicRfReader(int offset, int bytes) {
a2b1414f	258	int byte_index=0, cmd_sz=0, card_sz=0;
2561caa2	259
8e220a91	260	LegicCommonInit();
8e220a91	261
a2b1414f	262	memset(BigBuf, 0, 1024);
2561caa2	263
8e220a91	264	DbpString("setting up legic card");
a2b1414f	265	uint32_t tag_type = perform_setup_phase_rwd(0x55);
	266	switch(tag_type) {
	267	case 0x1d:
	268	DbpString("MIM 256 card found, reading card ...");
	269	cmd_sz = 9;
	270	card_sz = 256;
	271	break;
	272	case 0x3d:
	273	DbpString("MIM 1024 card found, reading card ...");
	274	cmd_sz = 11;
	275	card_sz = 1024;
	276	break;
	277	default:
b279e3ef	278	Dbprintf("Unknown card format: %x",tag_type);
a2b1414f	279	switch_off_tag_rwd();
	280	return;
	281	}
	282	if(bytes == -1) {
	283	bytes = card_sz;
	284	}
	285	if(bytes+offset >= card_sz) {
	286	bytes = card_sz-offset;
	287	}
	288
	289	switch_off_tag_rwd(); //we lost to mutch time with dprintf
8e220a91	290	perform_setup_phase_rwd(0x55);
	291
	292	while(byte_index < bytes) {
a2b1414f	293	int r = legic_read_byte(byte_index+offset, cmd_sz);
	294	if(r == -1) {
	295	Dbprintf("aborting");
	296	switch_off_tag_rwd();
	297	return;
	298	}
	299	((uint8_t*)BigBuf)[byte_index] = r;
2561caa2	300	byte_index++;
2561caa2	301	}
8e220a91	302	switch_off_tag_rwd();
4c8db262	303	Dbprintf("Card read, use 'hf legic decode' or 'data hexsamples %d' to view results", (bytes+7) & ~7);
dcc10e5e	304	}
a2b1414f	305