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15c4dc5a 1//-----------------------------------------------------------------------------
bd20f8f4 2// Jonathan Westhues, April 2006
62638f87 3// iZsh <izsh at fail0verflow.com>, 2014
bd20f8f4 4//
5// This code is licensed to you under the terms of the GNU GPL, version 2 or,
6// at your option, any later version. See the LICENSE.txt file for the text of
7// the license.
8//-----------------------------------------------------------------------------
15c4dc5a 9// Routines to load the FPGA image, and then to configure the FPGA's major
10// mode once it is configured.
15c4dc5a 11//-----------------------------------------------------------------------------
add4d470 12
13#include <stdint.h>
14#include <stddef.h>
15#include <stdbool.h>
16#include "fpgaloader.h"
e30c654b 17#include "proxmark3.h"
f7e3ed82 18#include "util.h"
9ab7a6c7 19#include "string.h"
add4d470 20#include "BigBuf.h"
21#include "zlib.h"
22
23extern void Dbprintf(const char *fmt, ...);
15c4dc5a 24
e6153040 25// remember which version of the bitstream we have already downloaded to the FPGA
26static int downloaded_bitstream = FPGA_BITSTREAM_ERR;
27
28// this is where the bitstreams are located in memory:
fb228974 29extern uint8_t _binary_obj_fpga_all_bit_z_start, _binary_obj_fpga_all_bit_z_end;
30
e6153040 31static uint8_t *fpga_image_ptr = NULL;
fb228974 32static uint32_t uncompressed_bytes_cnt;
e6153040 33
34static const uint8_t _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
e6153040 35#define FPGA_BITSTREAM_FIXED_HEADER_SIZE sizeof(_bitparse_fixed_header)
fb228974 36#define OUTPUT_BUFFER_LEN 80
37#define FPGA_INTERLEAVE_SIZE 288
e6153040 38
15c4dc5a 39//-----------------------------------------------------------------------------
40// Set up the Serial Peripheral Interface as master
41// Used to write the FPGA config word
42// May also be used to write to other SPI attached devices like an LCD
43//-----------------------------------------------------------------------------
44void SetupSpi(int mode)
45{
46 // PA10 -> SPI_NCS2 chip select (LCD)
47 // PA11 -> SPI_NCS0 chip select (FPGA)
48 // PA12 -> SPI_MISO Master-In Slave-Out
49 // PA13 -> SPI_MOSI Master-Out Slave-In
50 // PA14 -> SPI_SPCK Serial Clock
51
52 // Disable PIO control of the following pins, allows use by the SPI peripheral
53 AT91C_BASE_PIOA->PIO_PDR =
54 GPIO_NCS0 |
55 GPIO_NCS2 |
56 GPIO_MISO |
57 GPIO_MOSI |
58 GPIO_SPCK;
59
60 AT91C_BASE_PIOA->PIO_ASR =
61 GPIO_NCS0 |
62 GPIO_MISO |
63 GPIO_MOSI |
64 GPIO_SPCK;
65
66 AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;
67
68 //enable the SPI Peripheral clock
69 AT91C_BASE_PMC->PMC_PCER = (1<<AT91C_ID_SPI);
70 // Enable SPI
71 AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
72
73 switch (mode) {
74 case SPI_FPGA_MODE:
75 AT91C_BASE_SPI->SPI_MR =
76 ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
77 (14 << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
78 ( 0 << 7) | // Local Loopback Disabled
79 ( 1 << 4) | // Mode Fault Detection disabled
80 ( 0 << 2) | // Chip selects connected directly to peripheral
81 ( 0 << 1) | // Fixed Peripheral Select
82 ( 1 << 0); // Master Mode
83 AT91C_BASE_SPI->SPI_CSR[0] =
84 ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
85 ( 1 << 16) | // Delay Before SPCK (1 MCK period)
86 ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
87 ( 8 << 4) | // Bits per Transfer (16 bits)
88 ( 0 << 3) | // Chip Select inactive after transfer
89 ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
90 ( 0 << 0); // Clock Polarity inactive state is logic 0
91 break;
92 case SPI_LCD_MODE:
93 AT91C_BASE_SPI->SPI_MR =
94 ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
95 (11 << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
96 ( 0 << 7) | // Local Loopback Disabled
97 ( 1 << 4) | // Mode Fault Detection disabled
98 ( 0 << 2) | // Chip selects connected directly to peripheral
99 ( 0 << 1) | // Fixed Peripheral Select
100 ( 1 << 0); // Master Mode
101 AT91C_BASE_SPI->SPI_CSR[2] =
102 ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
103 ( 1 << 16) | // Delay Before SPCK (1 MCK period)
104 ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
105 ( 1 << 4) | // Bits per Transfer (9 bits)
106 ( 0 << 3) | // Chip Select inactive after transfer
107 ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
108 ( 0 << 0); // Clock Polarity inactive state is logic 0
109 break;
110 default: // Disable SPI
111 AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
112 break;
113 }
114}
115
116//-----------------------------------------------------------------------------
117// Set up the synchronous serial port, with the one set of options that we
118// always use when we are talking to the FPGA. Both RX and TX are enabled.
119//-----------------------------------------------------------------------------
120void FpgaSetupSsc(void)
121{
122 // First configure the GPIOs, and get ourselves a clock.
123 AT91C_BASE_PIOA->PIO_ASR =
124 GPIO_SSC_FRAME |
125 GPIO_SSC_DIN |
126 GPIO_SSC_DOUT |
127 GPIO_SSC_CLK;
128 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
129
130 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC);
131
132 // Now set up the SSC proper, starting from a known state.
133 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
134
135 // RX clock comes from TX clock, RX starts when TX starts, data changes
136 // on RX clock rising edge, sampled on falling edge
137 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
138
139 // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
d714d3ef 140 // pulse, no output sync
902cb3c0 141 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
15c4dc5a 142
143 // clock comes from TK pin, no clock output, outputs change on falling
d714d3ef 144 // edge of TK, sample on rising edge of TK, start on positive-going edge of sync
902cb3c0 145 AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5);
15c4dc5a 146
147 // tx framing is the same as the rx framing
148 AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
149
150 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
151}
152
153//-----------------------------------------------------------------------------
154// Set up DMA to receive samples from the FPGA. We will use the PDC, with
155// a single buffer as a circular buffer (so that we just chain back to
156// ourselves, not to another buffer). The stuff to manipulate those buffers
157// is in apps.h, because it should be inlined, for speed.
158//-----------------------------------------------------------------------------
d19929cb 159bool FpgaSetupSscDma(uint8_t *buf, int len)
15c4dc5a 160{
d19929cb 161 if (buf == NULL) {
162 return false;
163 }
164
7bc95e2e 165 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; // Disable DMA Transfer
166 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf; // transfer to this memory address
167 AT91C_BASE_PDC_SSC->PDC_RCR = len; // transfer this many bytes
168 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf; // next transfer to same memory address
169 AT91C_BASE_PDC_SSC->PDC_RNCR = len; // ... with same number of bytes
170 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; // go!
d19929cb 171
172 return true;
15c4dc5a 173}
174
e6153040 175
8e074056 176//----------------------------------------------------------------------------
177// Uncompress (inflate) the FPGA data. Returns one decompressed byte with
178// each call.
179//----------------------------------------------------------------------------
fb228974 180static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer)
e6153040 181{
add4d470 182 if (fpga_image_ptr == compressed_fpga_stream->next_out) { // need more data
183 compressed_fpga_stream->next_out = output_buffer;
184 compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
185 fpga_image_ptr = output_buffer;
186 int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);
25056d8b 187 if (res != Z_OK) {
add4d470 188 Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);
25056d8b 189 }
190 if (res < 0) {
191 return res;
192 }
add4d470 193 }
194
fb228974 195 uncompressed_bytes_cnt++;
196
add4d470 197 return *fpga_image_ptr++;
e6153040 198}
199
8e074056 200//----------------------------------------------------------------------------
201// Undo the interleaving of several FPGA config files. FPGA config files
202// are combined into one big file:
203// 288 bytes from FPGA file 1, followed by 288 bytes from FGPA file 2, etc.
204//----------------------------------------------------------------------------
fb228974 205static int get_from_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
206{
207 while((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % FPGA_BITSTREAM_MAX != (bitstream_version - 1)) {
208 // skip undesired data belonging to other bitstream_versions
209 get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
210 }
211
212 return get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
213
214}
215
216
add4d470 217static voidpf fpga_inflate_malloc(voidpf opaque, uInt items, uInt size)
e6153040 218{
add4d470 219 return BigBuf_malloc(items*size);
220}
221
222
223static void fpga_inflate_free(voidpf opaque, voidpf address)
224{
8e074056 225 BigBuf_free();
add4d470 226}
227
228
8e074056 229//----------------------------------------------------------------------------
230// Initialize decompression of the respective (HF or LF) FPGA stream
231//----------------------------------------------------------------------------
25056d8b 232static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
add4d470 233{
234 uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
add4d470 235
fb228974 236 uncompressed_bytes_cnt = 0;
237
25056d8b 238 // initialize z_stream structure for inflate:
fb228974 239 compressed_fpga_stream->next_in = &_binary_obj_fpga_all_bit_z_start;
240 compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_start - &_binary_obj_fpga_all_bit_z_end;
25056d8b 241 compressed_fpga_stream->next_out = output_buffer;
242 compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
243 compressed_fpga_stream->zalloc = &fpga_inflate_malloc;
244 compressed_fpga_stream->zfree = &fpga_inflate_free;
245
8e074056 246 inflateInit2(compressed_fpga_stream, 0);
25056d8b 247
248 fpga_image_ptr = output_buffer;
add4d470 249
250 for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++) {
fb228974 251 header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
add4d470 252 }
253
254 // Check for a valid .bit file (starts with _bitparse_fixed_header)
255 if(memcmp(_bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0) {
256 return true;
257 } else {
258 return false;
259 }
e6153040 260}
261
262
15c4dc5a 263static void DownloadFPGA_byte(unsigned char w)
264{
265#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }
266 SEND_BIT(7);
267 SEND_BIT(6);
268 SEND_BIT(5);
269 SEND_BIT(4);
270 SEND_BIT(3);
271 SEND_BIT(2);
272 SEND_BIT(1);
273 SEND_BIT(0);
274}
275
e6153040 276// Download the fpga image starting at current stream position with length FpgaImageLen bytes
fb228974 277static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
15c4dc5a 278{
add4d470 279
25056d8b 280 Dbprintf("DownloadFPGA(len: %d)", FpgaImageLen);
281
15c4dc5a 282 int i=0;
283
284 AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
285 AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
286 HIGH(GPIO_FPGA_ON); // ensure everything is powered on
287
288 SpinDelay(50);
289
290 LED_D_ON();
291
292 // These pins are inputs
293 AT91C_BASE_PIOA->PIO_ODR =
294 GPIO_FPGA_NINIT |
295 GPIO_FPGA_DONE;
296 // PIO controls the following pins
297 AT91C_BASE_PIOA->PIO_PER =
298 GPIO_FPGA_NINIT |
299 GPIO_FPGA_DONE;
300 // Enable pull-ups
301 AT91C_BASE_PIOA->PIO_PPUER =
302 GPIO_FPGA_NINIT |
303 GPIO_FPGA_DONE;
304
305 // setup initial logic state
306 HIGH(GPIO_FPGA_NPROGRAM);
307 LOW(GPIO_FPGA_CCLK);
308 LOW(GPIO_FPGA_DIN);
309 // These pins are outputs
310 AT91C_BASE_PIOA->PIO_OER =
311 GPIO_FPGA_NPROGRAM |
312 GPIO_FPGA_CCLK |
313 GPIO_FPGA_DIN;
314
315 // enter FPGA configuration mode
316 LOW(GPIO_FPGA_NPROGRAM);
317 SpinDelay(50);
318 HIGH(GPIO_FPGA_NPROGRAM);
319
320 i=100000;
321 // wait for FPGA ready to accept data signal
322 while ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) {
323 i--;
324 }
325
326 // crude error indicator, leave both red LEDs on and return
327 if (i==0){
328 LED_C_ON();
329 LED_D_ON();
330 return;
331 }
332
25056d8b 333 for(i = 0; i < FpgaImageLen; i++) {
fb228974 334 int b = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
25056d8b 335 if (b < 0) {
336 Dbprintf("Error %d during FpgaDownload", b);
337 break;
338 }
339 DownloadFPGA_byte(b);
15c4dc5a 340 }
25056d8b 341
15c4dc5a 342 // continue to clock FPGA until ready signal goes high
343 i=100000;
344 while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
345 HIGH(GPIO_FPGA_CCLK);
346 LOW(GPIO_FPGA_CCLK);
347 }
348 // crude error indicator, leave both red LEDs on and return
349 if (i==0){
350 LED_C_ON();
351 LED_D_ON();
352 return;
353 }
354 LED_D_OFF();
355}
356
e6153040 357
15c4dc5a 358/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence
359 * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01
360 * After that the format is 1 byte section type (ASCII character), 2 byte length
361 * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes
362 * length.
363 */
fb228974 364static int bitparse_find_section(int bitstream_version, char section_name, unsigned int *section_length, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
15c4dc5a 365{
15c4dc5a 366 int result = 0;
e6153040 367 #define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100 // maximum number of bytes to search for the requested section
368 uint16_t numbytes = 0;
369 while(numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {
fb228974 370 char current_name = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
e6153040 371 numbytes++;
15c4dc5a 372 unsigned int current_length = 0;
373 if(current_name < 'a' || current_name > 'e') {
374 /* Strange section name, abort */
375 break;
376 }
377 current_length = 0;
378 switch(current_name) {
379 case 'e':
380 /* Four byte length field */
fb228974 381 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 24;
382 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 16;
e6153040 383 numbytes += 2;
15c4dc5a 384 default: /* Fall through, two byte length field */
fb228974 385 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 8;
386 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 0;
e6153040 387 numbytes += 2;
15c4dc5a 388 }
e30c654b 389
15c4dc5a 390 if(current_name != 'e' && current_length > 255) {
391 /* Maybe a parse error */
392 break;
393 }
e30c654b 394
15c4dc5a 395 if(current_name == section_name) {
396 /* Found it */
15c4dc5a 397 *section_length = current_length;
398 result = 1;
399 break;
400 }
e30c654b 401
e6153040 402 for (uint16_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {
fb228974 403 get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
e6153040 404 numbytes++;
405 }
15c4dc5a 406 }
e30c654b 407
15c4dc5a 408 return result;
409}
410
e6153040 411
8e074056 412//----------------------------------------------------------------------------
413// Check which FPGA image is currently loaded (if any). If necessary
414// decompress and load the correct (HF or LF) image to the FPGA
415//----------------------------------------------------------------------------
7cc204bf 416void FpgaDownloadAndGo(int bitstream_version)
15c4dc5a 417{
add4d470 418 z_stream compressed_fpga_stream;
419 uint8_t output_buffer[OUTPUT_BUFFER_LEN];
e6153040 420
7cc204bf 421 // check whether or not the bitstream is already loaded
e6153040 422 if (downloaded_bitstream == bitstream_version)
7cc204bf 423 return;
424
8e074056 425 // make sure that we have enough memory to decompress
426 BigBuf_free();
427
add4d470 428 if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
7cc204bf 429 return;
e6153040 430 }
25056d8b 431
add4d470 432 unsigned int bitstream_length;
fb228974 433 if(bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
434 DownloadFPGA(bitstream_version, bitstream_length, &compressed_fpga_stream, output_buffer);
add4d470 435 downloaded_bitstream = bitstream_version;
15c4dc5a 436 }
25056d8b 437
438 inflateEnd(&compressed_fpga_stream);
e6153040 439}
15c4dc5a 440
7cc204bf 441
8e074056 442//-----------------------------------------------------------------------------
443// Gather version information from FPGA image. Needs to decompress the begin
444// of the respective (HF or LF) image.
445// Note: decompression makes use of (i.e. overwrites) BigBuf[]. It is therefore
446// advisable to call this only once and store the results for later use.
447//-----------------------------------------------------------------------------
e6153040 448void FpgaGatherVersion(int bitstream_version, char *dst, int len)
15c4dc5a 449{
15c4dc5a 450 unsigned int fpga_info_len;
e6153040 451 char tempstr[40];
add4d470 452 z_stream compressed_fpga_stream;
453 uint8_t output_buffer[OUTPUT_BUFFER_LEN];
e6153040 454
455 dst[0] = '\0';
25056d8b 456
8e074056 457 // ensure that we can allocate enough memory for decompression:
458 BigBuf_free();
459
add4d470 460 if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
e6153040 461 return;
e6153040 462 }
463
fb228974 464 if(bitparse_find_section(bitstream_version, 'a', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
e6153040 465 for (uint16_t i = 0; i < fpga_info_len; i++) {
fb228974 466 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
e6153040 467 if (i < sizeof(tempstr)) {
468 tempstr[i] = c;
469 }
15c4dc5a 470 }
e6153040 471 if (!memcmp("fpga_lf", tempstr, 7))
472 strncat(dst, "LF ", len-1);
473 else if (!memcmp("fpga_hf", tempstr, 7))
474 strncat(dst, "HF ", len-1);
475 }
476 strncat(dst, "FPGA image built", len-1);
fb228974 477 if(bitparse_find_section(bitstream_version, 'b', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
e6153040 478 strncat(dst, " for ", len-1);
479 for (uint16_t i = 0; i < fpga_info_len; i++) {
fb228974 480 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
e6153040 481 if (i < sizeof(tempstr)) {
482 tempstr[i] = c;
483 }
15c4dc5a 484 }
e6153040 485 strncat(dst, tempstr, len-1);
486 }
fb228974 487 if(bitparse_find_section(bitstream_version, 'c', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
e6153040 488 strncat(dst, " on ", len-1);
489 for (uint16_t i = 0; i < fpga_info_len; i++) {
fb228974 490 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
e6153040 491 if (i < sizeof(tempstr)) {
492 tempstr[i] = c;
493 }
15c4dc5a 494 }
e6153040 495 strncat(dst, tempstr, len-1);
496 }
fb228974 497 if(bitparse_find_section(bitstream_version, 'd', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
e6153040 498 strncat(dst, " at ", len-1);
499 for (uint16_t i = 0; i < fpga_info_len; i++) {
fb228974 500 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
e6153040 501 if (i < sizeof(tempstr)) {
502 tempstr[i] = c;
503 }
15c4dc5a 504 }
e6153040 505 strncat(dst, tempstr, len-1);
15c4dc5a 506 }
25056d8b 507
8e074056 508 strncat(dst, "\n", len-1);
25056d8b 509
8e074056 510 inflateEnd(&compressed_fpga_stream);
15c4dc5a 511}
512
add4d470 513
15c4dc5a 514//-----------------------------------------------------------------------------
515// Send a 16 bit command/data pair to the FPGA.
516// The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
517// where C is the 4 bit command and D is the 12 bit data
518//-----------------------------------------------------------------------------
f7e3ed82 519void FpgaSendCommand(uint16_t cmd, uint16_t v)
15c4dc5a 520{
521 SetupSpi(SPI_FPGA_MODE);
522 while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete
523 AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v; // send the data
524}
525//-----------------------------------------------------------------------------
526// Write the FPGA setup word (that determines what mode the logic is in, read
527// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
528// avoid changing this function's occurence everywhere in the source code.
529//-----------------------------------------------------------------------------
f7e3ed82 530void FpgaWriteConfWord(uint8_t v)
15c4dc5a 531{
532 FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
533}
534
535//-----------------------------------------------------------------------------
536// Set up the CMOS switches that mux the ADC: four switches, independently
537// closable, but should only close one at a time. Not an FPGA thing, but
538// the samples from the ADC always flow through the FPGA.
539//-----------------------------------------------------------------------------
f7e3ed82 540void SetAdcMuxFor(uint32_t whichGpio)
15c4dc5a 541{
542 AT91C_BASE_PIOA->PIO_OER =
543 GPIO_MUXSEL_HIPKD |
544 GPIO_MUXSEL_LOPKD |
545 GPIO_MUXSEL_LORAW |
546 GPIO_MUXSEL_HIRAW;
547
548 AT91C_BASE_PIOA->PIO_PER =
549 GPIO_MUXSEL_HIPKD |
550 GPIO_MUXSEL_LOPKD |
551 GPIO_MUXSEL_LORAW |
552 GPIO_MUXSEL_HIRAW;
553
554 LOW(GPIO_MUXSEL_HIPKD);
555 LOW(GPIO_MUXSEL_HIRAW);
556 LOW(GPIO_MUXSEL_LORAW);
557 LOW(GPIO_MUXSEL_LOPKD);
558
559 HIGH(whichGpio);
560}
e2012d1b
MHS
561
562void Fpga_print_status(void)
563{
564 Dbprintf("Fgpa");
565 if(downloaded_bitstream == FPGA_BITSTREAM_HF) Dbprintf(" mode.............HF");
566 else if(downloaded_bitstream == FPGA_BITSTREAM_LF) Dbprintf(" mode.............LF");
567 else Dbprintf(" mode.............%d", downloaded_bitstream);
568}
fdcfbdcc
RAB
569
570int FpgaGetCurrent() {
571 return downloaded_bitstream;
572}
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