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[proxmark3-svn] / armsrc / lfops.c
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9bea179a 1//-----------------------------------------------------------------------------\r
2// Miscellaneous routines for low frequency tag operations.\r
3// Tags supported here so far are Texas Instruments (TI), HID\r
4// Also routines for raw mode reading/simulating of LF waveform\r
5//\r
6//-----------------------------------------------------------------------------\r
7#include <proxmark3.h>\r
8#include "apps.h"\r
0fa9ca5b 9#include "hitag2.h"\r
7fe9b0b7 10#include "crc16.h"\r
9bea179a 11\r
12void AcquireRawAdcSamples125k(BOOL at134khz)\r
13{\r
0d974852 14 if (at134khz)\r
9bea179a 15 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 16 else\r
9bea179a 17 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 18\r
19 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 20\r
21 // Connect the A/D to the peak-detected low-frequency path.\r
22 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
23\r
24 // Give it a bit of time for the resonant antenna to settle.\r
25 SpinDelay(50);\r
26\r
27 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
28 FpgaSetupSsc();\r
29\r
30 // Now call the acquisition routine\r
0d974852 31 DoAcquisition125k();\r
9bea179a 32}\r
33\r
34// split into two routines so we can avoid timing issues after sending commands //\r
0d974852 35void DoAcquisition125k(void)\r
9bea179a 36{\r
37 BYTE *dest = (BYTE *)BigBuf;\r
38 int n = sizeof(BigBuf);\r
39 int i;\r
6f5cb60c 40 \r
0d974852 41 memset(dest, 0, n);\r
9bea179a 42 i = 0;\r
43 for(;;) {\r
6f5cb60c 44 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {\r
6949aca9 45 AT91C_BASE_SSC->SSC_THR = 0x43;\r
9bea179a 46 LED_D_ON();\r
47 }\r
0d974852 48 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r
6949aca9 49 dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
9bea179a 50 i++;\r
51 LED_D_OFF();\r
6f5cb60c 52 if (i >= n) break;\r
9bea179a 53 }\r
54 }\r
1e1b3030 55 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",\r
56 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);\r
9bea179a 57}\r
58\r
0d974852 59void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, BYTE *command)\r
9bea179a 60{\r
61 BOOL at134khz;\r
62\r
0fa9ca5b 63 /* Make sure the tag is reset */\r
64 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
65 SpinDelay(2500);\r
66 \r
9bea179a 67 // see if 'h' was specified\r
0d974852 68 if (command[strlen((char *) command) - 1] == 'h')\r
69 at134khz = TRUE;\r
9bea179a 70 else\r
0d974852 71 at134khz = FALSE;\r
9bea179a 72\r
0d974852 73 if (at134khz)\r
9bea179a 74 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 75 else\r
9bea179a 76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 77\r
78 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 79\r
80 // Give it a bit of time for the resonant antenna to settle.\r
81 SpinDelay(50);\r
0fa9ca5b 82 // And a little more time for the tag to fully power up\r
83 SpinDelay(2000);\r
9bea179a 84\r
85 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
86 FpgaSetupSsc();\r
87\r
88 // now modulate the reader field\r
0d974852 89 while(*command != '\0' && *command != ' ') {\r
9bea179a 90 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
91 LED_D_OFF();\r
92 SpinDelayUs(delay_off);\r
0d974852 93 if (at134khz)\r
9bea179a 94 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 95 else\r
9bea179a 96 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 97\r
98 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 99 LED_D_ON();\r
0d974852 100 if(*(command++) == '0')\r
9bea179a 101 SpinDelayUs(period_0);\r
0d974852 102 else\r
9bea179a 103 SpinDelayUs(period_1);\r
0d974852 104 }\r
9bea179a 105 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
106 LED_D_OFF();\r
107 SpinDelayUs(delay_off);\r
0d974852 108 if (at134khz)\r
9bea179a 109 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 110 else\r
9bea179a 111 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 112\r
113 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 114\r
115 // now do the read\r
0d974852 116 DoAcquisition125k();\r
9bea179a 117}\r
118\r
7381e8f2 119/* blank r/w tag data stream\r
120...0000000000000000 01111111\r
1211010101010101010101010101010101010101010101010101010101010101010\r
1220011010010100001\r
12301111111\r
124101010101010101[0]000...\r
125\r
126[5555fe852c5555555555555555fe0000]\r
127*/\r
0d974852 128void ReadTItag(void)\r
7381e8f2 129{\r
130 // some hardcoded initial params\r
131 // when we read a TI tag we sample the zerocross line at 2Mhz\r
132 // TI tags modulate a 1 as 16 cycles of 123.2Khz\r
133 // TI tags modulate a 0 as 16 cycles of 134.2Khz\r
134 #define FSAMPLE 2000000\r
135 #define FREQLO 123200\r
136 #define FREQHI 134200\r
137\r
138 signed char *dest = (signed char *)BigBuf;\r
139 int n = sizeof(BigBuf);\r
140// int *dest = GraphBuffer;\r
141// int n = GraphTraceLen;\r
142\r
143 // 128 bit shift register [shift3:shift2:shift1:shift0]\r
144 DWORD shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;\r
145\r
146 int i, cycles=0, samples=0;\r
147 // how many sample points fit in 16 cycles of each frequency\r
148 DWORD sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;\r
149 // when to tell if we're close enough to one freq or another\r
150 DWORD threshold = (sampleslo - sampleshi + 1)>>1;\r
151\r
152 // TI tags charge at 134.2Khz\r
153 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
154\r
155 // Place FPGA in passthrough mode, in this mode the CROSS_LO line\r
156 // connects to SSP_DIN and the SSP_DOUT logic level controls\r
157 // whether we're modulating the antenna (high)\r
158 // or listening to the antenna (low)\r
159 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r
160\r
161 // get TI tag data into the buffer\r
162 AcquireTiType();\r
163\r
164 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
165\r
166 for (i=0; i<n-1; i++) {\r
167 // count cycles by looking for lo to hi zero crossings\r
168 if ( (dest[i]<0) && (dest[i+1]>0) ) {\r
169 cycles++;\r
170 // after 16 cycles, measure the frequency\r
171 if (cycles>15) {\r
172 cycles=0;\r
173 samples=i-samples; // number of samples in these 16 cycles\r
174\r
175 // TI bits are coming to us lsb first so shift them\r
176 // right through our 128 bit right shift register\r
177 shift0 = (shift0>>1) | (shift1 << 31);\r
178 shift1 = (shift1>>1) | (shift2 << 31);\r
179 shift2 = (shift2>>1) | (shift3 << 31);\r
180 shift3 >>= 1;\r
181\r
182 // check if the cycles fall close to the number\r
183 // expected for either the low or high frequency\r
184 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {\r
185 // low frequency represents a 1\r
186 shift3 |= (1<<31);\r
187 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {\r
188 // high frequency represents a 0\r
189 } else {\r
190 // probably detected a gay waveform or noise\r
191 // use this as gaydar or discard shift register and start again\r
192 shift3 = shift2 = shift1 = shift0 = 0;\r
193 }\r
194 samples = i;\r
195\r
196 // for each bit we receive, test if we've detected a valid tag\r
197\r
198 // if we see 17 zeroes followed by 6 ones, we might have a tag\r
199 // remember the bits are backwards\r
200 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {\r
201 // if start and end bytes match, we have a tag so break out of the loop\r
202 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {\r
203 cycles = 0xF0B; //use this as a flag (ugly but whatever)\r
204 break;\r
205 }\r
206 }\r
207 }\r
208 }\r
209 }\r
210\r
211 // if flag is set we have a tag\r
212 if (cycles!=0xF0B) {\r
213 DbpString("Info: No valid tag detected.");\r
214 } else {\r
215 // put 64 bit data into shift1 and shift0\r
216 shift0 = (shift0>>24) | (shift1 << 8);\r
217 shift1 = (shift1>>24) | (shift2 << 8);\r
218\r
219 // align 16 bit crc into lower half of shift2\r
220 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;\r
221\r
222 // if r/w tag, check ident match\r
223 if ( shift3&(1<<15) ) {\r
224 DbpString("Info: TI tag is rewriteable");\r
225 // only 15 bits compare, last bit of ident is not valid\r
226 if ( ((shift3>>16)^shift0)&0x7fff ) {\r
227 DbpString("Error: Ident mismatch!");\r
228 } else {\r
229 DbpString("Info: TI tag ident is valid");\r
230 }\r
231 } else {\r
232 DbpString("Info: TI tag is readonly");\r
233 }\r
234\r
235 // WARNING the order of the bytes in which we calc crc below needs checking\r
236 // i'm 99% sure the crc algorithm is correct, but it may need to eat the\r
237 // bytes in reverse or something\r
238 // calculate CRC\r
239 DWORD crc=0;\r
240\r
241 crc = update_crc16(crc, (shift0)&0xff);\r
242 crc = update_crc16(crc, (shift0>>8)&0xff);\r
243 crc = update_crc16(crc, (shift0>>16)&0xff);\r
244 crc = update_crc16(crc, (shift0>>24)&0xff);\r
245 crc = update_crc16(crc, (shift1)&0xff);\r
246 crc = update_crc16(crc, (shift1>>8)&0xff);\r
247 crc = update_crc16(crc, (shift1>>16)&0xff);\r
248 crc = update_crc16(crc, (shift1>>24)&0xff);\r
249\r
1e1b3030 250 Dbprintf("Info: Tag data: %x%08x, crc=%x",\r
6f5cb60c 251 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);\r
7381e8f2 252 if (crc != (shift2&0xffff)) {\r
a9bc033b 253 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);\r
7381e8f2 254 } else {\r
255 DbpString("Info: CRC is good");\r
256 }\r
257 }\r
258}\r
259\r
260void WriteTIbyte(BYTE b)\r
261{\r
262 int i = 0;\r
263\r
264 // modulate 8 bits out to the antenna\r
265 for (i=0; i<8; i++)\r
266 {\r
267 if (b&(1<<i)) {\r
268 // stop modulating antenna\r
6949aca9 269 LOW(GPIO_SSC_DOUT);\r
7381e8f2 270 SpinDelayUs(1000);\r
271 // modulate antenna\r
6949aca9 272 HIGH(GPIO_SSC_DOUT);\r
7381e8f2 273 SpinDelayUs(1000);\r
274 } else {\r
275 // stop modulating antenna\r
6949aca9 276 LOW(GPIO_SSC_DOUT);\r
7381e8f2 277 SpinDelayUs(300);\r
278 // modulate antenna\r
6949aca9 279 HIGH(GPIO_SSC_DOUT);\r
7381e8f2 280 SpinDelayUs(1700);\r
281 }\r
282 }\r
283}\r
284\r
9bea179a 285void AcquireTiType(void)\r
286{\r
7381e8f2 287 int i, j, n;\r
9bea179a 288 // tag transmission is <20ms, sampling at 2M gives us 40K samples max\r
289 // each sample is 1 bit stuffed into a DWORD so we need 1250 DWORDS\r
7381e8f2 290 #define TIBUFLEN 1250\r
9bea179a 291\r
292 // clear buffer\r
293 memset(BigBuf,0,sizeof(BigBuf));\r
294\r
295 // Set up the synchronous serial port\r
6949aca9 296 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;\r
297 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;\r
9bea179a 298\r
299 // steal this pin from the SSP and use it to control the modulation\r
6949aca9 300 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r
0d974852 301 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
9bea179a 302\r
6949aca9 303 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;\r
304 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;\r
9bea179a 305\r
6949aca9 306 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long\r
307 // 48/2 = 24 MHz clock must be divided by 12\r
308 AT91C_BASE_SSC->SSC_CMR = 12;\r
9bea179a 309\r
6949aca9 310 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);\r
311 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;\r
312 AT91C_BASE_SSC->SSC_TCMR = 0;\r
313 AT91C_BASE_SSC->SSC_TFMR = 0;\r
9bea179a 314\r
315 LED_D_ON();\r
316\r
317 // modulate antenna\r
6949aca9 318 HIGH(GPIO_SSC_DOUT);\r
9bea179a 319\r
320 // Charge TI tag for 50ms.\r
321 SpinDelay(50);\r
322\r
323 // stop modulating antenna and listen\r
6949aca9 324 LOW(GPIO_SSC_DOUT);\r
9bea179a 325\r
326 LED_D_OFF();\r
327\r
328 i = 0;\r
329 for(;;) {\r
6949aca9 330 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r
331 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer\r
332 i++; if(i >= TIBUFLEN) break;\r
333 }\r
334 WDT_HIT();\r
9bea179a 335 }\r
336\r
337 // return stolen pin to SSP\r
6949aca9 338 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;\r
339 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;\r
9bea179a 340\r
7381e8f2 341 char *dest = (char *)BigBuf;\r
342 n = TIBUFLEN*32;\r
343 // unpack buffer\r
344 for (i=TIBUFLEN-1; i>=0; i--) {\r
7381e8f2 345 for (j=0; j<32; j++) {\r
346 if(BigBuf[i] & (1 << j)) {\r
347 dest[--n] = 1;\r
348 } else {\r
349 dest[--n] = -1;\r
350 }\r
9bea179a 351 }\r
352 }\r
353}\r
354\r
9bea179a 355// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc\r
356// if crc provided, it will be written with the data verbatim (even if bogus)\r
357// if not provided a valid crc will be computed from the data and written.\r
358void WriteTItag(DWORD idhi, DWORD idlo, WORD crc)\r
359{\r
9bea179a 360 if(crc == 0) {\r
361 crc = update_crc16(crc, (idlo)&0xff);\r
362 crc = update_crc16(crc, (idlo>>8)&0xff);\r
363 crc = update_crc16(crc, (idlo>>16)&0xff);\r
364 crc = update_crc16(crc, (idlo>>24)&0xff);\r
365 crc = update_crc16(crc, (idhi)&0xff);\r
366 crc = update_crc16(crc, (idhi>>8)&0xff);\r
367 crc = update_crc16(crc, (idhi>>16)&0xff);\r
368 crc = update_crc16(crc, (idhi>>24)&0xff);\r
369 }\r
1e1b3030 370 Dbprintf("Writing to tag: %x%08x, crc=%x",\r
6f5cb60c 371 (unsigned int) idhi, (unsigned int) idlo, crc);\r
9bea179a 372\r
373 // TI tags charge at 134.2Khz\r
374 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
375 // Place FPGA in passthrough mode, in this mode the CROSS_LO line\r
376 // connects to SSP_DIN and the SSP_DOUT logic level controls\r
377 // whether we're modulating the antenna (high)\r
378 // or listening to the antenna (low)\r
379 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r
380 LED_A_ON();\r
381\r
382 // steal this pin from the SSP and use it to control the modulation\r
6949aca9 383 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r
6f5cb60c 384 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
9bea179a 385\r
386 // writing algorithm:\r
387 // a high bit consists of a field off for 1ms and field on for 1ms\r
388 // a low bit consists of a field off for 0.3ms and field on for 1.7ms\r
389 // initiate a charge time of 50ms (field on) then immediately start writing bits\r
390 // start by writing 0xBB (keyword) and 0xEB (password)\r
391 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)\r
392 // finally end with 0x0300 (write frame)\r
393 // all data is sent lsb firts\r
394 // finish with 15ms programming time\r
395\r
396 // modulate antenna\r
6949aca9 397 HIGH(GPIO_SSC_DOUT);\r
9bea179a 398 SpinDelay(50); // charge time\r
399\r
400 WriteTIbyte(0xbb); // keyword\r
401 WriteTIbyte(0xeb); // password\r
402 WriteTIbyte( (idlo )&0xff );\r
403 WriteTIbyte( (idlo>>8 )&0xff );\r
404 WriteTIbyte( (idlo>>16)&0xff );\r
405 WriteTIbyte( (idlo>>24)&0xff );\r
406 WriteTIbyte( (idhi )&0xff );\r
407 WriteTIbyte( (idhi>>8 )&0xff );\r
408 WriteTIbyte( (idhi>>16)&0xff );\r
409 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo\r
410 WriteTIbyte( (crc )&0xff ); // crc lo\r
411 WriteTIbyte( (crc>>8 )&0xff ); // crc hi\r
412 WriteTIbyte(0x00); // write frame lo\r
413 WriteTIbyte(0x03); // write frame hi\r
6949aca9 414 HIGH(GPIO_SSC_DOUT);\r
9bea179a 415 SpinDelay(50); // programming time\r
416\r
417 LED_A_OFF();\r
418\r
419 // get TI tag data into the buffer\r
420 AcquireTiType();\r
421\r
422 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
7381e8f2 423 DbpString("Now use tiread to check");\r
9bea179a 424}\r
425\r
13a79da4 426void SimulateTagLowFrequency(int period, int gap, int ledcontrol)\r
9bea179a 427{\r
428 int i;\r
429 BYTE *tab = (BYTE *)BigBuf;\r
430\r
431 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
432\r
6949aca9 433 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;\r
9bea179a 434\r
6949aca9 435 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
436 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;\r
9bea179a 437\r
438#define SHORT_COIL() LOW(GPIO_SSC_DOUT)\r
6949aca9 439#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)\r
9bea179a 440\r
441 i = 0;\r
442 for(;;) {\r
6949aca9 443 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {\r
9bea179a 444 if(BUTTON_PRESS()) {\r
445 DbpString("Stopped");\r
446 return;\r
447 }\r
448 WDT_HIT();\r
449 }\r
450\r
451 if (ledcontrol)\r
452 LED_D_ON();\r
453\r
454 if(tab[i])\r
455 OPEN_COIL();\r
456 else\r
457 SHORT_COIL();\r
458\r
459 if (ledcontrol)\r
460 LED_D_OFF();\r
461\r
6949aca9 462 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {\r
9bea179a 463 if(BUTTON_PRESS()) {\r
464 DbpString("Stopped");\r
465 return;\r
466 }\r
467 WDT_HIT();\r
468 }\r
469\r
470 i++;\r
13a79da4 471 if(i == period) {\r
472 i = 0;\r
473 if (gap) { \r
474 SHORT_COIL();\r
475 SpinDelayUs(gap);\r
476 }\r
477 }\r
9bea179a 478 }\r
479}\r
480\r
0fa9ca5b 481/* Provides a framework for bidirectional LF tag communication\r
482 * Encoding is currently Hitag2, but the general idea can probably\r
483 * be transferred to other encodings.\r
484 * \r
485 * The new FPGA code will, for the LF simulator mode, give on SSC_FRAME\r
486 * (PA15) a thresholded version of the signal from the ADC. Setting the\r
487 * ADC path to the low frequency peak detection signal, will enable a\r
488 * somewhat reasonable receiver for modulation on the carrier signal\r
489 * that is generated by the reader. The signal is low when the reader\r
490 * field is switched off, and high when the reader field is active. Due\r
491 * to the way that the signal looks like, mostly only the rising edge is\r
492 * useful, your mileage may vary.\r
493 * \r
494 * Neat perk: PA15 can not only be used as a bit-banging GPIO, but is also\r
495 * TIOA1, which can be used as the capture input for timer 1. This should\r
496 * make it possible to measure the exact edge-to-edge time, without processor\r
497 * intervention.\r
498 * \r
499 * Arguments: divisor is the divisor to be sent to the FPGA (e.g. 95 for 125kHz)\r
500 * t0 is the carrier frequency cycle duration in terms of MCK (384 for 125kHz)\r
501 * \r
502 * The following defines are in carrier periods: \r
503 */\r
504#define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */ \r
505#define HITAG_T_1_MIN 24 /* T[1] should be 26..30 */\r
506#define HITAG_T_EOF 40 /* T_EOF should be > 36 */\r
507#define HITAG_T_WRESP 208 /* T_wresp should be 204..212 */\r
508\r
509static void hitag_handle_frame(int t0, int frame_len, char *frame);\r
510//#define DEBUG_RA_VALUES 1\r
511#define DEBUG_FRAME_CONTENTS 1\r
512void SimulateTagLowFrequencyBidir(int divisor, int t0)\r
513{\r
514#if DEBUG_RA_VALUES || DEBUG_FRAME_CONTENTS\r
515 int i = 0;\r
516#endif\r
517 char frame[10];\r
518 int frame_pos=0;\r
519 \r
520 DbpString("Starting Hitag2 emulator, press button to end");\r
521 hitag2_init();\r
522 \r
523 /* Set up simulator mode, frequency divisor which will drive the FPGA\r
6949aca9 524 * and analog mux selection.\r
0fa9ca5b 525 */\r
526 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
527 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);\r
528 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
529 RELAY_OFF();\r
530 \r
531 /* Set up Timer 1:\r
532 * Capture mode, timer source MCK/2 (TIMER_CLOCK1), TIOA is external trigger,\r
533 * external trigger rising edge, load RA on rising edge of TIOA, load RB on rising\r
6949aca9 534 * edge of TIOA. Assign PA15 to TIOA1 (peripheral B)\r
0fa9ca5b 535 */\r
536 \r
6949aca9 537 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);\r
538 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;\r
539 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r
540 AT91C_BASE_TC1->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 |\r
541 AT91C_TC_ETRGEDG_RISING |\r
542 AT91C_TC_ABETRG |\r
543 AT91C_TC_LDRA_RISING |\r
544 AT91C_TC_LDRB_RISING;\r
545 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN |\r
546 AT91C_TC_SWTRG;\r
0fa9ca5b 547 \r
548 /* calculate the new value for the carrier period in terms of TC1 values */\r
549 t0 = t0/2;\r
550 \r
551 int overflow = 0;\r
552 while(!BUTTON_PRESS()) {\r
553 WDT_HIT();\r
6949aca9 554 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {\r
555 int ra = AT91C_BASE_TC1->TC_RA;\r
0fa9ca5b 556 if((ra > t0*HITAG_T_EOF) | overflow) ra = t0*HITAG_T_EOF+1;\r
557#if DEBUG_RA_VALUES\r
558 if(ra > 255 || overflow) ra = 255;\r
559 ((char*)BigBuf)[i] = ra;\r
560 i = (i+1) % 8000;\r
561#endif\r
562 \r
563 if(overflow || (ra > t0*HITAG_T_EOF) || (ra < t0*HITAG_T_0_MIN)) {\r
564 /* Ignore */\r
565 } else if(ra >= t0*HITAG_T_1_MIN ) {\r
566 /* '1' bit */\r
567 if(frame_pos < 8*sizeof(frame)) {\r
568 frame[frame_pos / 8] |= 1<<( 7-(frame_pos%8) );\r
569 frame_pos++;\r
570 }\r
571 } else if(ra >= t0*HITAG_T_0_MIN) {\r
572 /* '0' bit */\r
573 if(frame_pos < 8*sizeof(frame)) {\r
574 frame[frame_pos / 8] |= 0<<( 7-(frame_pos%8) );\r
575 frame_pos++;\r
576 }\r
577 }\r
578 \r
579 overflow = 0;\r
580 LED_D_ON();\r
581 } else {\r
6949aca9 582 if(AT91C_BASE_TC1->TC_CV > t0*HITAG_T_EOF) {\r
0fa9ca5b 583 /* Minor nuisance: In Capture mode, the timer can not be\r
584 * stopped by a Compare C. There's no way to stop the clock\r
585 * in software, so we'll just have to note the fact that an\r
586 * overflow happened and the next loaded timer value might\r
587 * have wrapped. Also, this marks the end of frame, and the\r
588 * still running counter can be used to determine the correct\r
6949aca9 589 * time for the start of the reply.\r
0fa9ca5b 590 */ \r
591 overflow = 1;\r
592 \r
593 if(frame_pos > 0) {\r
594 /* Have a frame, do something with it */\r
595#if DEBUG_FRAME_CONTENTS\r
596 ((char*)BigBuf)[i++] = frame_pos;\r
597 memcpy( ((char*)BigBuf)+i, frame, 7);\r
598 i+=7;\r
599 i = i % sizeof(BigBuf);\r
600#endif\r
601 hitag_handle_frame(t0, frame_pos, frame);\r
602 memset(frame, 0, sizeof(frame));\r
603 }\r
604 frame_pos = 0;\r
605\r
606 }\r
607 LED_D_OFF();\r
608 }\r
609 }\r
610 DbpString("All done");\r
611}\r
612\r
613static void hitag_send_bit(int t0, int bit) {\r
614 if(bit == 1) {\r
615 /* Manchester: Loaded, then unloaded */\r
616 LED_A_ON();\r
617 SHORT_COIL();\r
6949aca9 618 while(AT91C_BASE_TC1->TC_CV < t0*15);\r
0fa9ca5b 619 OPEN_COIL();\r
6949aca9 620 while(AT91C_BASE_TC1->TC_CV < t0*31);\r
0fa9ca5b 621 LED_A_OFF();\r
622 } else if(bit == 0) {\r
623 /* Manchester: Unloaded, then loaded */\r
624 LED_B_ON();\r
625 OPEN_COIL();\r
6949aca9 626 while(AT91C_BASE_TC1->TC_CV < t0*15);\r
0fa9ca5b 627 SHORT_COIL();\r
6949aca9 628 while(AT91C_BASE_TC1->TC_CV < t0*31);\r
0fa9ca5b 629 LED_B_OFF();\r
630 }\r
6949aca9 631 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset clock for the next bit */\r
0fa9ca5b 632 \r
633}\r
634static void hitag_send_frame(int t0, int frame_len, const char const * frame, int fdt)\r
635{\r
636 OPEN_COIL();\r
6949aca9 637 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
0fa9ca5b 638 \r
639 /* Wait for HITAG_T_WRESP carrier periods after the last reader bit,\r
640 * not that since the clock counts since the rising edge, but T_wresp is\r
641 * with respect to the falling edge, we need to wait actually (T_wresp - T_g)\r
6949aca9 642 * periods. The gap time T_g varies (4..10).\r
0fa9ca5b 643 */\r
6949aca9 644 while(AT91C_BASE_TC1->TC_CV < t0*(fdt-8));\r
0fa9ca5b 645\r
6949aca9 646 int saved_cmr = AT91C_BASE_TC1->TC_CMR;\r
647 AT91C_BASE_TC1->TC_CMR &= ~AT91C_TC_ETRGEDG; /* Disable external trigger for the clock */\r
648 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset the clock and use it for response timing */\r
0fa9ca5b 649 \r
650 int i;\r
651 for(i=0; i<5; i++)\r
652 hitag_send_bit(t0, 1); /* Start of frame */\r
653 \r
654 for(i=0; i<frame_len; i++) {\r
655 hitag_send_bit(t0, !!(frame[i/ 8] & (1<<( 7-(i%8) ))) );\r
656 }\r
657 \r
658 OPEN_COIL();\r
6949aca9 659 AT91C_BASE_TC1->TC_CMR = saved_cmr;\r
0fa9ca5b 660}\r
661\r
662/* Callback structure to cleanly separate tag emulation code from the radio layer. */\r
663static int hitag_cb(const char* response_data, const int response_length, const int fdt, void *cb_cookie)\r
664{\r
665 hitag_send_frame(*(int*)cb_cookie, response_length, response_data, fdt);\r
666 return 0;\r
667}\r
668/* Frame length in bits, frame contents in MSBit first format */\r
669static void hitag_handle_frame(int t0, int frame_len, char *frame)\r
670{\r
671 hitag2_handle_command(frame, frame_len, hitag_cb, &t0);\r
672}\r
673\r
9bea179a 674// compose fc/8 fc/10 waveform\r
675static void fc(int c, int *n) {\r
676 BYTE *dest = (BYTE *)BigBuf;\r
677 int idx;\r
678\r
679 // for when we want an fc8 pattern every 4 logical bits\r
680 if(c==0) {\r
681 dest[((*n)++)]=1;\r
682 dest[((*n)++)]=1;\r
683 dest[((*n)++)]=0;\r
684 dest[((*n)++)]=0;\r
685 dest[((*n)++)]=0;\r
686 dest[((*n)++)]=0;\r
687 dest[((*n)++)]=0;\r
688 dest[((*n)++)]=0;\r
689 }\r
690 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples\r
691 if(c==8) {\r
692 for (idx=0; idx<6; idx++) {\r
693 dest[((*n)++)]=1;\r
694 dest[((*n)++)]=1;\r
695 dest[((*n)++)]=0;\r
696 dest[((*n)++)]=0;\r
697 dest[((*n)++)]=0;\r
698 dest[((*n)++)]=0;\r
699 dest[((*n)++)]=0;\r
700 dest[((*n)++)]=0;\r
701 }\r
702 }\r
703\r
704 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples\r
705 if(c==10) {\r
706 for (idx=0; idx<5; idx++) {\r
707 dest[((*n)++)]=1;\r
708 dest[((*n)++)]=1;\r
709 dest[((*n)++)]=1;\r
710 dest[((*n)++)]=0;\r
711 dest[((*n)++)]=0;\r
712 dest[((*n)++)]=0;\r
713 dest[((*n)++)]=0;\r
714 dest[((*n)++)]=0;\r
715 dest[((*n)++)]=0;\r
716 dest[((*n)++)]=0;\r
717 }\r
718 }\r
719}\r
720\r
721// prepare a waveform pattern in the buffer based on the ID given then\r
722// simulate a HID tag until the button is pressed\r
723void CmdHIDsimTAG(int hi, int lo, int ledcontrol)\r
724{\r
725 int n=0, i=0;\r
726 /*\r
727 HID tag bitstream format\r
728 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits\r
729 A 1 bit is represented as 6 fc8 and 5 fc10 patterns\r
730 A 0 bit is represented as 5 fc10 and 6 fc8 patterns\r
731 A fc8 is inserted before every 4 bits\r
732 A special start of frame pattern is used consisting a0b0 where a and b are neither 0\r
733 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)\r
734 */\r
735\r
736 if (hi>0xFFF) {\r
737 DbpString("Tags can only have 44 bits.");\r
738 return;\r
739 }\r
740 fc(0,&n);\r
741 // special start of frame marker containing invalid bit sequences\r
742 fc(8, &n); fc(8, &n); // invalid\r
743 fc(8, &n); fc(10, &n); // logical 0\r
744 fc(10, &n); fc(10, &n); // invalid\r
745 fc(8, &n); fc(10, &n); // logical 0\r
746\r
747 WDT_HIT();\r
748 // manchester encode bits 43 to 32\r
749 for (i=11; i>=0; i--) {\r
750 if ((i%4)==3) fc(0,&n);\r
751 if ((hi>>i)&1) {\r
752 fc(10, &n); fc(8, &n); // low-high transition\r
753 } else {\r
754 fc(8, &n); fc(10, &n); // high-low transition\r
755 }\r
756 }\r
757\r
758 WDT_HIT();\r
759 // manchester encode bits 31 to 0\r
760 for (i=31; i>=0; i--) {\r
761 if ((i%4)==3) fc(0,&n);\r
762 if ((lo>>i)&1) {\r
763 fc(10, &n); fc(8, &n); // low-high transition\r
764 } else {\r
765 fc(8, &n); fc(10, &n); // high-low transition\r
766 }\r
767 }\r
768\r
769 if (ledcontrol)\r
770 LED_A_ON();\r
13a79da4 771 SimulateTagLowFrequency(n, 0, ledcontrol);\r
9bea179a 772\r
773 if (ledcontrol)\r
774 LED_A_OFF();\r
775}\r
776\r
777\r
778// loop to capture raw HID waveform then FSK demodulate the TAG ID from it\r
779void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)\r
780{\r
781 BYTE *dest = (BYTE *)BigBuf;\r
782 int m=0, n=0, i=0, idx=0, found=0, lastval=0;\r
783 DWORD hi=0, lo=0;\r
784\r
785 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
786 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
787\r
788 // Connect the A/D to the peak-detected low-frequency path.\r
789 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
790\r
791 // Give it a bit of time for the resonant antenna to settle.\r
792 SpinDelay(50);\r
793\r
794 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
795 FpgaSetupSsc();\r
796\r
797 for(;;) {\r
798 WDT_HIT();\r
799 if (ledcontrol)\r
800 LED_A_ON();\r
801 if(BUTTON_PRESS()) {\r
802 DbpString("Stopped");\r
803 if (ledcontrol)\r
804 LED_A_OFF();\r
805 return;\r
806 }\r
807\r
808 i = 0;\r
809 m = sizeof(BigBuf);\r
810 memset(dest,128,m);\r
811 for(;;) {\r
6949aca9 812 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
813 AT91C_BASE_SSC->SSC_THR = 0x43;\r
9bea179a 814 if (ledcontrol)\r
815 LED_D_ON();\r
816 }\r
6949aca9 817 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
818 dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
9bea179a 819 // we don't care about actual value, only if it's more or less than a\r
820 // threshold essentially we capture zero crossings for later analysis\r
821 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;\r
822 i++;\r
823 if (ledcontrol)\r
824 LED_D_OFF();\r
825 if(i >= m) {\r
826 break;\r
827 }\r
828 }\r
829 }\r
830\r
831 // FSK demodulator\r
832\r
833 // sync to first lo-hi transition\r
834 for( idx=1; idx<m; idx++) {\r
835 if (dest[idx-1]<dest[idx])\r
836 lastval=idx;\r
837 break;\r
838 }\r
839 WDT_HIT();\r
840\r
841 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)\r
842 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere\r
843 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10\r
844 for( i=0; idx<m; idx++) {\r
845 if (dest[idx-1]<dest[idx]) {\r
846 dest[i]=idx-lastval;\r
847 if (dest[i] <= 8) {\r
848 dest[i]=1;\r
849 } else {\r
850 dest[i]=0;\r
851 }\r
852\r
853 lastval=idx;\r
854 i++;\r
855 }\r
856 }\r
857 m=i;\r
858 WDT_HIT();\r
859\r
860 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns\r
861 lastval=dest[0];\r
862 idx=0;\r
863 i=0;\r
864 n=0;\r
865 for( idx=0; idx<m; idx++) {\r
866 if (dest[idx]==lastval) {\r
867 n++;\r
868 } else {\r
869 // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,\r
870 // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets\r
871 // swallowed up by rounding\r
872 // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding\r
873 // special start of frame markers use invalid manchester states (no transitions) by using sequences\r
874 // like 111000\r
875 if (dest[idx-1]) {\r
876 n=(n+1)/6; // fc/8 in sets of 6\r
877 } else {\r
878 n=(n+1)/5; // fc/10 in sets of 5\r
879 }\r
880 switch (n) { // stuff appropriate bits in buffer\r
881 case 0:\r
882 case 1: // one bit\r
883 dest[i++]=dest[idx-1];\r
884 break;\r
885 case 2: // two bits\r
886 dest[i++]=dest[idx-1];\r
887 dest[i++]=dest[idx-1];\r
888 break;\r
889 case 3: // 3 bit start of frame markers\r
890 dest[i++]=dest[idx-1];\r
891 dest[i++]=dest[idx-1];\r
892 dest[i++]=dest[idx-1];\r
893 break;\r
894 // When a logic 0 is immediately followed by the start of the next transmisson\r
895 // (special pattern) a pattern of 4 bit duration lengths is created.\r
896 case 4:\r
897 dest[i++]=dest[idx-1];\r
898 dest[i++]=dest[idx-1];\r
899 dest[i++]=dest[idx-1];\r
900 dest[i++]=dest[idx-1];\r
901 break;\r
902 default: // this shouldn't happen, don't stuff any bits\r
903 break;\r
904 }\r
905 n=0;\r
906 lastval=dest[idx];\r
907 }\r
908 }\r
909 m=i;\r
910 WDT_HIT();\r
911\r
912 // final loop, go over previously decoded manchester data and decode into usable tag ID\r
913 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0\r
914 for( idx=0; idx<m-6; idx++) {\r
915 // search for a start of frame marker\r
916 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )\r
917 {\r
918 found=1;\r
919 idx+=6;\r
920 if (found && (hi|lo)) {\r
1e1b3030 921 Dbprintf("TAG ID: %x%08x (%d)",\r
6f5cb60c 922 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r
9bea179a 923 /* if we're only looking for one tag */\r
924 if (findone)\r
925 {\r
926 *high = hi;\r
927 *low = lo;\r
928 return;\r
929 }\r
930 hi=0;\r
931 lo=0;\r
932 found=0;\r
933 }\r
934 }\r
935 if (found) {\r
936 if (dest[idx] && (!dest[idx+1]) ) {\r
937 hi=(hi<<1)|(lo>>31);\r
938 lo=(lo<<1)|0;\r
939 } else if ( (!dest[idx]) && dest[idx+1]) {\r
940 hi=(hi<<1)|(lo>>31);\r
941 lo=(lo<<1)|1;\r
942 } else {\r
943 found=0;\r
944 hi=0;\r
945 lo=0;\r
946 }\r
947 idx++;\r
948 }\r
949 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )\r
950 {\r
951 found=1;\r
952 idx+=6;\r
953 if (found && (hi|lo)) {\r
1e1b3030 954 Dbprintf("TAG ID: %x%08x (%d)",\r
6f5cb60c 955 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r
9bea179a 956 /* if we're only looking for one tag */\r
957 if (findone)\r
958 {\r
959 *high = hi;\r
960 *low = lo;\r
961 return;\r
962 }\r
963 hi=0;\r
964 lo=0;\r
965 found=0;\r
966 }\r
967 }\r
968 }\r
969 WDT_HIT();\r
970 }\r
971}\r
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