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cee5a30d 1//-----------------------------------------------------------------------------
2// Gerhard de Koning Gans - May 2008
3// Hagen Fritsch - June 2010
4// Gerhard de Koning Gans - May 2011
1e262141 5// Gerhard de Koning Gans - June 2012 - Added iClass card and reader emulation
cee5a30d 6//
7// This code is licensed to you under the terms of the GNU GPL, version 2 or,
8// at your option, any later version. See the LICENSE.txt file for the text of
9// the license.
10//-----------------------------------------------------------------------------
11// Routines to support iClass.
12//-----------------------------------------------------------------------------
13// Based on ISO14443a implementation. Still in experimental phase.
14// Contribution made during a security research at Radboud University Nijmegen
15//
16// Please feel free to contribute and extend iClass support!!
17//-----------------------------------------------------------------------------
18//
cee5a30d 19// FIX:
20// ====
21// We still have sometimes a demodulation error when snooping iClass communication.
22// The resulting trace of a read-block-03 command may look something like this:
23//
24// + 22279: : 0c 03 e8 01
25//
26// ...with an incorrect answer...
27//
28// + 85: 0: TAG ff! ff! ff! ff! ff! ff! ff! ff! bb 33 bb 00 01! 0e! 04! bb !crc
29//
30// We still left the error signalling bytes in the traces like 0xbb
31//
32// A correct trace should look like this:
33//
34// + 21112: : 0c 03 e8 01
35// + 85: 0: TAG ff ff ff ff ff ff ff ff ea f5
36//
37//-----------------------------------------------------------------------------
38
99cf19d9 39#include "proxmark3.h"
cee5a30d 40#include "apps.h"
41#include "util.h"
42#include "string.h"
7e67e42f 43#include "common.h"
f38a1528 44#include "cmd.h"
1e262141 45// Needed for CRC in emulation mode;
46// same construction as in ISO 14443;
47// different initial value (CRC_ICLASS)
99cf19d9 48#include "iso14443crc.h"
49#include "iso15693tools.h"
b67f7ec3 50#include "protocols.h"
10a8875c 51#include "optimized_cipher.h"
cee5a30d 52
1e262141 53static int timeout = 4096;
cee5a30d 54
cee5a30d 55
1e262141 56static int SendIClassAnswer(uint8_t *resp, int respLen, int delay);
cee5a30d 57
58//-----------------------------------------------------------------------------
59// The software UART that receives commands from the reader, and its state
60// variables.
61//-----------------------------------------------------------------------------
62static struct {
63 enum {
64 STATE_UNSYNCD,
65 STATE_START_OF_COMMUNICATION,
66 STATE_RECEIVING
67 } state;
68 uint16_t shiftReg;
69 int bitCnt;
70 int byteCnt;
71 int byteCntMax;
72 int posCnt;
73 int nOutOfCnt;
74 int OutOfCnt;
75 int syncBit;
1e262141 76 int samples;
cee5a30d 77 int highCnt;
78 int swapper;
79 int counter;
80 int bitBuffer;
81 int dropPosition;
a501c82b 82 uint8_t *output;
cee5a30d 83} Uart;
84
1e262141 85static RAMFUNC int OutOfNDecoding(int bit)
cee5a30d 86{
9f693930 87 //int error = 0;
cee5a30d 88 int bitright;
89
90 if(!Uart.bitBuffer) {
91 Uart.bitBuffer = bit ^ 0xFF0;
92 return FALSE;
93 }
94 else {
95 Uart.bitBuffer <<= 4;
96 Uart.bitBuffer ^= bit;
97 }
98
99 /*if(Uart.swapper) {
100 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
101 Uart.byteCnt++;
102 Uart.swapper = 0;
103 if(Uart.byteCnt > 15) { return TRUE; }
104 }
105 else {
106 Uart.swapper = 1;
107 }*/
108
109 if(Uart.state != STATE_UNSYNCD) {
110 Uart.posCnt++;
111
112 if((Uart.bitBuffer & Uart.syncBit) ^ Uart.syncBit) {
113 bit = 0x00;
114 }
115 else {
116 bit = 0x01;
117 }
118 if(((Uart.bitBuffer << 1) & Uart.syncBit) ^ Uart.syncBit) {
119 bitright = 0x00;
120 }
121 else {
122 bitright = 0x01;
123 }
124 if(bit != bitright) { bit = bitright; }
125
126
127 // So, now we only have to deal with *bit*, lets see...
128 if(Uart.posCnt == 1) {
129 // measurement first half bitperiod
130 if(!bit) {
131 // Drop in first half means that we are either seeing
132 // an SOF or an EOF.
133
134 if(Uart.nOutOfCnt == 1) {
135 // End of Communication
136 Uart.state = STATE_UNSYNCD;
137 Uart.highCnt = 0;
138 if(Uart.byteCnt == 0) {
139 // Its not straightforward to show single EOFs
140 // So just leave it and do not return TRUE
a501c82b 141 Uart.output[0] = 0xf0;
cee5a30d 142 Uart.byteCnt++;
cee5a30d 143 }
144 else {
145 return TRUE;
146 }
147 }
148 else if(Uart.state != STATE_START_OF_COMMUNICATION) {
149 // When not part of SOF or EOF, it is an error
150 Uart.state = STATE_UNSYNCD;
151 Uart.highCnt = 0;
9f693930 152 //error = 4;
cee5a30d 153 }
154 }
155 }
156 else {
157 // measurement second half bitperiod
158 // Count the bitslot we are in... (ISO 15693)
159 Uart.nOutOfCnt++;
160
161 if(!bit) {
162 if(Uart.dropPosition) {
163 if(Uart.state == STATE_START_OF_COMMUNICATION) {
9f693930 164 //error = 1;
cee5a30d 165 }
166 else {
9f693930 167 //error = 7;
cee5a30d 168 }
169 // It is an error if we already have seen a drop in current frame
170 Uart.state = STATE_UNSYNCD;
171 Uart.highCnt = 0;
172 }
173 else {
174 Uart.dropPosition = Uart.nOutOfCnt;
175 }
176 }
177
178 Uart.posCnt = 0;
179
180
181 if(Uart.nOutOfCnt == Uart.OutOfCnt && Uart.OutOfCnt == 4) {
182 Uart.nOutOfCnt = 0;
183
184 if(Uart.state == STATE_START_OF_COMMUNICATION) {
185 if(Uart.dropPosition == 4) {
186 Uart.state = STATE_RECEIVING;
187 Uart.OutOfCnt = 256;
188 }
189 else if(Uart.dropPosition == 3) {
190 Uart.state = STATE_RECEIVING;
191 Uart.OutOfCnt = 4;
192 //Uart.output[Uart.byteCnt] = 0xdd;
193 //Uart.byteCnt++;
194 }
195 else {
196 Uart.state = STATE_UNSYNCD;
197 Uart.highCnt = 0;
198 }
199 Uart.dropPosition = 0;
200 }
201 else {
202 // RECEIVING DATA
203 // 1 out of 4
204 if(!Uart.dropPosition) {
205 Uart.state = STATE_UNSYNCD;
206 Uart.highCnt = 0;
9f693930 207 //error = 9;
cee5a30d 208 }
209 else {
210 Uart.shiftReg >>= 2;
211
212 // Swap bit order
213 Uart.dropPosition--;
214 //if(Uart.dropPosition == 1) { Uart.dropPosition = 2; }
215 //else if(Uart.dropPosition == 2) { Uart.dropPosition = 1; }
216
217 Uart.shiftReg ^= ((Uart.dropPosition & 0x03) << 6);
218 Uart.bitCnt += 2;
219 Uart.dropPosition = 0;
220
221 if(Uart.bitCnt == 8) {
222 Uart.output[Uart.byteCnt] = (Uart.shiftReg & 0xff);
223 Uart.byteCnt++;
cee5a30d 224 Uart.bitCnt = 0;
225 Uart.shiftReg = 0;
226 }
227 }
228 }
229 }
230 else if(Uart.nOutOfCnt == Uart.OutOfCnt) {
231 // RECEIVING DATA
232 // 1 out of 256
233 if(!Uart.dropPosition) {
234 Uart.state = STATE_UNSYNCD;
235 Uart.highCnt = 0;
9f693930 236 //error = 3;
cee5a30d 237 }
238 else {
239 Uart.dropPosition--;
240 Uart.output[Uart.byteCnt] = (Uart.dropPosition & 0xff);
241 Uart.byteCnt++;
cee5a30d 242 Uart.bitCnt = 0;
243 Uart.shiftReg = 0;
244 Uart.nOutOfCnt = 0;
245 Uart.dropPosition = 0;
246 }
247 }
248
249 /*if(error) {
250 Uart.output[Uart.byteCnt] = 0xAA;
251 Uart.byteCnt++;
252 Uart.output[Uart.byteCnt] = error & 0xFF;
253 Uart.byteCnt++;
254 Uart.output[Uart.byteCnt] = 0xAA;
255 Uart.byteCnt++;
256 Uart.output[Uart.byteCnt] = (Uart.bitBuffer >> 8) & 0xFF;
257 Uart.byteCnt++;
258 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
259 Uart.byteCnt++;
260 Uart.output[Uart.byteCnt] = (Uart.syncBit >> 3) & 0xFF;
261 Uart.byteCnt++;
262 Uart.output[Uart.byteCnt] = 0xAA;
263 Uart.byteCnt++;
264 return TRUE;
265 }*/
266 }
267
268 }
269 else {
270 bit = Uart.bitBuffer & 0xf0;
271 bit >>= 4;
272 bit ^= 0x0F; // drops become 1s ;-)
273 if(bit) {
274 // should have been high or at least (4 * 128) / fc
275 // according to ISO this should be at least (9 * 128 + 20) / fc
276 if(Uart.highCnt == 8) {
277 // we went low, so this could be start of communication
278 // it turns out to be safer to choose a less significant
279 // syncbit... so we check whether the neighbour also represents the drop
280 Uart.posCnt = 1; // apparently we are busy with our first half bit period
281 Uart.syncBit = bit & 8;
282 Uart.samples = 3;
283 if(!Uart.syncBit) { Uart.syncBit = bit & 4; Uart.samples = 2; }
284 else if(bit & 4) { Uart.syncBit = bit & 4; Uart.samples = 2; bit <<= 2; }
285 if(!Uart.syncBit) { Uart.syncBit = bit & 2; Uart.samples = 1; }
286 else if(bit & 2) { Uart.syncBit = bit & 2; Uart.samples = 1; bit <<= 1; }
287 if(!Uart.syncBit) { Uart.syncBit = bit & 1; Uart.samples = 0;
288 if(Uart.syncBit && (Uart.bitBuffer & 8)) {
289 Uart.syncBit = 8;
290
291 // the first half bit period is expected in next sample
292 Uart.posCnt = 0;
293 Uart.samples = 3;
294 }
295 }
296 else if(bit & 1) { Uart.syncBit = bit & 1; Uart.samples = 0; }
297
298 Uart.syncBit <<= 4;
299 Uart.state = STATE_START_OF_COMMUNICATION;
300 Uart.bitCnt = 0;
301 Uart.byteCnt = 0;
cee5a30d 302 Uart.nOutOfCnt = 0;
303 Uart.OutOfCnt = 4; // Start at 1/4, could switch to 1/256
304 Uart.dropPosition = 0;
305 Uart.shiftReg = 0;
9f693930 306 //error = 0;
cee5a30d 307 }
308 else {
309 Uart.highCnt = 0;
310 }
311 }
312 else {
313 if(Uart.highCnt < 8) {
314 Uart.highCnt++;
315 }
316 }
317 }
318
319 return FALSE;
320}
321
322//=============================================================================
1e262141 323// Manchester
cee5a30d 324//=============================================================================
325
326static struct {
327 enum {
328 DEMOD_UNSYNCD,
329 DEMOD_START_OF_COMMUNICATION,
330 DEMOD_START_OF_COMMUNICATION2,
331 DEMOD_START_OF_COMMUNICATION3,
332 DEMOD_SOF_COMPLETE,
333 DEMOD_MANCHESTER_D,
334 DEMOD_MANCHESTER_E,
335 DEMOD_END_OF_COMMUNICATION,
336 DEMOD_END_OF_COMMUNICATION2,
337 DEMOD_MANCHESTER_F,
338 DEMOD_ERROR_WAIT
339 } state;
340 int bitCount;
341 int posCount;
342 int syncBit;
cee5a30d 343 uint16_t shiftReg;
344 int buffer;
345 int buffer2;
346 int buffer3;
347 int buff;
348 int samples;
349 int len;
350 enum {
351 SUB_NONE,
352 SUB_FIRST_HALF,
353 SUB_SECOND_HALF,
354 SUB_BOTH
355 } sub;
356 uint8_t *output;
357} Demod;
358
359static RAMFUNC int ManchesterDecoding(int v)
360{
361 int bit;
362 int modulation;
363 int error = 0;
364
365 bit = Demod.buffer;
366 Demod.buffer = Demod.buffer2;
367 Demod.buffer2 = Demod.buffer3;
368 Demod.buffer3 = v;
369
370 if(Demod.buff < 3) {
371 Demod.buff++;
372 return FALSE;
373 }
374
375 if(Demod.state==DEMOD_UNSYNCD) {
376 Demod.output[Demod.len] = 0xfa;
377 Demod.syncBit = 0;
378 //Demod.samples = 0;
379 Demod.posCount = 1; // This is the first half bit period, so after syncing handle the second part
cee5a30d 380
381 if(bit & 0x08) {
382 Demod.syncBit = 0x08;
383 }
384
385 if(bit & 0x04) {
386 if(Demod.syncBit) {
387 bit <<= 4;
388 }
389 Demod.syncBit = 0x04;
390 }
391
392 if(bit & 0x02) {
393 if(Demod.syncBit) {
394 bit <<= 2;
395 }
396 Demod.syncBit = 0x02;
397 }
398
399 if(bit & 0x01 && Demod.syncBit) {
400 Demod.syncBit = 0x01;
401 }
402
403 if(Demod.syncBit) {
404 Demod.len = 0;
405 Demod.state = DEMOD_START_OF_COMMUNICATION;
406 Demod.sub = SUB_FIRST_HALF;
407 Demod.bitCount = 0;
408 Demod.shiftReg = 0;
cee5a30d 409 Demod.samples = 0;
410 if(Demod.posCount) {
411 //if(trigger) LED_A_OFF(); // Not useful in this case...
412 switch(Demod.syncBit) {
413 case 0x08: Demod.samples = 3; break;
414 case 0x04: Demod.samples = 2; break;
415 case 0x02: Demod.samples = 1; break;
416 case 0x01: Demod.samples = 0; break;
417 }
418 // SOF must be long burst... otherwise stay unsynced!!!
419 if(!(Demod.buffer & Demod.syncBit) || !(Demod.buffer2 & Demod.syncBit)) {
420 Demod.state = DEMOD_UNSYNCD;
421 }
422 }
423 else {
424 // SOF must be long burst... otherwise stay unsynced!!!
425 if(!(Demod.buffer2 & Demod.syncBit) || !(Demod.buffer3 & Demod.syncBit)) {
426 Demod.state = DEMOD_UNSYNCD;
427 error = 0x88;
428 }
5cc88edf 429
430 // TODO: use this error value to print? Ask Holiman.
431 // 2016-01-08 iceman
cee5a30d 432 }
433 error = 0;
cee5a30d 434 }
435 }
436 else {
437 modulation = bit & Demod.syncBit;
438 modulation |= ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit;
cee5a30d 439
440 Demod.samples += 4;
441
442 if(Demod.posCount==0) {
443 Demod.posCount = 1;
444 if(modulation) {
445 Demod.sub = SUB_FIRST_HALF;
446 }
447 else {
448 Demod.sub = SUB_NONE;
449 }
450 }
451 else {
452 Demod.posCount = 0;
453 /*(modulation && (Demod.sub == SUB_FIRST_HALF)) {
454 if(Demod.state!=DEMOD_ERROR_WAIT) {
455 Demod.state = DEMOD_ERROR_WAIT;
456 Demod.output[Demod.len] = 0xaa;
457 error = 0x01;
458 }
459 }*/
460 //else if(modulation) {
461 if(modulation) {
462 if(Demod.sub == SUB_FIRST_HALF) {
463 Demod.sub = SUB_BOTH;
464 }
465 else {
466 Demod.sub = SUB_SECOND_HALF;
467 }
468 }
469 else if(Demod.sub == SUB_NONE) {
470 if(Demod.state == DEMOD_SOF_COMPLETE) {
471 Demod.output[Demod.len] = 0x0f;
472 Demod.len++;
cee5a30d 473 Demod.state = DEMOD_UNSYNCD;
474// error = 0x0f;
475 return TRUE;
476 }
477 else {
478 Demod.state = DEMOD_ERROR_WAIT;
479 error = 0x33;
480 }
481 /*if(Demod.state!=DEMOD_ERROR_WAIT) {
482 Demod.state = DEMOD_ERROR_WAIT;
483 Demod.output[Demod.len] = 0xaa;
484 error = 0x01;
485 }*/
486 }
487
488 switch(Demod.state) {
489 case DEMOD_START_OF_COMMUNICATION:
490 if(Demod.sub == SUB_BOTH) {
491 //Demod.state = DEMOD_MANCHESTER_D;
492 Demod.state = DEMOD_START_OF_COMMUNICATION2;
493 Demod.posCount = 1;
494 Demod.sub = SUB_NONE;
495 }
496 else {
497 Demod.output[Demod.len] = 0xab;
498 Demod.state = DEMOD_ERROR_WAIT;
499 error = 0xd2;
500 }
501 break;
502 case DEMOD_START_OF_COMMUNICATION2:
503 if(Demod.sub == SUB_SECOND_HALF) {
504 Demod.state = DEMOD_START_OF_COMMUNICATION3;
505 }
506 else {
507 Demod.output[Demod.len] = 0xab;
508 Demod.state = DEMOD_ERROR_WAIT;
509 error = 0xd3;
510 }
511 break;
512 case DEMOD_START_OF_COMMUNICATION3:
513 if(Demod.sub == SUB_SECOND_HALF) {
514// Demod.state = DEMOD_MANCHESTER_D;
515 Demod.state = DEMOD_SOF_COMPLETE;
516 //Demod.output[Demod.len] = Demod.syncBit & 0xFF;
517 //Demod.len++;
518 }
519 else {
520 Demod.output[Demod.len] = 0xab;
521 Demod.state = DEMOD_ERROR_WAIT;
522 error = 0xd4;
523 }
524 break;
525 case DEMOD_SOF_COMPLETE:
526 case DEMOD_MANCHESTER_D:
527 case DEMOD_MANCHESTER_E:
528 // OPPOSITE FROM ISO14443 - 11110000 = 0 (1 in 14443)
529 // 00001111 = 1 (0 in 14443)
530 if(Demod.sub == SUB_SECOND_HALF) { // SUB_FIRST_HALF
531 Demod.bitCount++;
532 Demod.shiftReg = (Demod.shiftReg >> 1) ^ 0x100;
533 Demod.state = DEMOD_MANCHESTER_D;
534 }
535 else if(Demod.sub == SUB_FIRST_HALF) { // SUB_SECOND_HALF
536 Demod.bitCount++;
537 Demod.shiftReg >>= 1;
538 Demod.state = DEMOD_MANCHESTER_E;
539 }
540 else if(Demod.sub == SUB_BOTH) {
541 Demod.state = DEMOD_MANCHESTER_F;
542 }
543 else {
544 Demod.state = DEMOD_ERROR_WAIT;
545 error = 0x55;
546 }
547 break;
548
549 case DEMOD_MANCHESTER_F:
550 // Tag response does not need to be a complete byte!
551 if(Demod.len > 0 || Demod.bitCount > 0) {
552 if(Demod.bitCount > 1) { // was > 0, do not interpret last closing bit, is part of EOF
f5ed4d12 553 Demod.shiftReg >>= (9 - Demod.bitCount); // right align data
cee5a30d 554 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
555 Demod.len++;
cee5a30d 556 }
557
558 Demod.state = DEMOD_UNSYNCD;
559 return TRUE;
560 }
561 else {
562 Demod.output[Demod.len] = 0xad;
563 Demod.state = DEMOD_ERROR_WAIT;
564 error = 0x03;
565 }
566 break;
567
568 case DEMOD_ERROR_WAIT:
569 Demod.state = DEMOD_UNSYNCD;
570 break;
571
572 default:
573 Demod.output[Demod.len] = 0xdd;
574 Demod.state = DEMOD_UNSYNCD;
575 break;
576 }
577
578 /*if(Demod.bitCount>=9) {
579 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
580 Demod.len++;
581
582 Demod.parityBits <<= 1;
583 Demod.parityBits ^= ((Demod.shiftReg >> 8) & 0x01);
584
585 Demod.bitCount = 0;
586 Demod.shiftReg = 0;
587 }*/
588 if(Demod.bitCount>=8) {
589 Demod.shiftReg >>= 1;
590 Demod.output[Demod.len] = (Demod.shiftReg & 0xff);
591 Demod.len++;
cee5a30d 592 Demod.bitCount = 0;
593 Demod.shiftReg = 0;
594 }
595
596 if(error) {
597 Demod.output[Demod.len] = 0xBB;
598 Demod.len++;
599 Demod.output[Demod.len] = error & 0xFF;
600 Demod.len++;
601 Demod.output[Demod.len] = 0xBB;
602 Demod.len++;
603 Demod.output[Demod.len] = bit & 0xFF;
604 Demod.len++;
605 Demod.output[Demod.len] = Demod.buffer & 0xFF;
606 Demod.len++;
607 // Look harder ;-)
608 Demod.output[Demod.len] = Demod.buffer2 & 0xFF;
609 Demod.len++;
610 Demod.output[Demod.len] = Demod.syncBit & 0xFF;
611 Demod.len++;
612 Demod.output[Demod.len] = 0xBB;
613 Demod.len++;
614 return TRUE;
615 }
616
617 }
618
619 } // end (state != UNSYNCED)
620
621 return FALSE;
622}
623
624//=============================================================================
1e262141 625// Finally, a `sniffer' for iClass communication
cee5a30d 626// Both sides of communication!
627//=============================================================================
628
629//-----------------------------------------------------------------------------
630// Record the sequence of commands sent by the reader to the tag, with
631// triggering so that we start recording at the point that the tag is moved
632// near the reader.
633//-----------------------------------------------------------------------------
634void RAMFUNC SnoopIClass(void)
635{
99cf19d9 636
637
cee5a30d 638 // We won't start recording the frames that we acquire until we trigger;
639 // a good trigger condition to get started is probably when we see a
640 // response from the tag.
9f693930 641 //int triggered = FALSE; // FALSE to wait first for card
cee5a30d 642
643 // The command (reader -> tag) that we're receiving.
644 // The length of a received command will in most cases be no more than 18 bytes.
645 // So 32 should be enough!
f71f4deb 646 #define ICLASS_BUFFER_SIZE 32
647 uint8_t readerToTagCmd[ICLASS_BUFFER_SIZE];
cee5a30d 648 // The response (tag -> reader) that we're receiving.
f71f4deb 649 uint8_t tagToReaderResponse[ICLASS_BUFFER_SIZE];
6a1f2d82 650
7cc204bf 651 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
652
f71f4deb 653 // free all BigBuf memory
654 BigBuf_free();
655 // The DMA buffer, used to stream samples from the FPGA
656 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
657
3000dc4e
MHS		 658 set_tracing(TRUE);
659 clear_trace();
1e262141 660 iso14a_set_trigger(FALSE);
cee5a30d 661
cee5a30d 662 int lastRxCounter;
117d9ec2 663 uint8_t *upTo;
cee5a30d 664 int smpl;
665 int maxBehindBy = 0;
666
667 // Count of samples received so far, so that we can include timing
668 // information in the trace buffer.
669 int samples = 0;
670 rsamples = 0;
671
cee5a30d 672 // Set up the demodulator for tag -> reader responses.
17cba269 673 Demod.output = tagToReaderResponse;
cee5a30d 674 Demod.len = 0;
675 Demod.state = DEMOD_UNSYNCD;
676
677 // Setup for the DMA.
678 FpgaSetupSsc();
679 upTo = dmaBuf;
680 lastRxCounter = DMA_BUFFER_SIZE;
681 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
682
683 // And the reader -> tag commands
684 memset(&Uart, 0, sizeof(Uart));
17cba269 685 Uart.output = readerToTagCmd;
cee5a30d 686 Uart.byteCntMax = 32; // was 100 (greg)////////////////////////////////////////////////////////////////////////
687 Uart.state = STATE_UNSYNCD;
688
689 // And put the FPGA in the appropriate mode
690 // Signal field is off with the appropriate LED
691 LED_D_OFF();
692 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_SNIFFER);
693 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
694
81012e67 695 uint32_t time_0 = GetCountSspClk();
55eaed8f
MHS		 696 uint32_t time_start = 0;
697 uint32_t time_stop = 0;
81012e67 698
cee5a30d 699 int div = 0;
700 //int div2 = 0;
701 int decbyte = 0;
702 int decbyter = 0;
703
704 // And now we loop, receiving samples.
705 for(;;) {
706 LED_A_ON();
707 WDT_HIT();
708 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &
709 (DMA_BUFFER_SIZE-1);
710 if(behindBy > maxBehindBy) {
711 maxBehindBy = behindBy;
f71f4deb 712 if(behindBy > (9 * DMA_BUFFER_SIZE / 10)) {
cee5a30d 713 Dbprintf("blew circular buffer! behindBy=0x%x", behindBy);
714 goto done;
715 }
716 }
717 if(behindBy < 1) continue;
718
719 LED_A_OFF();
720 smpl = upTo[0];
721 upTo++;
722 lastRxCounter -= 1;
723 if(upTo - dmaBuf > DMA_BUFFER_SIZE) {
724 upTo -= DMA_BUFFER_SIZE;
725 lastRxCounter += DMA_BUFFER_SIZE;
726 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
727 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
728 }
729
730 //samples += 4;
731 samples += 1;
cee5a30d 732
cee5a30d 733 if(smpl & 0xF) {
734 decbyte ^= (1 << (3 - div));
735 }
cee5a30d 736
737 // FOR READER SIDE COMMUMICATION...
17cba269 738
cee5a30d 739 decbyter <<= 2;
740 decbyter ^= (smpl & 0x30);
741
742 div++;
743
744 if((div + 1) % 2 == 0) {
745 smpl = decbyter;
1e262141 746 if(OutOfNDecoding((smpl & 0xF0) >> 4)) {
cee5a30d 747 rsamples = samples - Uart.samples;
55eaed8f 748 time_stop = (GetCountSspClk()-time_0) << 4;
cee5a30d 749 LED_C_ON();
17cba269 750
81012e67 751 //if(!LogTrace(Uart.output,Uart.byteCnt, rsamples, Uart.parityBits,TRUE)) break;
17cba269 752 //if(!LogTrace(NULL, 0, Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, 0, TRUE)) break;
6a1f2d82 753 if(tracing) {
a501c82b 754 uint8_t parity[MAX_PARITY_SIZE];
755 GetParity(Uart.output, Uart.byteCnt, parity);
55eaed8f 756 LogTrace(Uart.output,Uart.byteCnt, time_start, time_stop, parity, TRUE);
81012e67
MHS		 757 }
758
17cba269
MHS		 759
760 /* And ready to receive another command. */
cee5a30d 761 Uart.state = STATE_UNSYNCD;
762 /* And also reset the demod code, which might have been */
763 /* false-triggered by the commands from the reader. */
764 Demod.state = DEMOD_UNSYNCD;
765 LED_B_OFF();
766 Uart.byteCnt = 0;
55eaed8f
MHS		 767 }else{
768 time_start = (GetCountSspClk()-time_0) << 4;
cee5a30d 769 }
770 decbyter = 0;
771 }
772
773 if(div > 3) {
774 smpl = decbyte;
775 if(ManchesterDecoding(smpl & 0x0F)) {
55eaed8f
MHS		 776 time_stop = (GetCountSspClk()-time_0) << 4;
777
cee5a30d 778 rsamples = samples - Demod.samples;
779 LED_B_ON();
780
6a1f2d82 781 if(tracing) {
a501c82b 782 uint8_t parity[MAX_PARITY_SIZE];
783 GetParity(Demod.output, Demod.len, parity);
55eaed8f 784 LogTrace(Demod.output, Demod.len, time_start, time_stop, parity, FALSE);
81012e67 785 }
17cba269 786
cee5a30d 787 // And ready to receive another response.
788 memset(&Demod, 0, sizeof(Demod));
17cba269 789 Demod.output = tagToReaderResponse;
cee5a30d 790 Demod.state = DEMOD_UNSYNCD;
791 LED_C_OFF();
55eaed8f
MHS		 792 }else{
793 time_start = (GetCountSspClk()-time_0) << 4;
cee5a30d 794 }
795
796 div = 0;
797 decbyte = 0x00;
798 }
799 //}
800
801 if(BUTTON_PRESS()) {
802 DbpString("cancelled_a");
803 goto done;
804 }
805 }
806
807 DbpString("COMMAND FINISHED");
808
809 Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
3000dc4e 810 Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
cee5a30d 811
812done:
813 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
814 Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
3000dc4e 815 Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
cee5a30d 816 LED_A_OFF();
817 LED_B_OFF();
1e262141 818 LED_C_OFF();
819 LED_D_OFF();
5ee53a0e 820 set_tracing(FALSE);
1e262141 821}
822
912a3e94 823void rotateCSN(uint8_t* originalCSN, uint8_t* rotatedCSN) {
824 int i;
825 for(i = 0; i < 8; i++) {
826 rotatedCSN[i] = (originalCSN[i] >> 3) | (originalCSN[(i+1)%8] << 5);
1e262141 827 }
828}
829
830//-----------------------------------------------------------------------------
831// Wait for commands from reader
832// Stop when button is pressed
833// Or return TRUE when command is captured
834//-----------------------------------------------------------------------------
835static int GetIClassCommandFromReader(uint8_t *received, int *len, int maxLen)
836{
912a3e94 837 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1e262141 838 // only, since we are receiving, not transmitting).
839 // Signal field is off with the appropriate LED
840 LED_D_OFF();
841 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
842
843 // Now run a `software UART' on the stream of incoming samples.
844 Uart.output = received;
845 Uart.byteCntMax = maxLen;
846 Uart.state = STATE_UNSYNCD;
847
848 for(;;) {
849 WDT_HIT();
850
851 if(BUTTON_PRESS()) return FALSE;
852
853 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
854 AT91C_BASE_SSC->SSC_THR = 0x00;
855 }
856 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
857 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
95e63594 858
1e262141 859 if(OutOfNDecoding(b & 0x0f)) {
860 *len = Uart.byteCnt;
861 return TRUE;
862 }
863 }
864 }
865}
866
645c960f
MHS		 867static uint8_t encode4Bits(const uint8_t b)
868{
869 uint8_t c = b & 0xF;
870 // OTA, the least significant bits first
871 // The columns are
872 // 1 - Bit value to send
873 // 2 - Reversed (big-endian)
874 // 3 - Encoded
875 // 4 - Hex values
876
877 switch(c){
878 // 1 2 3 4
879 case 15: return 0x55; // 1111 -> 1111 -> 01010101 -> 0x55
880 case 14: return 0x95; // 1110 -> 0111 -> 10010101 -> 0x95
881 case 13: return 0x65; // 1101 -> 1011 -> 01100101 -> 0x65
882 case 12: return 0xa5; // 1100 -> 0011 -> 10100101 -> 0xa5
883 case 11: return 0x59; // 1011 -> 1101 -> 01011001 -> 0x59
884 case 10: return 0x99; // 1010 -> 0101 -> 10011001 -> 0x99
885 case 9: return 0x69; // 1001 -> 1001 -> 01101001 -> 0x69
886 case 8: return 0xa9; // 1000 -> 0001 -> 10101001 -> 0xa9
887 case 7: return 0x56; // 0111 -> 1110 -> 01010110 -> 0x56
888 case 6: return 0x96; // 0110 -> 0110 -> 10010110 -> 0x96
889 case 5: return 0x66; // 0101 -> 1010 -> 01100110 -> 0x66
890 case 4: return 0xa6; // 0100 -> 0010 -> 10100110 -> 0xa6
891 case 3: return 0x5a; // 0011 -> 1100 -> 01011010 -> 0x5a
892 case 2: return 0x9a; // 0010 -> 0100 -> 10011010 -> 0x9a
893 case 1: return 0x6a; // 0001 -> 1000 -> 01101010 -> 0x6a
894 default: return 0xaa; // 0000 -> 0000 -> 10101010 -> 0xaa
895
896 }
897}
1e262141 898
899//-----------------------------------------------------------------------------
900// Prepare tag messages
901//-----------------------------------------------------------------------------
902static void CodeIClassTagAnswer(const uint8_t *cmd, int len)
903{
645c960f
MHS		 904
905 /*
906 * SOF comprises 3 parts;
907 * * An unmodulated time of 56.64 us
908 * * 24 pulses of 423.75 KHz (fc/32)
909 * * A logic 1, which starts with an unmodulated time of 18.88us
910 * followed by 8 pulses of 423.75kHz (fc/32)
911 *
912 *
913 * EOF comprises 3 parts:
914 * - A logic 0 (which starts with 8 pulses of fc/32 followed by an unmodulated
915 * time of 18.88us.
916 * - 24 pulses of fc/32
917 * - An unmodulated time of 56.64 us
918 *
919 *
920 * A logic 0 starts with 8 pulses of fc/32
921 * followed by an unmodulated time of 256/fc (~18,88us).
922 *
923 * A logic 0 starts with unmodulated time of 256/fc (~18,88us) followed by
924 * 8 pulses of fc/32 (also 18.88us)
925 *
926 * The mode FPGA_HF_SIMULATOR_MODULATE_424K_8BIT which we use to simulate tag,
927 * works like this.
928 * - A 1-bit input to the FPGA becomes 8 pulses on 423.5kHz (fc/32) (18.88us).
929 * - A 0-bit inptu to the FPGA becomes an unmodulated time of 18.88us
930 *
6b038d19 931 * In this mode the SOF can be written as 00011101 = 0x1D
645c960f
MHS		 932 * The EOF can be written as 10111000 = 0xb8
933 * A logic 1 is 01
934 * A logic 0 is 10
935 *
936 * */
937
1e262141 938 int i;
939
940 ToSendReset();
941
942 // Send SOF
645c960f 943 ToSend[++ToSendMax] = 0x1D;
1e262141 944
945 for(i = 0; i < len; i++) {
1e262141 946 uint8_t b = cmd[i];
645c960f
MHS		 947 ToSend[++ToSendMax] = encode4Bits(b & 0xF); //Least significant half
948 ToSend[++ToSendMax] = encode4Bits((b >>4) & 0xF);//Most significant half
1e262141 949 }
1e262141 950
951 // Send EOF
645c960f 952 ToSend[++ToSendMax] = 0xB8;
81012e67 953 //lastProxToAirDuration = 8*ToSendMax - 3*8 - 3*8;//Not counting zeroes in the beginning or end
1e262141 954 // Convert from last byte pos to length
955 ToSendMax++;
956}
957
958// Only SOF
959static void CodeIClassTagSOF()
960{
81012e67
MHS		 961 //So far a dummy implementation, not used
962 //int lastProxToAirDuration =0;
1e262141 963
81012e67 964 ToSendReset();
1e262141 965 // Send SOF
645c960f 966 ToSend[++ToSendMax] = 0x1D;
81012e67
MHS		 967// lastProxToAirDuration = 8*ToSendMax - 3*8;//Not counting zeroes in the beginning
968
1e262141 969 // Convert from last byte pos to length
970 ToSendMax++;
971}
b67f7ec3
MHS		 972#define MODE_SIM_CSN 0
973#define MODE_EXIT_AFTER_MAC 1
974#define MODE_FULLSIM 2
55eaed8f 975
b67f7ec3 976int doIClassSimulation(int simulationMode, uint8_t *reader_mac_buf);
ff7bb4ef
MHS		 977/**
978 * @brief SimulateIClass simulates an iClass card.
979 * @param arg0 type of simulation
980 * - 0 uses the first 8 bytes in usb data as CSN
981 * - 2 "dismantling iclass"-attack. This mode iterates through all CSN's specified
982 * in the usb data. This mode collects MAC from the reader, in order to do an offline
983 * attack on the keys. For more info, see "dismantling iclass" and proxclone.com.
984 * - Other : Uses the default CSN (031fec8af7ff12e0)
985 * @param arg1 - number of CSN's contained in datain (applicable for mode 2 only)
986 * @param arg2
987 * @param datain
988 */
989void SimulateIClass(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain)
1e262141 990{
ff7bb4ef
MHS		 991 uint32_t simType = arg0;
992 uint32_t numberOfCSNS = arg1;
7cc204bf 993 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1e262141 994
ff7bb4ef 995 // Enable and clear the trace
3000dc4e
MHS		 996 set_tracing(TRUE);
997 clear_trace();
b67f7ec3
MHS		 998 //Use the emulator memory for SIM
999 uint8_t *emulator = BigBuf_get_EM_addr();
81cd0474 1000
ff7bb4ef
MHS		 1001 if(simType == 0) {
1002 // Use the CSN from commandline
b67f7ec3
MHS		 1003 memcpy(emulator, datain, 8);
1004 doIClassSimulation(MODE_SIM_CSN,NULL);
ff7bb4ef
MHS		 1005 }else if(simType == 1)
1006 {
b67f7ec3
MHS		 1007 //Default CSN
1008 uint8_t csn_crc[] = { 0x03, 0x1f, 0xec, 0x8a, 0xf7, 0xff, 0x12, 0xe0, 0x00, 0x00 };
1009 // Use the CSN from commandline
1010 memcpy(emulator, csn_crc, 8);
1011 doIClassSimulation(MODE_SIM_CSN,NULL);
ff7bb4ef
MHS		 1012 }
1013 else if(simType == 2)
1014 {
9f6e9d15 1015
7b941c8d 1016 uint8_t mac_responses[USB_CMD_DATA_SIZE] = { 0 };
a501c82b 1017 Dbprintf("Going into attack mode, %d CSNS sent", numberOfCSNS);
ff7bb4ef
MHS		 1018 // In this mode, a number of csns are within datain. We'll simulate each one, one at a time
1019 // in order to collect MAC's from the reader. This can later be used in an offlne-attack
1020 // in order to obtain the keys, as in the "dismantling iclass"-paper.
9f6e9d15
MHS		 1021 int i = 0;
1022 for( ; i < numberOfCSNS && i*8+8 < USB_CMD_DATA_SIZE; i++)
ff7bb4ef
MHS		 1023 {
1024 // The usb data is 512 bytes, fitting 65 8-byte CSNs in there.
1025
b67f7ec3
MHS		 1026 memcpy(emulator, datain+(i*8), 8);
1027 if(doIClassSimulation(MODE_EXIT_AFTER_MAC,mac_responses+i*8))
f83cc126 1028 {
645c960f 1029 cmd_send(CMD_ACK,CMD_SIMULATE_TAG_ICLASS,i,0,mac_responses,i*8);
f83cc126
MHS		 1030 return; // Button pressed
1031 }
ff7bb4ef 1032 }
9f6e9d15
MHS		 1033 cmd_send(CMD_ACK,CMD_SIMULATE_TAG_ICLASS,i,0,mac_responses,i*8);
1034
b67f7ec3
MHS		 1035 }else if(simType == 3){
1036 //This is 'full sim' mode, where we use the emulator storage for data.
1037 doIClassSimulation(MODE_FULLSIM, NULL);
81012e67
MHS		 1038 }
1039 else{
ff7bb4ef
MHS		 1040 // We may want a mode here where we hardcode the csns to use (from proxclone).
1041 // That will speed things up a little, but not required just yet.
1042 Dbprintf("The mode is not implemented, reserved for future use");
1043 }
9f6e9d15 1044 Dbprintf("Done...");
5ee53a0e 1045 set_tracing(FALSE);
ff7bb4ef 1046}
c8387e85
MHS		 1047void AppendCrc(uint8_t* data, int len)
1048{
1049 ComputeCrc14443(CRC_ICLASS,data,len,data+len,data+len+1);
1050}
b67f7ec3 1051
ff7bb4ef
MHS		 1052/**
1053 * @brief Does the actual simulation
1054 * @param csn - csn to use
1055 * @param breakAfterMacReceived if true, returns after reader MAC has been received.
1056 */
b67f7ec3 1057int doIClassSimulation( int simulationMode, uint8_t *reader_mac_buf)
ff7bb4ef 1058{
b67f7ec3
MHS		 1059 // free eventually allocated BigBuf memory
1060 BigBuf_free_keep_EM();
55eaed8f 1061
61fe9073
MHS		 1062 State cipher_state;
1063// State cipher_state_reserve;
b67f7ec3
MHS		 1064 uint8_t *csn = BigBuf_get_EM_addr();
1065 uint8_t *emulator = csn;
1066 uint8_t sof_data[] = { 0x0F} ;
1e262141 1067 // CSN followed by two CRC bytes
b67f7ec3
MHS		 1068 uint8_t anticoll_data[10] = { 0 };
1069 uint8_t csn_data[10] = { 0 };
1070 memcpy(csn_data,csn,sizeof(csn_data));
f83cc126 1071 Dbprintf("Simulating CSN %02x%02x%02x%02x%02x%02x%02x%02x",csn[0],csn[1],csn[2],csn[3],csn[4],csn[5],csn[6],csn[7]);
1e262141 1072
1e262141 1073 // Construct anticollision-CSN
b67f7ec3 1074 rotateCSN(csn_data,anticoll_data);
1e262141 1075
1076 // Compute CRC on both CSNs
b67f7ec3
MHS		 1077 ComputeCrc14443(CRC_ICLASS, anticoll_data, 8, &anticoll_data[8], &anticoll_data[9]);
1078 ComputeCrc14443(CRC_ICLASS, csn_data, 8, &csn_data[8], &csn_data[9]);
1079
61fe9073 1080 uint8_t diversified_key[8] = { 0 };
b67f7ec3
MHS		 1081 // e-Purse
1082 uint8_t card_challenge_data[8] = { 0x00 };
1083 if(simulationMode == MODE_FULLSIM)
1084 {
e5cd4ee4
MHS		 1085 //The diversified key should be stored on block 3
1086 //Get the diversified key from emulator memory
1087 memcpy(diversified_key, emulator+(8*3),8);
1088
b67f7ec3
MHS		 1089 //Card challenge, a.k.a e-purse is on block 2
1090 memcpy(card_challenge_data,emulator + (8 * 2) , 8);
61fe9073 1091 //Precalculate the cipher state, feeding it the CC
e5cd4ee4
MHS		 1092 cipher_state = opt_doTagMAC_1(card_challenge_data,diversified_key);
1093
b67f7ec3 1094 }
1e262141 1095
ff7bb4ef 1096 int exitLoop = 0;
1e262141 1097 // Reader 0a
1098 // Tag 0f
1099 // Reader 0c
1100 // Tag anticoll. CSN
1101 // Reader 81 anticoll. CSN
1102 // Tag CSN
1103
55eaed8f 1104 uint8_t *modulated_response;
b19caaef 1105 int modulated_response_size = 0;
55eaed8f
MHS		 1106 uint8_t* trace_data = NULL;
1107 int trace_data_size = 0;
1e262141 1108
b67f7ec3 1109
645c960f 1110 // Respond SOF -- takes 1 bytes
b67f7ec3
MHS		 1111 uint8_t *resp_sof = BigBuf_malloc(2);
1112 int resp_sof_Len;
1e262141 1113
1114 // Anticollision CSN (rotated CSN)
645c960f 1115 // 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
b67f7ec3
MHS		 1116 uint8_t *resp_anticoll = BigBuf_malloc(28);
1117 int resp_anticoll_len;
1e262141 1118
1119 // CSN
645c960f 1120 // 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
b67f7ec3
MHS		 1121 uint8_t *resp_csn = BigBuf_malloc(30);
1122 int resp_csn_len;
1e262141 1123
1124 // e-Purse
b3cc5f29 1125 // 18: Takes 2 bytes for SOF/EOF and 8 * 2 = 16 bytes (2 bytes/bit)
b67f7ec3
MHS		 1126 uint8_t *resp_cc = BigBuf_malloc(20);
1127 int resp_cc_len;
1e262141 1128
f71f4deb 1129 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1e262141 1130 int len;
1131
1e262141 1132 // Prepare card messages
1133 ToSendMax = 0;
1134
1135 // First card answer: SOF
1136 CodeIClassTagSOF();
b67f7ec3 1137 memcpy(resp_sof, ToSend, ToSendMax); resp_sof_Len = ToSendMax;
1e262141 1138
1139 // Anticollision CSN
b67f7ec3
MHS		 1140 CodeIClassTagAnswer(anticoll_data, sizeof(anticoll_data));
1141 memcpy(resp_anticoll, ToSend, ToSendMax); resp_anticoll_len = ToSendMax;
1e262141 1142
1143 // CSN
b67f7ec3
MHS		 1144 CodeIClassTagAnswer(csn_data, sizeof(csn_data));
1145 memcpy(resp_csn, ToSend, ToSendMax); resp_csn_len = ToSendMax;
1e262141 1146
1147 // e-Purse
b67f7ec3
MHS		 1148 CodeIClassTagAnswer(card_challenge_data, sizeof(card_challenge_data));
1149 memcpy(resp_cc, ToSend, ToSendMax); resp_cc_len = ToSendMax;
1e262141 1150
b19caaef 1151 //This is used for responding to READ-block commands or other data which is dynamically generated
c8387e85
MHS		 1152 //First the 'trace'-data, not encoded for FPGA
1153 uint8_t *data_generic_trace = BigBuf_malloc(8 + 2);//8 bytes data + 2byte CRC is max tag answer
1154 //Then storage for the modulated data
1155 //Each bit is doubled when modulated for FPGA, and we also have SOF and EOF (2 bytes)
1156 uint8_t *data_response = BigBuf_malloc( (8+2) * 2 + 2);
e3dc1e4c
MHS		 1157
1158 // Start from off (no field generated)
fa541aca
MHS		 1159 //FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1160 //SpinDelay(200);
1161 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1162 SpinDelay(100);
1163 StartCountSspClk();
1e262141 1164 // We need to listen to the high-frequency, peak-detected path.
1165 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1166 FpgaSetupSsc();
1167
1168 // To control where we are in the protocol
1e262141 1169 int cmdsRecvd = 0;
81012e67
MHS		 1170 uint32_t time_0 = GetCountSspClk();
1171 uint32_t t2r_time =0;
1172 uint32_t r2t_time =0;
912a3e94 1173
1e262141 1174 LED_A_ON();
f83cc126 1175 bool buttonPressed = false;
e5cd4ee4 1176 uint8_t response_delay = 1;
ff7bb4ef 1177 while(!exitLoop) {
e5cd4ee4 1178 response_delay = 1;
1e262141 1179 LED_B_OFF();
e3dc1e4c
MHS		 1180 //Signal tracer
1181 // Can be used to get a trigger for an oscilloscope..
1182 LED_C_OFF();
1183
1e262141 1184 if(!GetIClassCommandFromReader(receivedCmd, &len, 100)) {
f83cc126 1185 buttonPressed = true;
1e262141 1186 break;
81cd0474 1187 }
81012e67 1188 r2t_time = GetCountSspClk();
e3dc1e4c
MHS		 1189 //Signal tracer
1190 LED_C_ON();
1e262141 1191
81cd0474 1192 // Okay, look at the command now.
b67f7ec3 1193 if(receivedCmd[0] == ICLASS_CMD_ACTALL ) {
1e262141 1194 // Reader in anticollission phase
b67f7ec3
MHS		 1195 modulated_response = resp_sof; modulated_response_size = resp_sof_Len; //order = 1;
1196 trace_data = sof_data;
1197 trace_data_size = sizeof(sof_data);
1198 } else if(receivedCmd[0] == ICLASS_CMD_READ_OR_IDENTIFY && len == 1) {
1e262141 1199 // Reader asks for anticollission CSN
b67f7ec3
MHS		 1200 modulated_response = resp_anticoll; modulated_response_size = resp_anticoll_len; //order = 2;
1201 trace_data = anticoll_data;
1202 trace_data_size = sizeof(anticoll_data);
1e262141 1203 //DbpString("Reader requests anticollission CSN:");
b67f7ec3 1204 } else if(receivedCmd[0] == ICLASS_CMD_SELECT) {
1e262141 1205 // Reader selects anticollission CSN.
1206 // Tag sends the corresponding real CSN
b67f7ec3
MHS		 1207 modulated_response = resp_csn; modulated_response_size = resp_csn_len; //order = 3;
1208 trace_data = csn_data;
1209 trace_data_size = sizeof(csn_data);
1e262141 1210 //DbpString("Reader selects anticollission CSN:");
b67f7ec3 1211 } else if(receivedCmd[0] == ICLASS_CMD_READCHECK_KD) {
1e262141 1212 // Read e-purse (88 02)
b67f7ec3
MHS		 1213 modulated_response = resp_cc; modulated_response_size = resp_cc_len; //order = 4;
1214 trace_data = card_challenge_data;
1215 trace_data_size = sizeof(card_challenge_data);
1e262141 1216 LED_B_ON();
b67f7ec3 1217 } else if(receivedCmd[0] == ICLASS_CMD_CHECK) {
1e262141 1218 // Reader random and reader MAC!!!
b67f7ec3 1219 if(simulationMode == MODE_FULLSIM)
61fe9073
MHS		 1220 {
1221 //NR, from reader, is in receivedCmd +1
1222 opt_doTagMAC_2(cipher_state,receivedCmd+1,data_generic_trace,diversified_key);
1223
b19caaef 1224 trace_data = data_generic_trace;
b67f7ec3
MHS		 1225 trace_data_size = 4;
1226 CodeIClassTagAnswer(trace_data , trace_data_size);
1227 memcpy(data_response, ToSend, ToSendMax);
1228 modulated_response = data_response;
1229 modulated_response_size = ToSendMax;
e5cd4ee4 1230 response_delay = 0;//We need to hurry here...
10a8875c 1231 //exitLoop = true;
b67f7ec3
MHS		 1232 }else
1233 { //Not fullsim, we don't respond
f38a1528 1234 // We do not know what to answer, so lets keep quiet
b67f7ec3 1235 modulated_response = resp_sof; modulated_response_size = 0;
55eaed8f
MHS		 1236 trace_data = NULL;
1237 trace_data_size = 0;
b67f7ec3 1238 if (simulationMode == MODE_EXIT_AFTER_MAC){
ff7bb4ef 1239 // dbprintf:ing ...
f5ed4d12 1240 Dbprintf("CSN: %02x %02x %02x %02x %02x %02x %02x %02x"
1241 ,csn[0],csn[1],csn[2],csn[3],csn[4],csn[5],csn[6],csn[7]);
ff7bb4ef 1242 Dbprintf("RDR: (len=%02d): %02x %02x %02x %02x %02x %02x %02x %02x %02x",len,
a501c82b 1243 receivedCmd[0], receivedCmd[1], receivedCmd[2],
ff7bb4ef
MHS		 1244 receivedCmd[3], receivedCmd[4], receivedCmd[5],
1245 receivedCmd[6], receivedCmd[7], receivedCmd[8]);
9f6e9d15
MHS		 1246 if (reader_mac_buf != NULL)
1247 {
1248 memcpy(reader_mac_buf,receivedCmd+1,8);
1249 }
ff7bb4ef
MHS		 1250 exitLoop = true;
1251 }
ff7bb4ef 1252 }
b67f7ec3
MHS		 1253
1254 } else if(receivedCmd[0] == ICLASS_CMD_HALT && len == 1) {
1e262141 1255 // Reader ends the session
b67f7ec3 1256 modulated_response = resp_sof; modulated_response_size = 0; //order = 0;
55eaed8f
MHS		 1257 trace_data = NULL;
1258 trace_data_size = 0;
b67f7ec3
MHS		 1259 } else if(simulationMode == MODE_FULLSIM && receivedCmd[0] == ICLASS_CMD_READ_OR_IDENTIFY && len == 4){
1260 //Read block
1261 uint16_t blk = receivedCmd[1];
c8387e85
MHS		 1262 //Take the data...
1263 memcpy(data_generic_trace, emulator+(blk << 3),8);
1264 //Add crc
1265 AppendCrc(data_generic_trace, 8);
1266 trace_data = data_generic_trace;
1267 trace_data_size = 10;
1268 CodeIClassTagAnswer(trace_data , trace_data_size);
1269 memcpy(data_response, ToSend, ToSendMax);
1270 modulated_response = data_response;
1271 modulated_response_size = ToSendMax;
1272 }else if(receivedCmd[0] == ICLASS_CMD_UPDATE && simulationMode == MODE_FULLSIM)
1273 {//Probably the reader wants to update the nonce. Let's just ignore that for now.
1274 // OBS! If this is implemented, don't forget to regenerate the cipher_state
1275 //We're expected to respond with the data+crc, exactly what's already in the receivedcmd
1276 //receivedcmd is now UPDATE 1b | ADDRESS 1b| DATA 8b| Signature 4b or CRC 2b|
1277
1278 //Take the data...
1279 memcpy(data_generic_trace, receivedCmd+2,8);
1280 //Add crc
1281 AppendCrc(data_generic_trace, 8);
1282 trace_data = data_generic_trace;
1283 trace_data_size = 10;
b67f7ec3
MHS		 1284 CodeIClassTagAnswer(trace_data , trace_data_size);
1285 memcpy(data_response, ToSend, ToSendMax);
1286 modulated_response = data_response;
1287 modulated_response_size = ToSendMax;
1288 }
b19caaef
MHS		 1289 else if(receivedCmd[0] == ICLASS_CMD_PAGESEL)
1290 {//Pagesel
1291 //Pagesel enables to select a page in the selected chip memory and return its configuration block
1292 //Chips with a single page will not answer to this command
1293 // It appears we're fine ignoring this.
1294 //Otherwise, we should answer 8bytes (block) + 2bytes CRC
1295 }
b67f7ec3 1296 else {
17cba269 1297 //#db# Unknown command received from reader (len=5): 26 1 0 f6 a 44 44 44 44
1e262141 1298 // Never seen this command before
1299 Dbprintf("Unknown command received from reader (len=%d): %x %x %x %x %x %x %x %x %x",
1300 len,
1301 receivedCmd[0], receivedCmd[1], receivedCmd[2],
1302 receivedCmd[3], receivedCmd[4], receivedCmd[5],
1303 receivedCmd[6], receivedCmd[7], receivedCmd[8]);
1304 // Do not respond
b67f7ec3 1305 modulated_response = resp_sof; modulated_response_size = 0; //order = 0;
55eaed8f
MHS		 1306 trace_data = NULL;
1307 trace_data_size = 0;
1e262141 1308 }
1309
81012e67
MHS		 1310 if(cmdsRecvd > 100) {
1311 //DbpString("100 commands later...");
9f6e9d15 1312 //break;
1e262141 1313 }
1314 else {
1315 cmdsRecvd++;
1316 }
55eaed8f 1317 /**
6b038d19 1318 A legit tag has about 380us delay between reader EOT and tag SOF.
55eaed8f
MHS		 1319 **/
1320 if(modulated_response_size > 0) {
e5cd4ee4 1321 SendIClassAnswer(modulated_response, modulated_response_size, response_delay);
81012e67 1322 t2r_time = GetCountSspClk();
81cd0474 1323 }
f83cc126 1324
81cd0474 1325 if (tracing) {
a501c82b 1326 uint8_t parity[MAX_PARITY_SIZE];
1327 GetParity(receivedCmd, len, parity);
1328 LogTrace(receivedCmd,len, (r2t_time-time_0)<< 4, (r2t_time-time_0) << 4, parity, TRUE);
17cba269 1329
55eaed8f
MHS		 1330 if (trace_data != NULL) {
1331 GetParity(trace_data, trace_data_size, parity);
1332 LogTrace(trace_data, trace_data_size, (t2r_time-time_0) << 4, (t2r_time-time_0) << 4, parity, FALSE);
17cba269 1333 }
81012e67
MHS		 1334 if(!tracing) {
1335 DbpString("Trace full");
1336 //break;
1337 }
1338
81cd0474 1339 }
81cd0474 1340 }
1e262141 1341
9f6e9d15 1342 //Dbprintf("%x", cmdsRecvd);
1e262141 1343 LED_A_OFF();
1344 LED_B_OFF();
7b941c8d
MHS		 1345 LED_C_OFF();
1346
f83cc126
MHS		 1347 if(buttonPressed)
1348 {
1349 DbpString("Button pressed");
1350 }
f83cc126 1351 return buttonPressed;
1e262141 1352}
1353
1354static int SendIClassAnswer(uint8_t *resp, int respLen, int delay)
1355{
e3dc1e4c 1356 int i = 0, d=0;//, u = 0, d = 0;
1e262141 1357 uint8_t b = 0;
e3dc1e4c 1358
645c960f
MHS		 1359 //FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K);
1360 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K_8BIT);
e3dc1e4c 1361
1e262141 1362 AT91C_BASE_SSC->SSC_THR = 0x00;
1363 FpgaSetupSsc();
e3dc1e4c
MHS		 1364 while(!BUTTON_PRESS()) {
1365 if((AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)){
1366 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1e262141 1367 }
e3dc1e4c
MHS		 1368 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)){
1369 b = 0x00;
1e262141 1370 if(d < delay) {
1e262141 1371 d++;
1372 }
e3dc1e4c
MHS		 1373 else {
1374 if( i < respLen){
1375 b = resp[i];
1376 //Hack
1377 //b = 0xAC;
1378 }
1379 i++;
1e262141 1380 }
1381 AT91C_BASE_SSC->SSC_THR = b;
1e262141 1382 }
e3dc1e4c 1383
645c960f
MHS		 1384// if (i > respLen +4) break;
1385 if (i > respLen +1) break;
1e262141 1386 }
1387
1388 return 0;
1389}
1390
1391/// THE READER CODE
1392
1393//-----------------------------------------------------------------------------
1394// Transmit the command (to the tag) that was placed in ToSend[].
1395//-----------------------------------------------------------------------------
1396static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait)
1397{
1398 int c;
1e262141 1399 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1400 AT91C_BASE_SSC->SSC_THR = 0x00;
1401 FpgaSetupSsc();
1402
1403 if (wait)
f5ed4d12 1404 {
1405 if(*wait < 10) *wait = 10;
2ed270a8 1406
1e262141 1407 for(c = 0; c < *wait;) {
1408 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1409 AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing!
1410 c++;
1411 }
1412 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1413 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1414 (void)r;
1415 }
1416 WDT_HIT();
1417 }
1418
f5ed4d12 1419 }
1420
1421
1e262141 1422 uint8_t sendbyte;
1423 bool firstpart = TRUE;
1424 c = 0;
1425 for(;;) {
1426 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1427
1428 // DOUBLE THE SAMPLES!
1429 if(firstpart) {
1430 sendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4);
1431 }
1432 else {
1433 sendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4);
1434 c++;
1435 }
1436 if(sendbyte == 0xff) {
1437 sendbyte = 0xfe;
1438 }
1439 AT91C_BASE_SSC->SSC_THR = sendbyte;
1440 firstpart = !firstpart;
1441
1442 if(c >= len) {
1443 break;
1444 }
1445 }
1446 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1447 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1448 (void)r;
1449 }
1450 WDT_HIT();
1451 }
1452 if (samples) *samples = (c + *wait) << 3;
1453}
1454
1455
1456//-----------------------------------------------------------------------------
1457// Prepare iClass reader command to send to FPGA
1458//-----------------------------------------------------------------------------
1459void CodeIClassCommand(const uint8_t * cmd, int len)
1460{
1461 int i, j, k;
1462 uint8_t b;
1463
1464 ToSendReset();
1465
1466 // Start of Communication: 1 out of 4
1467 ToSend[++ToSendMax] = 0xf0;
1468 ToSend[++ToSendMax] = 0x00;
1469 ToSend[++ToSendMax] = 0x0f;
1470 ToSend[++ToSendMax] = 0x00;
1471
1472 // Modulate the bytes
1473 for (i = 0; i < len; i++) {
1474 b = cmd[i];
1475 for(j = 0; j < 4; j++) {
1476 for(k = 0; k < 4; k++) {
e3dc1e4c
MHS		 1477 if(k == (b & 3)) {
1478 ToSend[++ToSendMax] = 0x0f;
1479 }
1480 else {
1481 ToSend[++ToSendMax] = 0x00;
1482 }
1e262141 1483 }
1484 b >>= 2;
1485 }
1486 }
1487
1488 // End of Communication
1489 ToSend[++ToSendMax] = 0x00;
1490 ToSend[++ToSendMax] = 0x00;
1491 ToSend[++ToSendMax] = 0xf0;
1492 ToSend[++ToSendMax] = 0x00;
1493
1494 // Convert from last character reference to length
1495 ToSendMax++;
1496}
1497
1498void ReaderTransmitIClass(uint8_t* frame, int len)
1499{
1500 int wait = 0;
1501 int samples = 0;
1e262141 1502
1503 // This is tied to other size changes
1e262141 1504 CodeIClassCommand(frame,len);
1505
1506 // Select the card
1507 TransmitIClassCommand(ToSend, ToSendMax, &samples, &wait);
1508 if(trigger)
1509 LED_A_ON();
1510
1511 // Store reader command in buffer
6a1f2d82 1512 if (tracing) {
a501c82b 1513 uint8_t par[MAX_PARITY_SIZE];
1514 GetParity(frame, len, par);
1515 LogTrace(frame, len, rsamples, rsamples, par, TRUE);
1516 }
1e262141 1517}
1518
1519//-----------------------------------------------------------------------------
1520// Wait a certain time for tag response
1521// If a response is captured return TRUE
1522// If it takes too long return FALSE
1523//-----------------------------------------------------------------------------
1524static int GetIClassAnswer(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed) //uint8_t *buffer
1525{
1526 // buffer needs to be 512 bytes
1527 int c;
1528
1529 // Set FPGA mode to "reader listen mode", no modulation (listen
1530 // only, since we are receiving, not transmitting).
1531 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1532
1533 // Now get the answer from the card
1534 Demod.output = receivedResponse;
1535 Demod.len = 0;
1536 Demod.state = DEMOD_UNSYNCD;
1537
1538 uint8_t b;
1539 if (elapsed) *elapsed = 0;
1540
1541 bool skip = FALSE;
1542
1543 c = 0;
1544 for(;;) {
1545 WDT_HIT();
1546
95e63594 1547 if(BUTTON_PRESS()) return FALSE;
1e262141 1548
1549 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1550 AT91C_BASE_SSC->SSC_THR = 0x00; // To make use of exact timing of next command from reader!!
1551 if (elapsed) (*elapsed)++;
1552 }
1553 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1554 if(c < timeout) { c++; } else { return FALSE; }
1555 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1556 skip = !skip;
1557 if(skip) continue;
95e63594 1558
1e262141 1559 if(ManchesterDecoding(b & 0x0f)) {
1560 *samples = c << 3;
1561 return TRUE;
1562 }
1563 }
1564 }
1565}
1566
1567int ReaderReceiveIClass(uint8_t* receivedAnswer)
1568{
1569 int samples = 0;
1570 if (!GetIClassAnswer(receivedAnswer,160,&samples,0)) return FALSE;
7bc95e2e 1571 rsamples += samples;
6a1f2d82 1572 if (tracing) {
1573 uint8_t parity[MAX_PARITY_SIZE];
1574 GetParity(receivedAnswer, Demod.len, parity);
1575 LogTrace(receivedAnswer,Demod.len,rsamples,rsamples,parity,FALSE);
a501c82b 1576 }
1e262141 1577 if(samples == 0) return FALSE;
1578 return Demod.len;
1579}
1580
f38a1528 1581void setupIclassReader()
1582{
1583 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1584 // Reset trace buffer
3000dc4e
MHS		 1585 set_tracing(TRUE);
1586 clear_trace();
f38a1528 1587
1588 // Setup SSC
1589 FpgaSetupSsc();
1590 // Start from off (no field generated)
1591 // Signal field is off with the appropriate LED
1592 LED_D_OFF();
1593 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1594 SpinDelay(200);
1595
1596 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1597
1598 // Now give it time to spin up.
1599 // Signal field is on with the appropriate LED
1600 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1601 SpinDelay(200);
1602 LED_A_ON();
1603
1604}
1605
e98572a1 1606bool sendCmdGetResponseWithRetries(uint8_t* command, size_t cmdsize, uint8_t* resp, uint8_t expected_size, uint8_t retries)
d3a22c7d 1607{
1608 while(retries-- > 0)
1609 {
1610 ReaderTransmitIClass(command, cmdsize);
1611 if(expected_size == ReaderReceiveIClass(resp)){
e98572a1 1612 return true;
d3a22c7d 1613 }
1614 }
e98572a1 1615 return false;//Error
d3a22c7d 1616}
1617
1618/**
1619 * @brief Talks to an iclass tag, sends the commands to get CSN and CC.
1620 * @param card_data where the CSN and CC are stored for return
1621 * @return 0 = fail
1622 * 1 = Got CSN
1623 * 2 = Got CSN and CC
1624 */
e98572a1 1625uint8_t handshakeIclassTag_ext(uint8_t *card_data, bool use_credit_key)
d3a22c7d 1626{
1627 static uint8_t act_all[] = { 0x0a };
e98572a1 1628 //static uint8_t identify[] = { 0x0c };
1629 static uint8_t identify[] = { 0x0c, 0x00, 0x73, 0x33 };
d3a22c7d 1630 static uint8_t select[] = { 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
e98572a1 1631 static uint8_t readcheck_cc[]= { 0x88, 0x02 };
1632 if (use_credit_key)
1633 readcheck_cc[0] = 0x18;
1634 else
1635 readcheck_cc[0] = 0x88;
caaf9618 1636
f71f4deb 1637 uint8_t resp[ICLASS_BUFFER_SIZE];
d3a22c7d 1638
1639 uint8_t read_status = 0;
1640
1641 // Send act_all
1642 ReaderTransmitIClass(act_all, 1);
1643 // Card present?
1644 if(!ReaderReceiveIClass(resp)) return read_status;//Fail
1645 //Send Identify
1646 ReaderTransmitIClass(identify, 1);
1647 //We expect a 10-byte response here, 8 byte anticollision-CSN and 2 byte CRC
1648 uint8_t len = ReaderReceiveIClass(resp);
1649 if(len != 10) return read_status;//Fail
1650
1651 //Copy the Anti-collision CSN to our select-packet
1652 memcpy(&select[1],resp,8);
1653 //Select the card
1654 ReaderTransmitIClass(select, sizeof(select));
1655 //We expect a 10-byte response here, 8 byte CSN and 2 byte CRC
1656 len = ReaderReceiveIClass(resp);
1657 if(len != 10) return read_status;//Fail
1658
1659 //Success - level 1, we got CSN
1660 //Save CSN in response data
1661 memcpy(card_data,resp,8);
1662
1663 //Flag that we got to at least stage 1, read CSN
1664 read_status = 1;
1665
1666 // Card selected, now read e-purse (cc)
1667 ReaderTransmitIClass(readcheck_cc, sizeof(readcheck_cc));
1668 if(ReaderReceiveIClass(resp) == 8) {
1669 //Save CC (e-purse) in response data
1670 memcpy(card_data+8,resp,8);
caaf9618 1671 read_status++;
d3a22c7d 1672 }
1673
1674 return read_status;
1675}
e98572a1 1676uint8_t handshakeIclassTag(uint8_t *card_data){
1677 return handshakeIclassTag_ext(card_data, false);
1678}
d3a22c7d 1679
caaf9618 1680
1e262141 1681// Reader iClass Anticollission
1682void ReaderIClass(uint8_t arg0) {
f38a1528 1683
83602aff
MHS		 1684 uint8_t card_data[6 * 8]={0};
1685 memset(card_data, 0xFF, sizeof(card_data));
f38a1528 1686 uint8_t last_csn[8]={0};
6a1f2d82 1687
caaf9618
MHS		 1688 //Read conf block CRC(0x01) => 0xfa 0x22
1689 uint8_t readConf[] = { ICLASS_CMD_READ_OR_IDENTIFY,0x01, 0xfa, 0x22};
1690 //Read conf block CRC(0x05) => 0xde 0x64
1691 uint8_t readAA[] = { ICLASS_CMD_READ_OR_IDENTIFY,0x05, 0xde, 0x64};
1692
1693
f38a1528 1694 int read_status= 0;
caaf9618 1695 uint8_t result_status = 0;
f38a1528 1696 bool abort_after_read = arg0 & FLAG_ICLASS_READER_ONLY_ONCE;
8949bb5d 1697 bool try_once = arg0 & FLAG_ICLASS_READER_ONE_TRY;
e98572a1 1698 bool use_credit_key = false;
1699 if (arg0 & FLAG_ICLASS_READER_CEDITKEY)
1700 use_credit_key = true;
3000dc4e 1701 set_tracing(TRUE);
f38a1528 1702 setupIclassReader();
1703
8949bb5d 1704 uint16_t tryCnt=0;
f38a1528 1705 while(!BUTTON_PRESS())
1706 {
8949bb5d 1707 if (try_once && tryCnt > 5) break;
1708 tryCnt++;
3000dc4e 1709 if(!tracing) {
d3a22c7d 1710 DbpString("Trace full");
1711 break;
1712 }
c8dd9b09 1713 WDT_HIT();
f38a1528 1714
e98572a1 1715 read_status = handshakeIclassTag_ext(card_data, use_credit_key);
d3a22c7d 1716
1717 if(read_status == 0) continue;
caaf9618
MHS		 1718 if(read_status == 1) result_status = FLAG_ICLASS_READER_CSN;
1719 if(read_status == 2) result_status = FLAG_ICLASS_READER_CSN|FLAG_ICLASS_READER_CC;
1720
1721 // handshakeIclass returns CSN|CC, but the actual block
1722 // layout is CSN|CONFIG|CC, so here we reorder the data,
1723 // moving CC forward 8 bytes
1724 memcpy(card_data+16,card_data+8, 8);
1725 //Read block 1, config
1726 if(arg0 & FLAG_ICLASS_READER_CONF)
1727 {
1728 if(sendCmdGetResponseWithRetries(readConf, sizeof(readConf),card_data+8, 10, 10))
caaf9618
MHS		 1729 {
1730 result_status |= FLAG_ICLASS_READER_CONF;
e98572a1 1731 } else {
1732 Dbprintf("Failed to dump config block");
caaf9618
MHS		 1733 }
1734 }
f38a1528 1735
caaf9618
MHS		 1736 //Read block 5, AA
1737 if(arg0 & FLAG_ICLASS_READER_AA){
1738 if(sendCmdGetResponseWithRetries(readAA, sizeof(readAA),card_data+(8*4), 10, 10))
1739 {
caaf9618 1740 result_status |= FLAG_ICLASS_READER_AA;
e98572a1 1741 } else {
1742 //Dbprintf("Failed to dump AA block");
caaf9618
MHS		 1743 }
1744 }
1745
1746 // 0 : CSN
b67f7ec3 1747 // 1 : Configuration
caaf9618
MHS		 1748 // 2 : e-purse
1749 // (3,4 write-only, kc and kd)
b67f7ec3
MHS		 1750 // 5 Application issuer area
1751 //
1752 //Then we can 'ship' back the 8 * 5 bytes of data,
1753 // with 0xFF:s in block 3 and 4.
1754
f38a1528 1755 LED_B_ON();
1756 //Send back to client, but don't bother if we already sent this
1757 if(memcmp(last_csn, card_data, 8) != 0)
d3a22c7d 1758 {
caaf9618
MHS		 1759 // If caller requires that we get CC, continue until we got it
1760 if( (arg0 & read_status & FLAG_ICLASS_READER_CC) || !(arg0 & FLAG_ICLASS_READER_CC))
d3a22c7d 1761 {
caaf9618 1762 cmd_send(CMD_ACK,result_status,0,0,card_data,sizeof(card_data));
d3a22c7d 1763 if(abort_after_read) {
1764 LED_A_OFF();
5ee53a0e 1765 set_tracing(FALSE);
d3a22c7d 1766 return;
1767 }
5ee53a0e 1768 //Save that we already sent this....
1769 memcpy(last_csn, card_data, 8);
d3a22c7d 1770 }
d3a22c7d 1771 }
c8dd9b09 1772 LED_B_OFF();
f38a1528 1773 }
d3a22c7d 1774 cmd_send(CMD_ACK,0,0,0,card_data, 0);
aa41c605 1775 LED_A_OFF();
5ee53a0e 1776 set_tracing(FALSE);
f38a1528 1777}
1778
1779void ReaderIClass_Replay(uint8_t arg0, uint8_t *MAC) {
d3a22c7d 1780
14edfd09 1781 uint8_t card_data[USB_CMD_DATA_SIZE]={0};
d3a22c7d 1782 uint16_t block_crc_LUT[255] = {0};
1783
1784 {//Generate a lookup table for block crc
1785 for(int block = 0; block < 255; block++){
1786 char bl = block;
1787 block_crc_LUT[block] = iclass_crc16(&bl ,1);
1788 }
1789 }
1790 //Dbprintf("Lookup table: %02x %02x %02x" ,block_crc_LUT[0],block_crc_LUT[1],block_crc_LUT[2]);
1791
f38a1528 1792 uint8_t check[] = { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1793 uint8_t read[] = { 0x0c, 0x00, 0x00, 0x00 };
1794
fecd8202 1795 uint16_t crc = 0;
f38a1528 1796 uint8_t cardsize=0;
f38a1528 1797 uint8_t mem=0;
1798
1799 static struct memory_t{
1800 int k16;
1801 int book;
1802 int k2;
1803 int lockauth;
1804 int keyaccess;
1805 } memory;
1806
f71f4deb 1807 uint8_t resp[ICLASS_BUFFER_SIZE];
6a1f2d82 1808
f38a1528 1809 setupIclassReader();
3000dc4e 1810 set_tracing(TRUE);
f38a1528 1811
d3a22c7d 1812 while(!BUTTON_PRESS()) {
1813
1814 WDT_HIT();
39d3ce5d 1815
3000dc4e 1816 if(!tracing) {
f38a1528 1817 DbpString("Trace full");
1818 break;
1819 }
1820
d3a22c7d 1821 uint8_t read_status = handshakeIclassTag(card_data);
1822 if(read_status < 2) continue;
1823
5ee53a0e 1824 //for now replay captured auth (as cc not updated)
1825 memcpy(check+5,MAC,4);
d3a22c7d 1826
e98572a1 1827 if(!sendCmdGetResponseWithRetries(check, sizeof(check),resp, 4, 5))
d3a22c7d 1828 {
5ee53a0e 1829 Dbprintf("Error: Authentication Fail!");
d3a22c7d 1830 continue;
5ee53a0e 1831 }
d3a22c7d 1832
1833 //first get configuration block (block 1)
1834 crc = block_crc_LUT[1];
5ee53a0e 1835 read[1]=1;
1836 read[2] = crc >> 8;
1837 read[3] = crc & 0xff;
d3a22c7d 1838
e98572a1 1839 if(!sendCmdGetResponseWithRetries(read, sizeof(read),resp, 10, 10))
d3a22c7d 1840 {
1841 Dbprintf("Dump config (block 1) failed");
1842 continue;
1843 }
1844
5ee53a0e 1845 mem=resp[5];
1846 memory.k16= (mem & 0x80);
1847 memory.book= (mem & 0x20);
1848 memory.k2= (mem & 0x8);
1849 memory.lockauth= (mem & 0x2);
1850 memory.keyaccess= (mem & 0x1);
f38a1528 1851
d3a22c7d 1852 cardsize = memory.k16 ? 255 : 32;
1853 WDT_HIT();
14edfd09 1854 //Set card_data to all zeroes, we'll fill it with data
1855 memset(card_data,0x0,USB_CMD_DATA_SIZE);
1856 uint8_t failedRead =0;
428d6221 1857 uint32_t stored_data_length =0;
f38a1528 1858 //then loop around remaining blocks
d3a22c7d 1859 for(int block=0; block < cardsize; block++){
1860
1861 read[1]= block;
1862 crc = block_crc_LUT[block];
5ee53a0e 1863 read[2] = crc >> 8;
1864 read[3] = crc & 0xff;
d3a22c7d 1865
e98572a1 1866 if(sendCmdGetResponseWithRetries(read, sizeof(read), resp, 10, 10))
d3a22c7d 1867 {
5ee53a0e 1868 Dbprintf(" %02x: %02x %02x %02x %02x %02x %02x %02x %02x",
1869 block, resp[0], resp[1], resp[2],
1870 resp[3], resp[4], resp[5],
1871 resp[6], resp[7]);
d3a22c7d 1872
14edfd09 1873 //Fill up the buffer
1874 memcpy(card_data+stored_data_length,resp,8);
1875 stored_data_length += 8;
14edfd09 1876 if(stored_data_length +8 > USB_CMD_DATA_SIZE)
1877 {//Time to send this off and start afresh
1878 cmd_send(CMD_ACK,
1879 stored_data_length,//data length
1880 failedRead,//Failed blocks?
1881 0,//Not used ATM
1882 card_data, stored_data_length);
1883 //reset
1884 stored_data_length = 0;
1885 failedRead = 0;
1886 }
5ee53a0e 1887 } else {
14edfd09 1888 failedRead = 1;
1889 stored_data_length +=8;//Otherwise, data becomes misaligned
d3a22c7d 1890 Dbprintf("Failed to dump block %d", block);
f38a1528 1891 }
1892 }
428d6221 1893
14edfd09 1894 //Send off any remaining data
1895 if(stored_data_length > 0)
1896 {
1897 cmd_send(CMD_ACK,
1898 stored_data_length,//data length
1899 failedRead,//Failed blocks?
1900 0,//Not used ATM
1901 card_data, stored_data_length);
1902 }
d3a22c7d 1903 //If we got here, let's break
1904 break;
f38a1528 1905 }
14edfd09 1906 //Signal end of transmission
1907 cmd_send(CMD_ACK,
1908 0,//data length
1909 0,//Failed blocks?
1910 0,//Not used ATM
1911 card_data, 0);
1912
f38a1528 1913 LED_A_OFF();
5ee53a0e 1914 set_tracing(FALSE);
f38a1528 1915}
1916
e98572a1 1917void iClass_ReadCheck(uint8_t blockNo, uint8_t keyType) {
1918 uint8_t readcheck[] = { keyType, blockNo };
1919 uint8_t resp[] = {0,0,0,0,0,0,0,0};
1920 size_t isOK = 0;
1921 isOK = sendCmdGetResponseWithRetries(readcheck, sizeof(readcheck), resp, sizeof(resp), 6);
1922 cmd_send(CMD_ACK,isOK,0,0,0,0);
1923}
1e262141 1924
e98572a1 1925void iClass_Authentication(uint8_t *MAC) {
1926 uint8_t check[] = { ICLASS_CMD_CHECK, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1927 uint8_t resp[ICLASS_BUFFER_SIZE];
1928 memcpy(check+5,MAC,4);
1929 bool isOK;
1930 isOK = sendCmdGetResponseWithRetries(check, sizeof(check), resp, 4, 6);
1931 cmd_send(CMD_ACK,isOK,0,0,0,0);
1932}
1933bool iClass_ReadBlock(uint8_t blockNo, uint8_t *readdata) {
1934 uint8_t readcmd[] = {ICLASS_CMD_READ_OR_IDENTIFY, blockNo, 0x00, 0x00}; //0x88, 0x00 // can i use 0C?
1935 char bl = blockNo;
1936 uint16_t rdCrc = iclass_crc16(&bl, 1);
1937 readcmd[2] = rdCrc >> 8;
1938 readcmd[3] = rdCrc & 0xff;
1939 uint8_t resp[] = {0,0,0,0,0,0,0,0,0,0};
1940 bool isOK = false;
1941
1942 //readcmd[1] = blockNo;
1943 isOK = sendCmdGetResponseWithRetries(readcmd, sizeof(readcmd), resp, 10, 10);
1944 memcpy(readdata, resp, sizeof(resp));
1945
1946 return isOK;
1947}
1e262141 1948
e98572a1 1949void iClass_ReadBlk(uint8_t blockno) {
1950 uint8_t readblockdata[] = {0,0,0,0,0,0,0,0,0,0};
1951 bool isOK = false;
1952 isOK = iClass_ReadBlock(blockno, readblockdata);
1953 cmd_send(CMD_ACK, isOK, 0, 0, readblockdata, 8);
1954}
1e262141 1955
e98572a1 1956void iClass_Dump(uint8_t blockno, uint8_t numblks) {
1957 uint8_t readblockdata[] = {0,0,0,0,0,0,0,0,0,0};
1958 bool isOK = false;
1959 uint8_t blkCnt = 0;
1e262141 1960
e98572a1 1961 BigBuf_free();
1962 uint8_t *dataout = BigBuf_malloc(255*8);
1963 if (dataout == NULL){
1964 Dbprintf("out of memory");
1965 OnError(1);
1966 return;
1967 }
1968 memset(dataout,0xFF,255*8);
1969
1970 for (;blkCnt < numblks; blkCnt++) {
1971 isOK = iClass_ReadBlock(blockno+blkCnt, readblockdata);
1972 if (!isOK || (readblockdata[0] == 0xBB || readblockdata[7] == 0xBB || readblockdata[2] == 0xBB)) { //try again
1973 isOK = iClass_ReadBlock(blockno+blkCnt, readblockdata);
1974 if (!isOK) {
1975 Dbprintf("Block %02X failed to read", blkCnt+blockno);
4ab4336a 1976 break;
1977 }
e98572a1 1978 }
1979 memcpy(dataout+(blkCnt*8),readblockdata,8);
1980 }
1981 //return pointer to dump memory in arg3
1982 cmd_send(CMD_ACK,isOK,blkCnt,BigBuf_max_traceLen(),0,0);
1983 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1984 LEDsoff();
1985 BigBuf_free();
1986}
1987
1988bool iClass_WriteBlock_ext(uint8_t blockNo, uint8_t *data) {
1989 uint8_t write[] = { ICLASS_CMD_UPDATE, blockNo, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1990 //uint8_t readblockdata[10];
1991 //write[1] = blockNo;
1992 memcpy(write+2, data, 12); // data + mac
1993 uint8_t resp[] = {0,0,0,0,0,0,0,0,0,0};
1994 bool isOK;
1995 isOK = sendCmdGetResponseWithRetries(write,sizeof(write),resp,sizeof(resp),10);
1996 if (isOK) {
1997 //Dbprintf("WriteResp: %02X%02X%02X%02X%02X%02X%02X%02X%02X%02X",resp[0],resp[1],resp[2],resp[3],resp[4],resp[5],resp[6],resp[7],resp[8],resp[9]);
1998 if (memcmp(write+2,resp,8)) {
1999 //error try again
2000 isOK = sendCmdGetResponseWithRetries(write,sizeof(write),resp,sizeof(resp),10);
2001 }
2002 }
2003 return isOK;
2004}
2005
2006void iClass_WriteBlock(uint8_t blockNo, uint8_t *data) {
2007 bool isOK = iClass_WriteBlock_ext(blockNo, data);
2008 if (isOK){
2009 Dbprintf("Write block [%02x] successful",blockNo);
f38a1528 2010 }else {
e98572a1 2011 Dbprintf("Write block [%02x] failed",blockNo);
2012 }
2013 cmd_send(CMD_ACK,isOK,0,0,0,0);
2014}
f38a1528 2015
e98572a1 2016void iClass_Clone(uint8_t startblock, uint8_t endblock, uint8_t *data) {
2017 int i;
2018 int written = 0;
2019 int total_block = (endblock - startblock) + 1;
2020 for (i = 0; i < total_block;i++){
2021 // block number
2022 if (iClass_WriteBlock_ext(i+startblock, data+(i*12))){
2023 Dbprintf("Write block [%02x] successful",i + startblock);
2024 written++;
2025 } else {
2026 if (iClass_WriteBlock_ext(i+startblock, data+(i*12))){
2027 Dbprintf("Write block [%02x] successful",i + startblock);
2028 written++;
2029 } else {
2030 Dbprintf("Write block [%02x] failed",i + startblock);
2031 }
1e262141 2032 }
1e262141 2033 }
e98572a1 2034 if (written == total_block)
2035 Dbprintf("Clone complete");
2036 else
2037 Dbprintf("Clone incomplete");
2038
2039 cmd_send(CMD_ACK,1,0,0,0,0);
2040 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2041 LEDsoff();
2042}
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