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Add make targets for flashing (Windows version untested)
[proxmark3-svn] / bootrom / bootrom.c
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6658905f 1#include <proxmark3.h>\r
2\r
8fcbf652 3struct common_area common_area __attribute__((section(".commonarea")));\r
4unsigned int start_addr, end_addr, bootrom_unlocked; \r
5extern char _bootrom_start, _bootrom_end, _flash_start, _flash_end;\r
6\r
6658905f 7static void ConfigClocks(void)\r
8{\r
9 // we are using a 16 MHz crystal as the basis for everything\r
10 // slow clock runs at 32Khz typical regardless of crystal\r
11\r
12 // enable system clock and USB clock\r
13 PMC_SYS_CLK_ENABLE = PMC_SYS_CLK_PROCESSOR_CLK | PMC_SYS_CLK_UDP_CLK;\r
14\r
15 // enable the clock to the following peripherals\r
16 PMC_PERIPHERAL_CLK_ENABLE =\r
17 (1<<PERIPH_PIOA) |\r
18 (1<<PERIPH_ADC) |\r
19 (1<<PERIPH_SPI) |\r
20 (1<<PERIPH_SSC) |\r
21 (1<<PERIPH_PWMC) |\r
22 (1<<PERIPH_UDP);\r
23\r
24 // worst case scenario, with 16Mhz xtal startup delay is 14.5ms\r
25 // with a slow clock running at it worst case (max) frequency of 42khz\r
26 // max startup delay = (14.5ms*42k)/8 = 76 = 0x4C round up to 0x50\r
27\r
28 // enable main oscillator and set startup delay\r
29 PMC_MAIN_OSCILLATOR = PMC_MAIN_OSCILLATOR_ENABLE |\r
30 PMC_MAIN_OSCILLATOR_STARTUP_DELAY(0x50);\r
31\r
32 // wait for main oscillator to stabilize\r
33 while ( !(PMC_INTERRUPT_STATUS & PMC_MAIN_OSCILLATOR_STABILIZED) )\r
34 ;\r
35\r
36 // minimum PLL clock frequency is 80 MHz in range 00 (96 here so okay)\r
37 // frequency is crystal * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz\r
38 PMC_PLL = PMC_PLL_DIVISOR(2) | PMC_PLL_COUNT_BEFORE_LOCK(0x50) |\r
39 PMC_PLL_FREQUENCY_RANGE(0) | PMC_PLL_MULTIPLIER(12) |\r
40 PMC_PLL_USB_DIVISOR(1);\r
41\r
42 // wait for PLL to lock\r
43 while ( !(PMC_INTERRUPT_STATUS & PMC_MAIN_OSCILLATOR_PLL_LOCK) )\r
44 ;\r
45\r
46 // we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz\r
47 // as per datasheet, this register must be programmed in two operations\r
48 // when changing to PLL, program the prescaler first then the source\r
49 PMC_MASTER_CLK = PMC_CLK_PRESCALE_DIV_2;\r
50\r
51 // wait for main clock ready signal\r
52 while ( !(PMC_INTERRUPT_STATUS & PMC_MAIN_OSCILLATOR_MCK_READY) )\r
53 ;\r
54\r
55 // set the source to PLL\r
56 PMC_MASTER_CLK = PMC_CLK_SELECTION_PLL_CLOCK | PMC_CLK_PRESCALE_DIV_2;\r
57\r
58 // wait for main clock ready signal\r
59 while ( !(PMC_INTERRUPT_STATUS & PMC_MAIN_OSCILLATOR_MCK_READY) )\r
60 ;\r
61}\r
62\r
63static void Fatal(void)\r
64{\r
65 for(;;);\r
66}\r
67\r
68void UsbPacketReceived(BYTE *packet, int len)\r
69{\r
8fcbf652 70 int i, dont_ack=0;\r
6658905f 71 UsbCommand *c = (UsbCommand *)packet;\r
72 volatile DWORD *p;\r
73\r
74 if(len != sizeof(*c)) {\r
75 Fatal();\r
76 }\r
77\r
78 switch(c->cmd) {\r
79 case CMD_DEVICE_INFO:\r
8fcbf652 80 dont_ack = 1;\r
81 c->cmd = CMD_DEVICE_INFO;\r
82 c->ext1 = DEVICE_INFO_FLAG_BOOTROM_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM | \r
83 DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH;\r
84 if(common_area.flags.osimage_present) c->ext1 |= DEVICE_INFO_FLAG_OSIMAGE_PRESENT;\r
85 UsbSendPacket(packet, len);\r
6658905f 86 break;\r
87\r
88 case CMD_SETUP_WRITE:\r
8fcbf652 89 /* The temporary write buffer of the embedded flash controller is mapped to the\r
90 * whole memory region, only the last 8 bits are decoded.
91 */\r
92 p = (volatile DWORD *)&_flash_start;\r
6658905f 93 for(i = 0; i < 12; i++) {\r
94 p[i+c->ext1] = c->d.asDwords[i];\r
95 }\r
96 break;\r
97\r
98 case CMD_FINISH_WRITE:\r
8fcbf652 99 p = (volatile DWORD *)&_flash_start;\r
6658905f 100 for(i = 0; i < 4; i++) {\r
101 p[i+60] = c->d.asDwords[i];\r
102 }\r
103\r
8fcbf652 104 /* Check that the address that we are supposed to write to is within our allowed region */\r
105 if( ((c->ext1+FLASH_PAGE_SIZE_BYTES-1) >= end_addr) || (c->ext1 < start_addr) ) {\r
106 /* Disallow write */\r
107 dont_ack = 1;\r
108 c->cmd = CMD_NACK;\r
109 UsbSendPacket(packet, len);\r
110 } else {\r
111 /* Translate address to flash page and do flash, update here for the 512k part */\r
112 MC_FLASH_COMMAND = MC_FLASH_COMMAND_KEY |\r
113 MC_FLASH_COMMAND_PAGEN((c->ext1-(int)&_flash_start)/FLASH_PAGE_SIZE_BYTES) |\r
114 FCMD_WRITE_PAGE;\r
115 }\r
6658905f 116 while(!(MC_FLASH_STATUS & MC_FLASH_STATUS_READY))\r
117 ;\r
118 break;\r
119\r
120 case CMD_HARDWARE_RESET:\r
8fcbf652 121 USB_D_PLUS_PULLUP_OFF();\r
122 RSTC_CONTROL = RST_CONTROL_KEY | RST_CONTROL_PROCESSOR_RESET;\r
6658905f 123 break;\r
8fcbf652 124 \r
125 case CMD_START_FLASH:\r
126 if(c->ext3 == START_FLASH_MAGIC) bootrom_unlocked = 1;\r
127 else bootrom_unlocked = 0;\r
128 {\r
129 int prot_start = (int)&_bootrom_start;\r
130 int prot_end = (int)&_bootrom_end;\r
131 int allow_start = (int)&_flash_start;\r
132 int allow_end = (int)&_flash_end;\r
133 int cmd_start = c->ext1;\r
134 int cmd_end = c->ext2;\r
135 \r
136 /* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected\r
137 * bootrom area. In any case they must be within the flash area.
138 */\r
139 if( (bootrom_unlocked || ((cmd_start >= prot_end) || (cmd_end < prot_start)))\r
140 && (cmd_start >= allow_start) && (cmd_end <= allow_end) ) {\r
141 start_addr = cmd_start;\r
142 end_addr = cmd_end;\r
143 } else {\r
144 start_addr = end_addr = 0;\r
145 dont_ack = 1;\r
146 c->cmd = CMD_NACK;\r
147 UsbSendPacket(packet, len);\r
148 }\r
149 }\r
150 break;\r
151 \r
6658905f 152 default:\r
153 Fatal();\r
154 break;\r
155 }\r
156\r
8fcbf652 157 if(!dont_ack) {\r
158 c->cmd = CMD_ACK;\r
159 UsbSendPacket(packet, len);\r
160 }\r
161}\r
162\r
163static void flash_mode(int externally_entered)\r
164{\r
165 start_addr = 0;\r
166 end_addr = 0;\r
167 bootrom_unlocked = 0;\r
168 \r
169 UsbStart();\r
170 for(;;) {\r
171 WDT_HIT();\r
172 \r
173 UsbPoll(TRUE);\r
174 \r
175 if(!externally_entered && !BUTTON_PRESS()) {\r
176 /* Perform a reset to leave flash mode */\r
177 USB_D_PLUS_PULLUP_OFF();\r
178 LED_B_ON();\r
179 RSTC_CONTROL = RST_CONTROL_KEY | RST_CONTROL_PROCESSOR_RESET;\r
180 for(;;);\r
181 }\r
182 if(externally_entered && BUTTON_PRESS()) {\r
183 /* Let the user's button press override the automatic leave */\r
184 externally_entered = 0;\r
185 }\r
186 }\r
6658905f 187}\r
188\r
e3ae0257 189extern char _osimage_entry;\r
6658905f 190void BootROM(void)\r
191{\r
192 //------------\r
193 // First set up all the I/O pins; GPIOs configured directly, other ones\r
194 // just need to be assigned to the appropriate peripheral.\r
195\r
196 // Kill all the pullups, especially the one on USB D+; leave them for\r
197 // the unused pins, though.\r
198 PIO_NO_PULL_UP_ENABLE = (1 << GPIO_USB_PU) |\r
199 (1 << GPIO_LED_A) |\r
200 (1 << GPIO_LED_B) |\r
201 (1 << GPIO_LED_C) |\r
202 (1 << GPIO_LED_D) |\r
203 (1 << GPIO_FPGA_DIN) |\r
204 (1 << GPIO_FPGA_DOUT) |\r
205 (1 << GPIO_FPGA_CCLK) |\r
206 (1 << GPIO_FPGA_NINIT) |\r
207 (1 << GPIO_FPGA_NPROGRAM) |\r
208 (1 << GPIO_FPGA_DONE) |\r
209 (1 << GPIO_MUXSEL_HIPKD) |\r
210 (1 << GPIO_MUXSEL_HIRAW) |\r
211 (1 << GPIO_MUXSEL_LOPKD) |\r
212 (1 << GPIO_MUXSEL_LORAW) |\r
213 (1 << GPIO_RELAY) |\r
214 (1 << GPIO_NVDD_ON);\r
215 // (and add GPIO_FPGA_ON)\r
216 // These pins are outputs\r
217 PIO_OUTPUT_ENABLE = (1 << GPIO_LED_A) |\r
218 (1 << GPIO_LED_B) |\r
219 (1 << GPIO_LED_C) |\r
220 (1 << GPIO_LED_D) |\r
221 (1 << GPIO_RELAY) |\r
222 (1 << GPIO_NVDD_ON);\r
223 // PIO controls the following pins\r
224 PIO_ENABLE = (1 << GPIO_USB_PU) |\r
225 (1 << GPIO_LED_A) |\r
226 (1 << GPIO_LED_B) |\r
227 (1 << GPIO_LED_C) |\r
228 (1 << GPIO_LED_D);\r
229\r
230 USB_D_PLUS_PULLUP_OFF();\r
231 LED_D_OFF();\r
232 LED_C_ON();\r
233 LED_B_OFF();\r
234 LED_A_OFF();\r
8fcbf652 235 \r
236 // if 512K FLASH part - TODO make some defines :)\r
237 if ((DBGU_CIDR | 0xf00) == 0xa00) {\r
238 MC_FLASH_MODE0 = MC_FLASH_MODE_FLASH_WAIT_STATES(1) |\r
239 MC_FLASH_MODE_MASTER_CLK_IN_MHZ(0x48);\r
240 MC_FLASH_MODE1 = MC_FLASH_MODE_FLASH_WAIT_STATES(1) |\r
241 MC_FLASH_MODE_MASTER_CLK_IN_MHZ(0x48);\r
242 } else {\r
243 MC_FLASH_MODE0 = MC_FLASH_MODE_FLASH_WAIT_STATES(0) |\r
244 MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);\r
245 }\r
246 \r
247 // Initialize all system clocks\r
6658905f 248 ConfigClocks();\r
8fcbf652 249 \r
6658905f 250 LED_A_ON();\r
8fcbf652 251 \r
252 int common_area_present = 0;\r
253 switch(RSTC_STATUS & RST_STATUS_TYPE_MASK) {\r
254 case RST_STATUS_TYPE_WATCHDOG:\r
255 case RST_STATUS_TYPE_SOFTWARE:\r
256 case RST_STATUS_TYPE_USER:\r
257 /* In these cases the common_area in RAM should be ok, retain it if it's there */\r
258 if(common_area.magic == COMMON_AREA_MAGIC && common_area.version == 1) {\r
259 common_area_present = 1;\r
260 }\r
261 break;\r
262 default: /* Otherwise, initialize it from scratch */\r
263 break;\r
264 }\r
265 \r
266 if(!common_area_present){\r
267 /* Common area not ok, initialize it */\r
268 int i; for(i=0; i<sizeof(common_area); i++) { /* Makeshift memset, no need to drag util.c into this */\r
269 ((char*)&common_area)[i] = 0;\r
270 }\r
271 common_area.magic = COMMON_AREA_MAGIC;\r
272 common_area.version = 1;\r
273 common_area.flags.bootrom_present = 1;\r
274 }\r
275 \r
276 common_area.flags.bootrom_present = 1;\r
277 if(common_area.command == COMMON_AREA_COMMAND_ENTER_FLASH_MODE) {\r
278 common_area.command = COMMON_AREA_COMMAND_NONE;\r
279 flash_mode(1);\r
280 } else if(BUTTON_PRESS()) {\r
281 flash_mode(0);\r
282 } else {\r
283 // jump to Flash address of the osimage entry point (LSBit set for thumb mode)\r
284 asm("bx %0\n" : : "r" ( ((int)&_osimage_entry) | 0x1 ) );\r
6658905f 285 }\r
286}\r
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