]> cvs.zerfleddert.de Git - proxmark3-svn/blame - armsrc/lfops.c
projects / proxmark3-svn / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Add generic CRC calculation code
[proxmark3-svn] / armsrc / lfops.c
CommitLineData
9bea179a 1//-----------------------------------------------------------------------------\r
2// Miscellaneous routines for low frequency tag operations.\r
3// Tags supported here so far are Texas Instruments (TI), HID\r
4// Also routines for raw mode reading/simulating of LF waveform\r
5//\r
6//-----------------------------------------------------------------------------\r
7#include <proxmark3.h>\r
8#include "apps.h"\r
0fa9ca5b 9#include "hitag2.h"\r
9bea179a 10#include "../common/crc16.c"\r
11\r
12void AcquireRawAdcSamples125k(BOOL at134khz)\r
13{\r
14 if(at134khz) {\r
15 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
16 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
17 } else {\r
18 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
19 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
20 }\r
21\r
22 // Connect the A/D to the peak-detected low-frequency path.\r
23 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
24\r
25 // Give it a bit of time for the resonant antenna to settle.\r
26 SpinDelay(50);\r
27\r
28 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
29 FpgaSetupSsc();\r
30\r
31 // Now call the acquisition routine\r
32 DoAcquisition125k(at134khz);\r
33}\r
34\r
35// split into two routines so we can avoid timing issues after sending commands //\r
36void DoAcquisition125k(BOOL at134khz)\r
37{\r
38 BYTE *dest = (BYTE *)BigBuf;\r
39 int n = sizeof(BigBuf);\r
40 int i;\r
41\r
42 memset(dest,0,n);\r
43 i = 0;\r
44 for(;;) {\r
6949aca9 45 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
46 AT91C_BASE_SSC->SSC_THR = 0x43;\r
9bea179a 47 LED_D_ON();\r
48 }\r
6949aca9 49 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
50 dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
9bea179a 51 i++;\r
52 LED_D_OFF();\r
53 if(i >= n) {\r
54 break;\r
55 }\r
56 }\r
57 }\r
58 DbpIntegers(dest[0], dest[1], at134khz);\r
59}\r
60\r
61void ModThenAcquireRawAdcSamples125k(int delay_off,int period_0,int period_1,BYTE *command)\r
62{\r
63 BOOL at134khz;\r
64\r
0fa9ca5b 65 /* Make sure the tag is reset */\r
66 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
67 SpinDelay(2500);\r
68 \r
9bea179a 69 // see if 'h' was specified\r
70 if(command[strlen((char *) command) - 1] == 'h')\r
71 at134khz= TRUE;\r
72 else\r
73 at134khz= FALSE;\r
74\r
75 if(at134khz) {\r
76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
77 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
78 } else {\r
79 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
80 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
81 }\r
82\r
83 // Give it a bit of time for the resonant antenna to settle.\r
84 SpinDelay(50);\r
0fa9ca5b 85 // And a little more time for the tag to fully power up\r
86 SpinDelay(2000);\r
9bea179a 87\r
88 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
89 FpgaSetupSsc();\r
90\r
91 // now modulate the reader field\r
92 while(*command != '\0' && *command != ' ')\r
93 {\r
94 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
95 LED_D_OFF();\r
96 SpinDelayUs(delay_off);\r
97 if(at134khz) {\r
98 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
99 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
100 } else {\r
101 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
102 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
103 }\r
104 LED_D_ON();\r
0fa9ca5b 105 if(*(command++) == '0') {\r
9bea179a 106 SpinDelayUs(period_0);\r
0fa9ca5b 107 } else {\r
9bea179a 108 SpinDelayUs(period_1);\r
109 }\r
0fa9ca5b 110 }\r
9bea179a 111 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
112 LED_D_OFF();\r
113 SpinDelayUs(delay_off);\r
114 if(at134khz) {\r
115 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
116 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
117 } else {\r
118 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
120 }\r
121\r
122 // now do the read\r
123 DoAcquisition125k(at134khz);\r
124}\r
125\r
7381e8f2 126/* blank r/w tag data stream\r
127...0000000000000000 01111111\r
1281010101010101010101010101010101010101010101010101010101010101010\r
1290011010010100001\r
13001111111\r
131101010101010101[0]000...\r
132\r
133[5555fe852c5555555555555555fe0000]\r
134*/\r
135void ReadTItag()\r
136{\r
137 // some hardcoded initial params\r
138 // when we read a TI tag we sample the zerocross line at 2Mhz\r
139 // TI tags modulate a 1 as 16 cycles of 123.2Khz\r
140 // TI tags modulate a 0 as 16 cycles of 134.2Khz\r
141 #define FSAMPLE 2000000\r
142 #define FREQLO 123200\r
143 #define FREQHI 134200\r
144\r
145 signed char *dest = (signed char *)BigBuf;\r
146 int n = sizeof(BigBuf);\r
147// int *dest = GraphBuffer;\r
148// int n = GraphTraceLen;\r
149\r
150 // 128 bit shift register [shift3:shift2:shift1:shift0]\r
151 DWORD shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;\r
152\r
153 int i, cycles=0, samples=0;\r
154 // how many sample points fit in 16 cycles of each frequency\r
155 DWORD sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;\r
156 // when to tell if we're close enough to one freq or another\r
157 DWORD threshold = (sampleslo - sampleshi + 1)>>1;\r
158\r
159 // TI tags charge at 134.2Khz\r
160 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
161\r
162 // Place FPGA in passthrough mode, in this mode the CROSS_LO line\r
163 // connects to SSP_DIN and the SSP_DOUT logic level controls\r
164 // whether we're modulating the antenna (high)\r
165 // or listening to the antenna (low)\r
166 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r
167\r
168 // get TI tag data into the buffer\r
169 AcquireTiType();\r
170\r
171 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
172\r
173 for (i=0; i<n-1; i++) {\r
174 // count cycles by looking for lo to hi zero crossings\r
175 if ( (dest[i]<0) && (dest[i+1]>0) ) {\r
176 cycles++;\r
177 // after 16 cycles, measure the frequency\r
178 if (cycles>15) {\r
179 cycles=0;\r
180 samples=i-samples; // number of samples in these 16 cycles\r
181\r
182 // TI bits are coming to us lsb first so shift them\r
183 // right through our 128 bit right shift register\r
184 shift0 = (shift0>>1) | (shift1 << 31);\r
185 shift1 = (shift1>>1) | (shift2 << 31);\r
186 shift2 = (shift2>>1) | (shift3 << 31);\r
187 shift3 >>= 1;\r
188\r
189 // check if the cycles fall close to the number\r
190 // expected for either the low or high frequency\r
191 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {\r
192 // low frequency represents a 1\r
193 shift3 |= (1<<31);\r
194 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {\r
195 // high frequency represents a 0\r
196 } else {\r
197 // probably detected a gay waveform or noise\r
198 // use this as gaydar or discard shift register and start again\r
199 shift3 = shift2 = shift1 = shift0 = 0;\r
200 }\r
201 samples = i;\r
202\r
203 // for each bit we receive, test if we've detected a valid tag\r
204\r
205 // if we see 17 zeroes followed by 6 ones, we might have a tag\r
206 // remember the bits are backwards\r
207 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {\r
208 // if start and end bytes match, we have a tag so break out of the loop\r
209 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {\r
210 cycles = 0xF0B; //use this as a flag (ugly but whatever)\r
211 break;\r
212 }\r
213 }\r
214 }\r
215 }\r
216 }\r
217\r
218 // if flag is set we have a tag\r
219 if (cycles!=0xF0B) {\r
220 DbpString("Info: No valid tag detected.");\r
221 } else {\r
222 // put 64 bit data into shift1 and shift0\r
223 shift0 = (shift0>>24) | (shift1 << 8);\r
224 shift1 = (shift1>>24) | (shift2 << 8);\r
225\r
226 // align 16 bit crc into lower half of shift2\r
227 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;\r
228\r
229 // if r/w tag, check ident match\r
230 if ( shift3&(1<<15) ) {\r
231 DbpString("Info: TI tag is rewriteable");\r
232 // only 15 bits compare, last bit of ident is not valid\r
233 if ( ((shift3>>16)^shift0)&0x7fff ) {\r
234 DbpString("Error: Ident mismatch!");\r
235 } else {\r
236 DbpString("Info: TI tag ident is valid");\r
237 }\r
238 } else {\r
239 DbpString("Info: TI tag is readonly");\r
240 }\r
241\r
242 // WARNING the order of the bytes in which we calc crc below needs checking\r
243 // i'm 99% sure the crc algorithm is correct, but it may need to eat the\r
244 // bytes in reverse or something\r
245 // calculate CRC\r
246 DWORD crc=0;\r
247\r
248 crc = update_crc16(crc, (shift0)&0xff);\r
249 crc = update_crc16(crc, (shift0>>8)&0xff);\r
250 crc = update_crc16(crc, (shift0>>16)&0xff);\r
251 crc = update_crc16(crc, (shift0>>24)&0xff);\r
252 crc = update_crc16(crc, (shift1)&0xff);\r
253 crc = update_crc16(crc, (shift1>>8)&0xff);\r
254 crc = update_crc16(crc, (shift1>>16)&0xff);\r
255 crc = update_crc16(crc, (shift1>>24)&0xff);\r
256\r
257 DbpString("Info: Tag data_hi, data_lo, crc = ");\r
258 DbpIntegers(shift1, shift0, shift2&0xffff);\r
259 if (crc != (shift2&0xffff)) {\r
260 DbpString("Error: CRC mismatch, expected");\r
261 DbpIntegers(0, 0, crc);\r
262 } else {\r
263 DbpString("Info: CRC is good");\r
264 }\r
265 }\r
266}\r
267\r
268void WriteTIbyte(BYTE b)\r
269{\r
270 int i = 0;\r
271\r
272 // modulate 8 bits out to the antenna\r
273 for (i=0; i<8; i++)\r
274 {\r
275 if (b&(1<<i)) {\r
276 // stop modulating antenna\r
6949aca9 277 LOW(GPIO_SSC_DOUT);\r
7381e8f2 278 SpinDelayUs(1000);\r
279 // modulate antenna\r
6949aca9 280 HIGH(GPIO_SSC_DOUT);\r
7381e8f2 281 SpinDelayUs(1000);\r
282 } else {\r
283 // stop modulating antenna\r
6949aca9 284 LOW(GPIO_SSC_DOUT);\r
7381e8f2 285 SpinDelayUs(300);\r
286 // modulate antenna\r
6949aca9 287 HIGH(GPIO_SSC_DOUT);\r
7381e8f2 288 SpinDelayUs(1700);\r
289 }\r
290 }\r
291}\r
292\r
9bea179a 293void AcquireTiType(void)\r
294{\r
7381e8f2 295 int i, j, n;\r
9bea179a 296 // tag transmission is <20ms, sampling at 2M gives us 40K samples max\r
297 // each sample is 1 bit stuffed into a DWORD so we need 1250 DWORDS\r
7381e8f2 298 #define TIBUFLEN 1250\r
9bea179a 299\r
300 // clear buffer\r
301 memset(BigBuf,0,sizeof(BigBuf));\r
302\r
303 // Set up the synchronous serial port\r
6949aca9 304 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;\r
305 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;\r
9bea179a 306\r
307 // steal this pin from the SSP and use it to control the modulation\r
6949aca9 308 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r
309 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
9bea179a 310\r
6949aca9 311 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;\r
312 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;\r
9bea179a 313\r
6949aca9 314 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long\r
315 // 48/2 = 24 MHz clock must be divided by 12\r
316 AT91C_BASE_SSC->SSC_CMR = 12;\r
9bea179a 317\r
6949aca9 318 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);\r
319 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;\r
320 AT91C_BASE_SSC->SSC_TCMR = 0;\r
321 AT91C_BASE_SSC->SSC_TFMR = 0;\r
9bea179a 322\r
323 LED_D_ON();\r
324\r
325 // modulate antenna\r
6949aca9 326 HIGH(GPIO_SSC_DOUT);\r
9bea179a 327\r
328 // Charge TI tag for 50ms.\r
329 SpinDelay(50);\r
330\r
331 // stop modulating antenna and listen\r
6949aca9 332 LOW(GPIO_SSC_DOUT);\r
9bea179a 333\r
334 LED_D_OFF();\r
335\r
336 i = 0;\r
337 for(;;) {\r
6949aca9 338 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r
339 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer\r
340 i++; if(i >= TIBUFLEN) break;\r
341 }\r
342 WDT_HIT();\r
9bea179a 343 }\r
344\r
345 // return stolen pin to SSP\r
6949aca9 346 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;\r
347 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;\r
9bea179a 348\r
7381e8f2 349 char *dest = (char *)BigBuf;\r
350 n = TIBUFLEN*32;\r
351 // unpack buffer\r
352 for (i=TIBUFLEN-1; i>=0; i--) {\r
353// DbpIntegers(0, 0, BigBuf[i]);\r
354 for (j=0; j<32; j++) {\r
355 if(BigBuf[i] & (1 << j)) {\r
356 dest[--n] = 1;\r
357 } else {\r
358 dest[--n] = -1;\r
359 }\r
9bea179a 360 }\r
361 }\r
362}\r
363\r
9bea179a 364// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc\r
365// if crc provided, it will be written with the data verbatim (even if bogus)\r
366// if not provided a valid crc will be computed from the data and written.\r
367void WriteTItag(DWORD idhi, DWORD idlo, WORD crc)\r
368{\r
369\r
370 // WARNING the order of the bytes in which we calc crc below needs checking\r
371 // i'm 99% sure the crc algorithm is correct, but it may need to eat the\r
372 // bytes in reverse or something\r
373\r
374 if(crc == 0) {\r
375 crc = update_crc16(crc, (idlo)&0xff);\r
376 crc = update_crc16(crc, (idlo>>8)&0xff);\r
377 crc = update_crc16(crc, (idlo>>16)&0xff);\r
378 crc = update_crc16(crc, (idlo>>24)&0xff);\r
379 crc = update_crc16(crc, (idhi)&0xff);\r
380 crc = update_crc16(crc, (idhi>>8)&0xff);\r
381 crc = update_crc16(crc, (idhi>>16)&0xff);\r
382 crc = update_crc16(crc, (idhi>>24)&0xff);\r
383 }\r
384 DbpString("Writing the following data to tag:");\r
385 DbpIntegers(idhi, idlo, crc);\r
386\r
387 // TI tags charge at 134.2Khz\r
388 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
389 // Place FPGA in passthrough mode, in this mode the CROSS_LO line\r
390 // connects to SSP_DIN and the SSP_DOUT logic level controls\r
391 // whether we're modulating the antenna (high)\r
392 // or listening to the antenna (low)\r
393 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r
394 LED_A_ON();\r
395\r
396 // steal this pin from the SSP and use it to control the modulation\r
6949aca9 397 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r
398 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
9bea179a 399\r
400 // writing algorithm:\r
401 // a high bit consists of a field off for 1ms and field on for 1ms\r
402 // a low bit consists of a field off for 0.3ms and field on for 1.7ms\r
403 // initiate a charge time of 50ms (field on) then immediately start writing bits\r
404 // start by writing 0xBB (keyword) and 0xEB (password)\r
405 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)\r
406 // finally end with 0x0300 (write frame)\r
407 // all data is sent lsb firts\r
408 // finish with 15ms programming time\r
409\r
410 // modulate antenna\r
6949aca9 411 HIGH(GPIO_SSC_DOUT);\r
9bea179a 412 SpinDelay(50); // charge time\r
413\r
414 WriteTIbyte(0xbb); // keyword\r
415 WriteTIbyte(0xeb); // password\r
416 WriteTIbyte( (idlo )&0xff );\r
417 WriteTIbyte( (idlo>>8 )&0xff );\r
418 WriteTIbyte( (idlo>>16)&0xff );\r
419 WriteTIbyte( (idlo>>24)&0xff );\r
420 WriteTIbyte( (idhi )&0xff );\r
421 WriteTIbyte( (idhi>>8 )&0xff );\r
422 WriteTIbyte( (idhi>>16)&0xff );\r
423 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo\r
424 WriteTIbyte( (crc )&0xff ); // crc lo\r
425 WriteTIbyte( (crc>>8 )&0xff ); // crc hi\r
426 WriteTIbyte(0x00); // write frame lo\r
427 WriteTIbyte(0x03); // write frame hi\r
6949aca9 428 HIGH(GPIO_SSC_DOUT);\r
9bea179a 429 SpinDelay(50); // programming time\r
430\r
431 LED_A_OFF();\r
432\r
433 // get TI tag data into the buffer\r
434 AcquireTiType();\r
435\r
436 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
7381e8f2 437 DbpString("Now use tiread to check");\r
9bea179a 438}\r
439\r
440void SimulateTagLowFrequency(int period, int ledcontrol)\r
441{\r
442 int i;\r
443 BYTE *tab = (BYTE *)BigBuf;\r
444\r
445 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
446\r
6949aca9 447 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;\r
9bea179a 448\r
6949aca9 449 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
450 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;\r
9bea179a 451\r
452#define SHORT_COIL() LOW(GPIO_SSC_DOUT)\r
6949aca9 453#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)\r
9bea179a 454\r
455 i = 0;\r
456 for(;;) {\r
6949aca9 457 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {\r
9bea179a 458 if(BUTTON_PRESS()) {\r
459 DbpString("Stopped");\r
460 return;\r
461 }\r
462 WDT_HIT();\r
463 }\r
464\r
465 if (ledcontrol)\r
466 LED_D_ON();\r
467\r
468 if(tab[i])\r
469 OPEN_COIL();\r
470 else\r
471 SHORT_COIL();\r
472\r
473 if (ledcontrol)\r
474 LED_D_OFF();\r
475\r
6949aca9 476 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {\r
9bea179a 477 if(BUTTON_PRESS()) {\r
478 DbpString("Stopped");\r
479 return;\r
480 }\r
481 WDT_HIT();\r
482 }\r
483\r
484 i++;\r
485 if(i == period) i = 0;\r
486 }\r
487}\r
488\r
0fa9ca5b 489/* Provides a framework for bidirectional LF tag communication\r
490 * Encoding is currently Hitag2, but the general idea can probably\r
491 * be transferred to other encodings.\r
492 * \r
493 * The new FPGA code will, for the LF simulator mode, give on SSC_FRAME\r
494 * (PA15) a thresholded version of the signal from the ADC. Setting the\r
495 * ADC path to the low frequency peak detection signal, will enable a\r
496 * somewhat reasonable receiver for modulation on the carrier signal\r
497 * that is generated by the reader. The signal is low when the reader\r
498 * field is switched off, and high when the reader field is active. Due\r
499 * to the way that the signal looks like, mostly only the rising edge is\r
500 * useful, your mileage may vary.\r
501 * \r
502 * Neat perk: PA15 can not only be used as a bit-banging GPIO, but is also\r
503 * TIOA1, which can be used as the capture input for timer 1. This should\r
504 * make it possible to measure the exact edge-to-edge time, without processor\r
505 * intervention.\r
506 * \r
507 * Arguments: divisor is the divisor to be sent to the FPGA (e.g. 95 for 125kHz)\r
508 * t0 is the carrier frequency cycle duration in terms of MCK (384 for 125kHz)\r
509 * \r
510 * The following defines are in carrier periods: \r
511 */\r
512#define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */ \r
513#define HITAG_T_1_MIN 24 /* T[1] should be 26..30 */\r
514#define HITAG_T_EOF 40 /* T_EOF should be > 36 */\r
515#define HITAG_T_WRESP 208 /* T_wresp should be 204..212 */\r
516\r
517static void hitag_handle_frame(int t0, int frame_len, char *frame);\r
518//#define DEBUG_RA_VALUES 1\r
519#define DEBUG_FRAME_CONTENTS 1\r
520void SimulateTagLowFrequencyBidir(int divisor, int t0)\r
521{\r
522#if DEBUG_RA_VALUES || DEBUG_FRAME_CONTENTS\r
523 int i = 0;\r
524#endif\r
525 char frame[10];\r
526 int frame_pos=0;\r
527 \r
528 DbpString("Starting Hitag2 emulator, press button to end");\r
529 hitag2_init();\r
530 \r
531 /* Set up simulator mode, frequency divisor which will drive the FPGA\r
6949aca9 532 * and analog mux selection.\r
0fa9ca5b 533 */\r
534 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
535 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);\r
536 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
537 RELAY_OFF();\r
538 \r
539 /* Set up Timer 1:\r
540 * Capture mode, timer source MCK/2 (TIMER_CLOCK1), TIOA is external trigger,\r
541 * external trigger rising edge, load RA on rising edge of TIOA, load RB on rising\r
6949aca9 542 * edge of TIOA. Assign PA15 to TIOA1 (peripheral B)\r
0fa9ca5b 543 */\r
544 \r
6949aca9 545 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);\r
546 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;\r
547 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r
548 AT91C_BASE_TC1->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 |\r
549 AT91C_TC_ETRGEDG_RISING |\r
550 AT91C_TC_ABETRG |\r
551 AT91C_TC_LDRA_RISING |\r
552 AT91C_TC_LDRB_RISING;\r
553 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN |\r
554 AT91C_TC_SWTRG;\r
0fa9ca5b 555 \r
556 /* calculate the new value for the carrier period in terms of TC1 values */\r
557 t0 = t0/2;\r
558 \r
559 int overflow = 0;\r
560 while(!BUTTON_PRESS()) {\r
561 WDT_HIT();\r
6949aca9 562 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {\r
563 int ra = AT91C_BASE_TC1->TC_RA;\r
0fa9ca5b 564 if((ra > t0*HITAG_T_EOF) | overflow) ra = t0*HITAG_T_EOF+1;\r
565#if DEBUG_RA_VALUES\r
566 if(ra > 255 || overflow) ra = 255;\r
567 ((char*)BigBuf)[i] = ra;\r
568 i = (i+1) % 8000;\r
569#endif\r
570 \r
571 if(overflow || (ra > t0*HITAG_T_EOF) || (ra < t0*HITAG_T_0_MIN)) {\r
572 /* Ignore */\r
573 } else if(ra >= t0*HITAG_T_1_MIN ) {\r
574 /* '1' bit */\r
575 if(frame_pos < 8*sizeof(frame)) {\r
576 frame[frame_pos / 8] |= 1<<( 7-(frame_pos%8) );\r
577 frame_pos++;\r
578 }\r
579 } else if(ra >= t0*HITAG_T_0_MIN) {\r
580 /* '0' bit */\r
581 if(frame_pos < 8*sizeof(frame)) {\r
582 frame[frame_pos / 8] |= 0<<( 7-(frame_pos%8) );\r
583 frame_pos++;\r
584 }\r
585 }\r
586 \r
587 overflow = 0;\r
588 LED_D_ON();\r
589 } else {\r
6949aca9 590 if(AT91C_BASE_TC1->TC_CV > t0*HITAG_T_EOF) {\r
0fa9ca5b 591 /* Minor nuisance: In Capture mode, the timer can not be\r
592 * stopped by a Compare C. There's no way to stop the clock\r
593 * in software, so we'll just have to note the fact that an\r
594 * overflow happened and the next loaded timer value might\r
595 * have wrapped. Also, this marks the end of frame, and the\r
596 * still running counter can be used to determine the correct\r
6949aca9 597 * time for the start of the reply.\r
0fa9ca5b 598 */ \r
599 overflow = 1;\r
600 \r
601 if(frame_pos > 0) {\r
602 /* Have a frame, do something with it */\r
603#if DEBUG_FRAME_CONTENTS\r
604 ((char*)BigBuf)[i++] = frame_pos;\r
605 memcpy( ((char*)BigBuf)+i, frame, 7);\r
606 i+=7;\r
607 i = i % sizeof(BigBuf);\r
608#endif\r
609 hitag_handle_frame(t0, frame_pos, frame);\r
610 memset(frame, 0, sizeof(frame));\r
611 }\r
612 frame_pos = 0;\r
613\r
614 }\r
615 LED_D_OFF();\r
616 }\r
617 }\r
618 DbpString("All done");\r
619}\r
620\r
621static void hitag_send_bit(int t0, int bit) {\r
622 if(bit == 1) {\r
623 /* Manchester: Loaded, then unloaded */\r
624 LED_A_ON();\r
625 SHORT_COIL();\r
6949aca9 626 while(AT91C_BASE_TC1->TC_CV < t0*15);\r
0fa9ca5b 627 OPEN_COIL();\r
6949aca9 628 while(AT91C_BASE_TC1->TC_CV < t0*31);\r
0fa9ca5b 629 LED_A_OFF();\r
630 } else if(bit == 0) {\r
631 /* Manchester: Unloaded, then loaded */\r
632 LED_B_ON();\r
633 OPEN_COIL();\r
6949aca9 634 while(AT91C_BASE_TC1->TC_CV < t0*15);\r
0fa9ca5b 635 SHORT_COIL();\r
6949aca9 636 while(AT91C_BASE_TC1->TC_CV < t0*31);\r
0fa9ca5b 637 LED_B_OFF();\r
638 }\r
6949aca9 639 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset clock for the next bit */\r
0fa9ca5b 640 \r
641}\r
642static void hitag_send_frame(int t0, int frame_len, const char const * frame, int fdt)\r
643{\r
644 OPEN_COIL();\r
6949aca9 645 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
0fa9ca5b 646 \r
647 /* Wait for HITAG_T_WRESP carrier periods after the last reader bit,\r
648 * not that since the clock counts since the rising edge, but T_wresp is\r
649 * with respect to the falling edge, we need to wait actually (T_wresp - T_g)\r
6949aca9 650 * periods. The gap time T_g varies (4..10).\r
0fa9ca5b 651 */\r
6949aca9 652 while(AT91C_BASE_TC1->TC_CV < t0*(fdt-8));\r
0fa9ca5b 653\r
6949aca9 654 int saved_cmr = AT91C_BASE_TC1->TC_CMR;\r
655 AT91C_BASE_TC1->TC_CMR &= ~AT91C_TC_ETRGEDG; /* Disable external trigger for the clock */\r
656 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset the clock and use it for response timing */\r
0fa9ca5b 657 \r
658 int i;\r
659 for(i=0; i<5; i++)\r
660 hitag_send_bit(t0, 1); /* Start of frame */\r
661 \r
662 for(i=0; i<frame_len; i++) {\r
663 hitag_send_bit(t0, !!(frame[i/ 8] & (1<<( 7-(i%8) ))) );\r
664 }\r
665 \r
666 OPEN_COIL();\r
6949aca9 667 AT91C_BASE_TC1->TC_CMR = saved_cmr;\r
0fa9ca5b 668}\r
669\r
670/* Callback structure to cleanly separate tag emulation code from the radio layer. */\r
671static int hitag_cb(const char* response_data, const int response_length, const int fdt, void *cb_cookie)\r
672{\r
673 hitag_send_frame(*(int*)cb_cookie, response_length, response_data, fdt);\r
674 return 0;\r
675}\r
676/* Frame length in bits, frame contents in MSBit first format */\r
677static void hitag_handle_frame(int t0, int frame_len, char *frame)\r
678{\r
679 hitag2_handle_command(frame, frame_len, hitag_cb, &t0);\r
680}\r
681\r
9bea179a 682// compose fc/8 fc/10 waveform\r
683static void fc(int c, int *n) {\r
684 BYTE *dest = (BYTE *)BigBuf;\r
685 int idx;\r
686\r
687 // for when we want an fc8 pattern every 4 logical bits\r
688 if(c==0) {\r
689 dest[((*n)++)]=1;\r
690 dest[((*n)++)]=1;\r
691 dest[((*n)++)]=0;\r
692 dest[((*n)++)]=0;\r
693 dest[((*n)++)]=0;\r
694 dest[((*n)++)]=0;\r
695 dest[((*n)++)]=0;\r
696 dest[((*n)++)]=0;\r
697 }\r
698 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples\r
699 if(c==8) {\r
700 for (idx=0; idx<6; idx++) {\r
701 dest[((*n)++)]=1;\r
702 dest[((*n)++)]=1;\r
703 dest[((*n)++)]=0;\r
704 dest[((*n)++)]=0;\r
705 dest[((*n)++)]=0;\r
706 dest[((*n)++)]=0;\r
707 dest[((*n)++)]=0;\r
708 dest[((*n)++)]=0;\r
709 }\r
710 }\r
711\r
712 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples\r
713 if(c==10) {\r
714 for (idx=0; idx<5; idx++) {\r
715 dest[((*n)++)]=1;\r
716 dest[((*n)++)]=1;\r
717 dest[((*n)++)]=1;\r
718 dest[((*n)++)]=0;\r
719 dest[((*n)++)]=0;\r
720 dest[((*n)++)]=0;\r
721 dest[((*n)++)]=0;\r
722 dest[((*n)++)]=0;\r
723 dest[((*n)++)]=0;\r
724 dest[((*n)++)]=0;\r
725 }\r
726 }\r
727}\r
728\r
729// prepare a waveform pattern in the buffer based on the ID given then\r
730// simulate a HID tag until the button is pressed\r
731void CmdHIDsimTAG(int hi, int lo, int ledcontrol)\r
732{\r
733 int n=0, i=0;\r
734 /*\r
735 HID tag bitstream format\r
736 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits\r
737 A 1 bit is represented as 6 fc8 and 5 fc10 patterns\r
738 A 0 bit is represented as 5 fc10 and 6 fc8 patterns\r
739 A fc8 is inserted before every 4 bits\r
740 A special start of frame pattern is used consisting a0b0 where a and b are neither 0\r
741 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)\r
742 */\r
743\r
744 if (hi>0xFFF) {\r
745 DbpString("Tags can only have 44 bits.");\r
746 return;\r
747 }\r
748 fc(0,&n);\r
749 // special start of frame marker containing invalid bit sequences\r
750 fc(8, &n); fc(8, &n); // invalid\r
751 fc(8, &n); fc(10, &n); // logical 0\r
752 fc(10, &n); fc(10, &n); // invalid\r
753 fc(8, &n); fc(10, &n); // logical 0\r
754\r
755 WDT_HIT();\r
756 // manchester encode bits 43 to 32\r
757 for (i=11; i>=0; i--) {\r
758 if ((i%4)==3) fc(0,&n);\r
759 if ((hi>>i)&1) {\r
760 fc(10, &n); fc(8, &n); // low-high transition\r
761 } else {\r
762 fc(8, &n); fc(10, &n); // high-low transition\r
763 }\r
764 }\r
765\r
766 WDT_HIT();\r
767 // manchester encode bits 31 to 0\r
768 for (i=31; i>=0; i--) {\r
769 if ((i%4)==3) fc(0,&n);\r
770 if ((lo>>i)&1) {\r
771 fc(10, &n); fc(8, &n); // low-high transition\r
772 } else {\r
773 fc(8, &n); fc(10, &n); // high-low transition\r
774 }\r
775 }\r
776\r
777 if (ledcontrol)\r
778 LED_A_ON();\r
779 SimulateTagLowFrequency(n, ledcontrol);\r
780\r
781 if (ledcontrol)\r
782 LED_A_OFF();\r
783}\r
784\r
785\r
786// loop to capture raw HID waveform then FSK demodulate the TAG ID from it\r
787void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)\r
788{\r
789 BYTE *dest = (BYTE *)BigBuf;\r
790 int m=0, n=0, i=0, idx=0, found=0, lastval=0;\r
791 DWORD hi=0, lo=0;\r
792\r
793 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
794 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
795\r
796 // Connect the A/D to the peak-detected low-frequency path.\r
797 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
798\r
799 // Give it a bit of time for the resonant antenna to settle.\r
800 SpinDelay(50);\r
801\r
802 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
803 FpgaSetupSsc();\r
804\r
805 for(;;) {\r
806 WDT_HIT();\r
807 if (ledcontrol)\r
808 LED_A_ON();\r
809 if(BUTTON_PRESS()) {\r
810 DbpString("Stopped");\r
811 if (ledcontrol)\r
812 LED_A_OFF();\r
813 return;\r
814 }\r
815\r
816 i = 0;\r
817 m = sizeof(BigBuf);\r
818 memset(dest,128,m);\r
819 for(;;) {\r
6949aca9 820 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
821 AT91C_BASE_SSC->SSC_THR = 0x43;\r
9bea179a 822 if (ledcontrol)\r
823 LED_D_ON();\r
824 }\r
6949aca9 825 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
826 dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
9bea179a 827 // we don't care about actual value, only if it's more or less than a\r
828 // threshold essentially we capture zero crossings for later analysis\r
829 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;\r
830 i++;\r
831 if (ledcontrol)\r
832 LED_D_OFF();\r
833 if(i >= m) {\r
834 break;\r
835 }\r
836 }\r
837 }\r
838\r
839 // FSK demodulator\r
840\r
841 // sync to first lo-hi transition\r
842 for( idx=1; idx<m; idx++) {\r
843 if (dest[idx-1]<dest[idx])\r
844 lastval=idx;\r
845 break;\r
846 }\r
847 WDT_HIT();\r
848\r
849 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)\r
850 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere\r
851 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10\r
852 for( i=0; idx<m; idx++) {\r
853 if (dest[idx-1]<dest[idx]) {\r
854 dest[i]=idx-lastval;\r
855 if (dest[i] <= 8) {\r
856 dest[i]=1;\r
857 } else {\r
858 dest[i]=0;\r
859 }\r
860\r
861 lastval=idx;\r
862 i++;\r
863 }\r
864 }\r
865 m=i;\r
866 WDT_HIT();\r
867\r
868 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns\r
869 lastval=dest[0];\r
870 idx=0;\r
871 i=0;\r
872 n=0;\r
873 for( idx=0; idx<m; idx++) {\r
874 if (dest[idx]==lastval) {\r
875 n++;\r
876 } else {\r
877 // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,\r
878 // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets\r
879 // swallowed up by rounding\r
880 // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding\r
881 // special start of frame markers use invalid manchester states (no transitions) by using sequences\r
882 // like 111000\r
883 if (dest[idx-1]) {\r
884 n=(n+1)/6; // fc/8 in sets of 6\r
885 } else {\r
886 n=(n+1)/5; // fc/10 in sets of 5\r
887 }\r
888 switch (n) { // stuff appropriate bits in buffer\r
889 case 0:\r
890 case 1: // one bit\r
891 dest[i++]=dest[idx-1];\r
892 break;\r
893 case 2: // two bits\r
894 dest[i++]=dest[idx-1];\r
895 dest[i++]=dest[idx-1];\r
896 break;\r
897 case 3: // 3 bit start of frame markers\r
898 dest[i++]=dest[idx-1];\r
899 dest[i++]=dest[idx-1];\r
900 dest[i++]=dest[idx-1];\r
901 break;\r
902 // When a logic 0 is immediately followed by the start of the next transmisson\r
903 // (special pattern) a pattern of 4 bit duration lengths is created.\r
904 case 4:\r
905 dest[i++]=dest[idx-1];\r
906 dest[i++]=dest[idx-1];\r
907 dest[i++]=dest[idx-1];\r
908 dest[i++]=dest[idx-1];\r
909 break;\r
910 default: // this shouldn't happen, don't stuff any bits\r
911 break;\r
912 }\r
913 n=0;\r
914 lastval=dest[idx];\r
915 }\r
916 }\r
917 m=i;\r
918 WDT_HIT();\r
919\r
920 // final loop, go over previously decoded manchester data and decode into usable tag ID\r
921 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0\r
922 for( idx=0; idx<m-6; idx++) {\r
923 // search for a start of frame marker\r
924 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )\r
925 {\r
926 found=1;\r
927 idx+=6;\r
928 if (found && (hi|lo)) {\r
929 DbpString("TAG ID");\r
930 DbpIntegers(hi, lo, (lo>>1)&0xffff);\r
931 /* if we're only looking for one tag */\r
932 if (findone)\r
933 {\r
934 *high = hi;\r
935 *low = lo;\r
936 return;\r
937 }\r
938 hi=0;\r
939 lo=0;\r
940 found=0;\r
941 }\r
942 }\r
943 if (found) {\r
944 if (dest[idx] && (!dest[idx+1]) ) {\r
945 hi=(hi<<1)|(lo>>31);\r
946 lo=(lo<<1)|0;\r
947 } else if ( (!dest[idx]) && dest[idx+1]) {\r
948 hi=(hi<<1)|(lo>>31);\r
949 lo=(lo<<1)|1;\r
950 } else {\r
951 found=0;\r
952 hi=0;\r
953 lo=0;\r
954 }\r
955 idx++;\r
956 }\r
957 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )\r
958 {\r
959 found=1;\r
960 idx+=6;\r
961 if (found && (hi|lo)) {\r
962 DbpString("TAG ID");\r
963 DbpIntegers(hi, lo, (lo>>1)&0xffff);\r
964 /* if we're only looking for one tag */\r
965 if (findone)\r
966 {\r
967 *high = hi;\r
968 *low = lo;\r
969 return;\r
970 }\r
971 hi=0;\r
972 lo=0;\r
973 found=0;\r
974 }\r
975 }\r
976 }\r
977 WDT_HIT();\r
978 }\r
979}\r
Proxmark3 GIT tracking
Impressum, Datenschutz