]> cvs.zerfleddert.de Git - proxmark3-svn/blame - armsrc/iclass.c
projects / proxmark3-svn / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
bugfix
[proxmark3-svn] / armsrc / iclass.c
CommitLineData
cee5a30d 1//-----------------------------------------------------------------------------
2// Gerhard de Koning Gans - May 2008
3// Hagen Fritsch - June 2010
4// Gerhard de Koning Gans - May 2011
1e262141 5// Gerhard de Koning Gans - June 2012 - Added iClass card and reader emulation
cee5a30d 6//
7// This code is licensed to you under the terms of the GNU GPL, version 2 or,
8// at your option, any later version. See the LICENSE.txt file for the text of
9// the license.
10//-----------------------------------------------------------------------------
11// Routines to support iClass.
12//-----------------------------------------------------------------------------
13// Based on ISO14443a implementation. Still in experimental phase.
14// Contribution made during a security research at Radboud University Nijmegen
15//
16// Please feel free to contribute and extend iClass support!!
17//-----------------------------------------------------------------------------
18//
cee5a30d 19// FIX:
20// ====
21// We still have sometimes a demodulation error when snooping iClass communication.
22// The resulting trace of a read-block-03 command may look something like this:
23//
24// + 22279: : 0c 03 e8 01
25//
26// ...with an incorrect answer...
27//
28// + 85: 0: TAG ff! ff! ff! ff! ff! ff! ff! ff! bb 33 bb 00 01! 0e! 04! bb !crc
29//
30// We still left the error signalling bytes in the traces like 0xbb
31//
32// A correct trace should look like this:
33//
34// + 21112: : 0c 03 e8 01
35// + 85: 0: TAG ff ff ff ff ff ff ff ff ea f5
36//
37//-----------------------------------------------------------------------------
38
39#include "proxmark3.h"
40#include "apps.h"
41#include "util.h"
42#include "string.h"
7e67e42f 43#include "common.h"
fecd8202 44#include "cmd.h"
1e262141 45// Needed for CRC in emulation mode;
46// same construction as in ISO 14443;
47// different initial value (CRC_ICLASS)
48#include "iso14443crc.h"
c3963755 49#include "iso15693tools.h"
cee5a30d 50
1e262141 51static int timeout = 4096;
cee5a30d 52
cee5a30d 53
1e262141 54static int SendIClassAnswer(uint8_t *resp, int respLen, int delay);
cee5a30d 55
56//-----------------------------------------------------------------------------
57// The software UART that receives commands from the reader, and its state
58// variables.
59//-----------------------------------------------------------------------------
60static struct {
61 enum {
62 STATE_UNSYNCD,
63 STATE_START_OF_COMMUNICATION,
64 STATE_RECEIVING
65 } state;
66 uint16_t shiftReg;
67 int bitCnt;
68 int byteCnt;
69 int byteCntMax;
70 int posCnt;
71 int nOutOfCnt;
72 int OutOfCnt;
73 int syncBit;
1e262141 74 int samples;
cee5a30d 75 int highCnt;
76 int swapper;
77 int counter;
78 int bitBuffer;
79 int dropPosition;
6a1f2d82 80 uint8_t *output;
cee5a30d 81} Uart;
82
1e262141 83static RAMFUNC int OutOfNDecoding(int bit)
cee5a30d 84{
9f693930 85 //int error = 0;
cee5a30d 86 int bitright;
87
88 if(!Uart.bitBuffer) {
89 Uart.bitBuffer = bit ^ 0xFF0;
90 return FALSE;
91 }
92 else {
93 Uart.bitBuffer <<= 4;
94 Uart.bitBuffer ^= bit;
95 }
96
97 /*if(Uart.swapper) {
98 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
99 Uart.byteCnt++;
100 Uart.swapper = 0;
101 if(Uart.byteCnt > 15) { return TRUE; }
102 }
103 else {
104 Uart.swapper = 1;
105 }*/
106
107 if(Uart.state != STATE_UNSYNCD) {
108 Uart.posCnt++;
109
110 if((Uart.bitBuffer & Uart.syncBit) ^ Uart.syncBit) {
111 bit = 0x00;
112 }
113 else {
114 bit = 0x01;
115 }
116 if(((Uart.bitBuffer << 1) & Uart.syncBit) ^ Uart.syncBit) {
117 bitright = 0x00;
118 }
119 else {
120 bitright = 0x01;
121 }
122 if(bit != bitright) { bit = bitright; }
123
124
125 // So, now we only have to deal with *bit*, lets see...
126 if(Uart.posCnt == 1) {
127 // measurement first half bitperiod
128 if(!bit) {
129 // Drop in first half means that we are either seeing
130 // an SOF or an EOF.
131
132 if(Uart.nOutOfCnt == 1) {
133 // End of Communication
134 Uart.state = STATE_UNSYNCD;
135 Uart.highCnt = 0;
136 if(Uart.byteCnt == 0) {
137 // Its not straightforward to show single EOFs
138 // So just leave it and do not return TRUE
6a1f2d82 139 Uart.output[0] = 0xf0;
cee5a30d 140 Uart.byteCnt++;
cee5a30d 141 }
142 else {
143 return TRUE;
144 }
145 }
146 else if(Uart.state != STATE_START_OF_COMMUNICATION) {
147 // When not part of SOF or EOF, it is an error
148 Uart.state = STATE_UNSYNCD;
149 Uart.highCnt = 0;
9f693930 150 //error = 4;
cee5a30d 151 }
152 }
153 }
154 else {
155 // measurement second half bitperiod
156 // Count the bitslot we are in... (ISO 15693)
157 Uart.nOutOfCnt++;
158
159 if(!bit) {
160 if(Uart.dropPosition) {
161 if(Uart.state == STATE_START_OF_COMMUNICATION) {
9f693930 162 //error = 1;
cee5a30d 163 }
164 else {
9f693930 165 //error = 7;
cee5a30d 166 }
167 // It is an error if we already have seen a drop in current frame
168 Uart.state = STATE_UNSYNCD;
169 Uart.highCnt = 0;
170 }
171 else {
172 Uart.dropPosition = Uart.nOutOfCnt;
173 }
174 }
175
176 Uart.posCnt = 0;
177
178
179 if(Uart.nOutOfCnt == Uart.OutOfCnt && Uart.OutOfCnt == 4) {
180 Uart.nOutOfCnt = 0;
181
182 if(Uart.state == STATE_START_OF_COMMUNICATION) {
183 if(Uart.dropPosition == 4) {
184 Uart.state = STATE_RECEIVING;
185 Uart.OutOfCnt = 256;
186 }
187 else if(Uart.dropPosition == 3) {
188 Uart.state = STATE_RECEIVING;
189 Uart.OutOfCnt = 4;
190 //Uart.output[Uart.byteCnt] = 0xdd;
191 //Uart.byteCnt++;
192 }
193 else {
194 Uart.state = STATE_UNSYNCD;
195 Uart.highCnt = 0;
196 }
197 Uart.dropPosition = 0;
198 }
199 else {
200 // RECEIVING DATA
201 // 1 out of 4
202 if(!Uart.dropPosition) {
203 Uart.state = STATE_UNSYNCD;
204 Uart.highCnt = 0;
9f693930 205 //error = 9;
cee5a30d 206 }
207 else {
208 Uart.shiftReg >>= 2;
209
210 // Swap bit order
211 Uart.dropPosition--;
212 //if(Uart.dropPosition == 1) { Uart.dropPosition = 2; }
213 //else if(Uart.dropPosition == 2) { Uart.dropPosition = 1; }
214
215 Uart.shiftReg ^= ((Uart.dropPosition & 0x03) << 6);
216 Uart.bitCnt += 2;
217 Uart.dropPosition = 0;
218
219 if(Uart.bitCnt == 8) {
220 Uart.output[Uart.byteCnt] = (Uart.shiftReg & 0xff);
221 Uart.byteCnt++;
cee5a30d 222 Uart.bitCnt = 0;
223 Uart.shiftReg = 0;
224 }
225 }
226 }
227 }
228 else if(Uart.nOutOfCnt == Uart.OutOfCnt) {
229 // RECEIVING DATA
230 // 1 out of 256
231 if(!Uart.dropPosition) {
232 Uart.state = STATE_UNSYNCD;
233 Uart.highCnt = 0;
9f693930 234 //error = 3;
cee5a30d 235 }
236 else {
237 Uart.dropPosition--;
238 Uart.output[Uart.byteCnt] = (Uart.dropPosition & 0xff);
239 Uart.byteCnt++;
cee5a30d 240 Uart.bitCnt = 0;
241 Uart.shiftReg = 0;
242 Uart.nOutOfCnt = 0;
243 Uart.dropPosition = 0;
244 }
245 }
246
247 /*if(error) {
248 Uart.output[Uart.byteCnt] = 0xAA;
249 Uart.byteCnt++;
250 Uart.output[Uart.byteCnt] = error & 0xFF;
251 Uart.byteCnt++;
252 Uart.output[Uart.byteCnt] = 0xAA;
253 Uart.byteCnt++;
254 Uart.output[Uart.byteCnt] = (Uart.bitBuffer >> 8) & 0xFF;
255 Uart.byteCnt++;
256 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
257 Uart.byteCnt++;
258 Uart.output[Uart.byteCnt] = (Uart.syncBit >> 3) & 0xFF;
259 Uart.byteCnt++;
260 Uart.output[Uart.byteCnt] = 0xAA;
261 Uart.byteCnt++;
262 return TRUE;
263 }*/
264 }
265
266 }
267 else {
268 bit = Uart.bitBuffer & 0xf0;
269 bit >>= 4;
270 bit ^= 0x0F; // drops become 1s ;-)
271 if(bit) {
272 // should have been high or at least (4 * 128) / fc
273 // according to ISO this should be at least (9 * 128 + 20) / fc
274 if(Uart.highCnt == 8) {
275 // we went low, so this could be start of communication
276 // it turns out to be safer to choose a less significant
277 // syncbit... so we check whether the neighbour also represents the drop
278 Uart.posCnt = 1; // apparently we are busy with our first half bit period
279 Uart.syncBit = bit & 8;
280 Uart.samples = 3;
281 if(!Uart.syncBit) { Uart.syncBit = bit & 4; Uart.samples = 2; }
282 else if(bit & 4) { Uart.syncBit = bit & 4; Uart.samples = 2; bit <<= 2; }
283 if(!Uart.syncBit) { Uart.syncBit = bit & 2; Uart.samples = 1; }
284 else if(bit & 2) { Uart.syncBit = bit & 2; Uart.samples = 1; bit <<= 1; }
285 if(!Uart.syncBit) { Uart.syncBit = bit & 1; Uart.samples = 0;
286 if(Uart.syncBit && (Uart.bitBuffer & 8)) {
287 Uart.syncBit = 8;
288
289 // the first half bit period is expected in next sample
290 Uart.posCnt = 0;
291 Uart.samples = 3;
292 }
293 }
294 else if(bit & 1) { Uart.syncBit = bit & 1; Uart.samples = 0; }
295
296 Uart.syncBit <<= 4;
297 Uart.state = STATE_START_OF_COMMUNICATION;
298 Uart.bitCnt = 0;
299 Uart.byteCnt = 0;
cee5a30d 300 Uart.nOutOfCnt = 0;
301 Uart.OutOfCnt = 4; // Start at 1/4, could switch to 1/256
302 Uart.dropPosition = 0;
303 Uart.shiftReg = 0;
9f693930 304 //error = 0;
cee5a30d 305 }
306 else {
307 Uart.highCnt = 0;
308 }
309 }
310 else {
311 if(Uart.highCnt < 8) {
312 Uart.highCnt++;
313 }
314 }
315 }
316
317 return FALSE;
318}
319
320//=============================================================================
1e262141 321// Manchester
cee5a30d 322//=============================================================================
323
324static struct {
325 enum {
326 DEMOD_UNSYNCD,
327 DEMOD_START_OF_COMMUNICATION,
328 DEMOD_START_OF_COMMUNICATION2,
329 DEMOD_START_OF_COMMUNICATION3,
330 DEMOD_SOF_COMPLETE,
331 DEMOD_MANCHESTER_D,
332 DEMOD_MANCHESTER_E,
333 DEMOD_END_OF_COMMUNICATION,
334 DEMOD_END_OF_COMMUNICATION2,
335 DEMOD_MANCHESTER_F,
336 DEMOD_ERROR_WAIT
337 } state;
338 int bitCount;
339 int posCount;
340 int syncBit;
cee5a30d 341 uint16_t shiftReg;
342 int buffer;
343 int buffer2;
344 int buffer3;
345 int buff;
346 int samples;
347 int len;
348 enum {
349 SUB_NONE,
350 SUB_FIRST_HALF,
351 SUB_SECOND_HALF,
352 SUB_BOTH
353 } sub;
6a1f2d82 354 uint8_t *output;
cee5a30d 355} Demod;
356
357static RAMFUNC int ManchesterDecoding(int v)
358{
359 int bit;
360 int modulation;
361 int error = 0;
362
363 bit = Demod.buffer;
364 Demod.buffer = Demod.buffer2;
365 Demod.buffer2 = Demod.buffer3;
366 Demod.buffer3 = v;
367
368 if(Demod.buff < 3) {
369 Demod.buff++;
370 return FALSE;
371 }
372
373 if(Demod.state==DEMOD_UNSYNCD) {
374 Demod.output[Demod.len] = 0xfa;
375 Demod.syncBit = 0;
376 //Demod.samples = 0;
377 Demod.posCount = 1; // This is the first half bit period, so after syncing handle the second part
cee5a30d 378
379 if(bit & 0x08) {
380 Demod.syncBit = 0x08;
381 }
382
383 if(bit & 0x04) {
384 if(Demod.syncBit) {
385 bit <<= 4;
386 }
387 Demod.syncBit = 0x04;
388 }
389
390 if(bit & 0x02) {
391 if(Demod.syncBit) {
392 bit <<= 2;
393 }
394 Demod.syncBit = 0x02;
395 }
396
397 if(bit & 0x01 && Demod.syncBit) {
398 Demod.syncBit = 0x01;
399 }
400
401 if(Demod.syncBit) {
402 Demod.len = 0;
403 Demod.state = DEMOD_START_OF_COMMUNICATION;
404 Demod.sub = SUB_FIRST_HALF;
405 Demod.bitCount = 0;
406 Demod.shiftReg = 0;
cee5a30d 407 Demod.samples = 0;
408 if(Demod.posCount) {
409 //if(trigger) LED_A_OFF(); // Not useful in this case...
410 switch(Demod.syncBit) {
411 case 0x08: Demod.samples = 3; break;
412 case 0x04: Demod.samples = 2; break;
413 case 0x02: Demod.samples = 1; break;
414 case 0x01: Demod.samples = 0; break;
415 }
416 // SOF must be long burst... otherwise stay unsynced!!!
417 if(!(Demod.buffer & Demod.syncBit) || !(Demod.buffer2 & Demod.syncBit)) {
418 Demod.state = DEMOD_UNSYNCD;
419 }
420 }
421 else {
422 // SOF must be long burst... otherwise stay unsynced!!!
423 if(!(Demod.buffer2 & Demod.syncBit) || !(Demod.buffer3 & Demod.syncBit)) {
424 Demod.state = DEMOD_UNSYNCD;
425 error = 0x88;
426 }
427
428 }
429 error = 0;
430
431 }
432 }
433 else {
434 modulation = bit & Demod.syncBit;
435 modulation |= ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit;
cee5a30d 436
437 Demod.samples += 4;
438
439 if(Demod.posCount==0) {
440 Demod.posCount = 1;
441 if(modulation) {
442 Demod.sub = SUB_FIRST_HALF;
443 }
444 else {
445 Demod.sub = SUB_NONE;
446 }
447 }
448 else {
449 Demod.posCount = 0;
450 /*(modulation && (Demod.sub == SUB_FIRST_HALF)) {
451 if(Demod.state!=DEMOD_ERROR_WAIT) {
452 Demod.state = DEMOD_ERROR_WAIT;
453 Demod.output[Demod.len] = 0xaa;
454 error = 0x01;
455 }
456 }*/
457 //else if(modulation) {
458 if(modulation) {
459 if(Demod.sub == SUB_FIRST_HALF) {
460 Demod.sub = SUB_BOTH;
461 }
462 else {
463 Demod.sub = SUB_SECOND_HALF;
464 }
465 }
466 else if(Demod.sub == SUB_NONE) {
467 if(Demod.state == DEMOD_SOF_COMPLETE) {
468 Demod.output[Demod.len] = 0x0f;
469 Demod.len++;
cee5a30d 470 Demod.state = DEMOD_UNSYNCD;
471// error = 0x0f;
472 return TRUE;
473 }
474 else {
475 Demod.state = DEMOD_ERROR_WAIT;
476 error = 0x33;
477 }
478 /*if(Demod.state!=DEMOD_ERROR_WAIT) {
479 Demod.state = DEMOD_ERROR_WAIT;
480 Demod.output[Demod.len] = 0xaa;
481 error = 0x01;
482 }*/
483 }
484
485 switch(Demod.state) {
486 case DEMOD_START_OF_COMMUNICATION:
487 if(Demod.sub == SUB_BOTH) {
488 //Demod.state = DEMOD_MANCHESTER_D;
489 Demod.state = DEMOD_START_OF_COMMUNICATION2;
490 Demod.posCount = 1;
491 Demod.sub = SUB_NONE;
492 }
493 else {
494 Demod.output[Demod.len] = 0xab;
495 Demod.state = DEMOD_ERROR_WAIT;
496 error = 0xd2;
497 }
498 break;
499 case DEMOD_START_OF_COMMUNICATION2:
500 if(Demod.sub == SUB_SECOND_HALF) {
501 Demod.state = DEMOD_START_OF_COMMUNICATION3;
502 }
503 else {
504 Demod.output[Demod.len] = 0xab;
505 Demod.state = DEMOD_ERROR_WAIT;
506 error = 0xd3;
507 }
508 break;
509 case DEMOD_START_OF_COMMUNICATION3:
510 if(Demod.sub == SUB_SECOND_HALF) {
511// Demod.state = DEMOD_MANCHESTER_D;
512 Demod.state = DEMOD_SOF_COMPLETE;
513 //Demod.output[Demod.len] = Demod.syncBit & 0xFF;
514 //Demod.len++;
515 }
516 else {
517 Demod.output[Demod.len] = 0xab;
518 Demod.state = DEMOD_ERROR_WAIT;
519 error = 0xd4;
520 }
521 break;
522 case DEMOD_SOF_COMPLETE:
523 case DEMOD_MANCHESTER_D:
524 case DEMOD_MANCHESTER_E:
525 // OPPOSITE FROM ISO14443 - 11110000 = 0 (1 in 14443)
526 // 00001111 = 1 (0 in 14443)
527 if(Demod.sub == SUB_SECOND_HALF) { // SUB_FIRST_HALF
528 Demod.bitCount++;
529 Demod.shiftReg = (Demod.shiftReg >> 1) ^ 0x100;
530 Demod.state = DEMOD_MANCHESTER_D;
531 }
532 else if(Demod.sub == SUB_FIRST_HALF) { // SUB_SECOND_HALF
533 Demod.bitCount++;
534 Demod.shiftReg >>= 1;
535 Demod.state = DEMOD_MANCHESTER_E;
536 }
537 else if(Demod.sub == SUB_BOTH) {
538 Demod.state = DEMOD_MANCHESTER_F;
539 }
540 else {
541 Demod.state = DEMOD_ERROR_WAIT;
542 error = 0x55;
543 }
544 break;
545
546 case DEMOD_MANCHESTER_F:
547 // Tag response does not need to be a complete byte!
548 if(Demod.len > 0 || Demod.bitCount > 0) {
549 if(Demod.bitCount > 1) { // was > 0, do not interpret last closing bit, is part of EOF
6a1f2d82 550 Demod.shiftReg >>= (9 - Demod.bitCount); // right align data
cee5a30d 551 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
552 Demod.len++;
cee5a30d 553 }
554
555 Demod.state = DEMOD_UNSYNCD;
556 return TRUE;
557 }
558 else {
559 Demod.output[Demod.len] = 0xad;
560 Demod.state = DEMOD_ERROR_WAIT;
561 error = 0x03;
562 }
563 break;
564
565 case DEMOD_ERROR_WAIT:
566 Demod.state = DEMOD_UNSYNCD;
567 break;
568
569 default:
570 Demod.output[Demod.len] = 0xdd;
571 Demod.state = DEMOD_UNSYNCD;
572 break;
573 }
574
575 /*if(Demod.bitCount>=9) {
576 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
577 Demod.len++;
578
579 Demod.parityBits <<= 1;
580 Demod.parityBits ^= ((Demod.shiftReg >> 8) & 0x01);
581
582 Demod.bitCount = 0;
583 Demod.shiftReg = 0;
584 }*/
585 if(Demod.bitCount>=8) {
586 Demod.shiftReg >>= 1;
587 Demod.output[Demod.len] = (Demod.shiftReg & 0xff);
588 Demod.len++;
cee5a30d 589 Demod.bitCount = 0;
590 Demod.shiftReg = 0;
591 }
592
593 if(error) {
594 Demod.output[Demod.len] = 0xBB;
595 Demod.len++;
596 Demod.output[Demod.len] = error & 0xFF;
597 Demod.len++;
598 Demod.output[Demod.len] = 0xBB;
599 Demod.len++;
600 Demod.output[Demod.len] = bit & 0xFF;
601 Demod.len++;
602 Demod.output[Demod.len] = Demod.buffer & 0xFF;
603 Demod.len++;
604 // Look harder ;-)
605 Demod.output[Demod.len] = Demod.buffer2 & 0xFF;
606 Demod.len++;
607 Demod.output[Demod.len] = Demod.syncBit & 0xFF;
608 Demod.len++;
609 Demod.output[Demod.len] = 0xBB;
610 Demod.len++;
611 return TRUE;
612 }
613
614 }
615
616 } // end (state != UNSYNCED)
617
618 return FALSE;
619}
620
621//=============================================================================
1e262141 622// Finally, a `sniffer' for iClass communication
cee5a30d 623// Both sides of communication!
624//=============================================================================
625
626//-----------------------------------------------------------------------------
627// Record the sequence of commands sent by the reader to the tag, with
628// triggering so that we start recording at the point that the tag is moved
629// near the reader.
630//-----------------------------------------------------------------------------
631void RAMFUNC SnoopIClass(void)
632{
17cba269 633
cee5a30d 634
635 // We won't start recording the frames that we acquire until we trigger;
636 // a good trigger condition to get started is probably when we see a
637 // response from the tag.
9f693930 638 //int triggered = FALSE; // FALSE to wait first for card
cee5a30d 639
640 // The command (reader -> tag) that we're receiving.
641 // The length of a received command will in most cases be no more than 18 bytes.
642 // So 32 should be enough!
17cba269 643 uint8_t *readerToTagCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);
cee5a30d 644 // The response (tag -> reader) that we're receiving.
6a1f2d82 645 uint8_t *tagToReaderResponse = (((uint8_t *)BigBuf) + RECV_RESP_OFFSET);
646
7cc204bf 647 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
648
1e262141 649 // reset traceLen to 0
650 iso14a_set_tracing(TRUE);
d19929cb 651 iso14a_clear_trace();
1e262141 652 iso14a_set_trigger(FALSE);
cee5a30d 653
654 // The DMA buffer, used to stream samples from the FPGA
655 int8_t *dmaBuf = ((int8_t *)BigBuf) + DMA_BUFFER_OFFSET;
656 int lastRxCounter;
657 int8_t *upTo;
658 int smpl;
659 int maxBehindBy = 0;
660
661 // Count of samples received so far, so that we can include timing
662 // information in the trace buffer.
663 int samples = 0;
664 rsamples = 0;
665
cee5a30d 666 // Set up the demodulator for tag -> reader responses.
17cba269 667 Demod.output = tagToReaderResponse;
cee5a30d 668 Demod.len = 0;
669 Demod.state = DEMOD_UNSYNCD;
670
671 // Setup for the DMA.
672 FpgaSetupSsc();
673 upTo = dmaBuf;
674 lastRxCounter = DMA_BUFFER_SIZE;
675 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
676
677 // And the reader -> tag commands
678 memset(&Uart, 0, sizeof(Uart));
17cba269 679 Uart.output = readerToTagCmd;
cee5a30d 680 Uart.byteCntMax = 32; // was 100 (greg)////////////////////////////////////////////////////////////////////////
681 Uart.state = STATE_UNSYNCD;
682
683 // And put the FPGA in the appropriate mode
684 // Signal field is off with the appropriate LED
685 LED_D_OFF();
686 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_SNIFFER);
687 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
688
81012e67 689 uint32_t time_0 = GetCountSspClk();
55eaed8f
MHS		 690 uint32_t time_start = 0;
691 uint32_t time_stop = 0;
81012e67 692
cee5a30d 693 int div = 0;
694 //int div2 = 0;
695 int decbyte = 0;
696 int decbyter = 0;
697
698 // And now we loop, receiving samples.
699 for(;;) {
700 LED_A_ON();
701 WDT_HIT();
702 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &
703 (DMA_BUFFER_SIZE-1);
704 if(behindBy > maxBehindBy) {
705 maxBehindBy = behindBy;
706 if(behindBy > 400) {
707 Dbprintf("blew circular buffer! behindBy=0x%x", behindBy);
708 goto done;
709 }
710 }
711 if(behindBy < 1) continue;
712
713 LED_A_OFF();
714 smpl = upTo[0];
715 upTo++;
716 lastRxCounter -= 1;
717 if(upTo - dmaBuf > DMA_BUFFER_SIZE) {
718 upTo -= DMA_BUFFER_SIZE;
719 lastRxCounter += DMA_BUFFER_SIZE;
720 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
721 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
722 }
723
724 //samples += 4;
725 samples += 1;
cee5a30d 726
cee5a30d 727 if(smpl & 0xF) {
728 decbyte ^= (1 << (3 - div));
729 }
cee5a30d 730
731 // FOR READER SIDE COMMUMICATION...
17cba269 732
cee5a30d 733 decbyter <<= 2;
734 decbyter ^= (smpl & 0x30);
735
736 div++;
737
738 if((div + 1) % 2 == 0) {
739 smpl = decbyter;
1e262141 740 if(OutOfNDecoding((smpl & 0xF0) >> 4)) {
cee5a30d 741 rsamples = samples - Uart.samples;
55eaed8f 742 time_stop = (GetCountSspClk()-time_0) << 4;
cee5a30d 743 LED_C_ON();
17cba269 744
81012e67 745 //if(!LogTrace(Uart.output,Uart.byteCnt, rsamples, Uart.parityBits,TRUE)) break;
17cba269 746 //if(!LogTrace(NULL, 0, Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, 0, TRUE)) break;
6a1f2d82 747 if(tracing) {
748 uint8_t parity[MAX_PARITY_SIZE];
749 GetParity(Uart.output, Uart.byteCnt, parity);
55eaed8f 750 LogTrace(Uart.output,Uart.byteCnt, time_start, time_stop, parity, TRUE);
81012e67
MHS		 751 }
752
17cba269
MHS		 753
754 /* And ready to receive another command. */
cee5a30d 755 Uart.state = STATE_UNSYNCD;
756 /* And also reset the demod code, which might have been */
757 /* false-triggered by the commands from the reader. */
758 Demod.state = DEMOD_UNSYNCD;
759 LED_B_OFF();
760 Uart.byteCnt = 0;
55eaed8f
MHS		 761 }else{
762 time_start = (GetCountSspClk()-time_0) << 4;
cee5a30d 763 }
764 decbyter = 0;
765 }
766
767 if(div > 3) {
768 smpl = decbyte;
769 if(ManchesterDecoding(smpl & 0x0F)) {
55eaed8f
MHS		 770 time_stop = (GetCountSspClk()-time_0) << 4;
771
772 rsamples = samples - Demod.samples;
cee5a30d 773 LED_B_ON();
774
6a1f2d82 775 if(tracing) {
776 uint8_t parity[MAX_PARITY_SIZE];
777 GetParity(Demod.output, Demod.len, parity);
55eaed8f 778 LogTrace(Demod.output, Demod.len, time_start, time_stop, parity, FALSE);
81012e67 779 }
17cba269 780
cee5a30d 781 // And ready to receive another response.
782 memset(&Demod, 0, sizeof(Demod));
17cba269 783 Demod.output = tagToReaderResponse;
cee5a30d 784 Demod.state = DEMOD_UNSYNCD;
785 LED_C_OFF();
55eaed8f
MHS		 786 }else{
787 time_start = (GetCountSspClk()-time_0) << 4;
cee5a30d 788 }
789
790 div = 0;
791 decbyte = 0x00;
792 }
793 //}
794
795 if(BUTTON_PRESS()) {
796 DbpString("cancelled_a");
797 goto done;
798 }
799 }
800
801 DbpString("COMMAND FINISHED");
802
803 Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
804 Dbprintf("%x %x %x", Uart.byteCntMax, traceLen, (int)Uart.output[0]);
805
806done:
807 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
808 Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
809 Dbprintf("%x %x %x", Uart.byteCntMax, traceLen, (int)Uart.output[0]);
810 LED_A_OFF();
811 LED_B_OFF();
1e262141 812 LED_C_OFF();
813 LED_D_OFF();
814}
815
912a3e94 816void rotateCSN(uint8_t* originalCSN, uint8_t* rotatedCSN) {
817 int i;
818 for(i = 0; i < 8; i++) {
819 rotatedCSN[i] = (originalCSN[i] >> 3) | (originalCSN[(i+1)%8] << 5);
1e262141 820 }
821}
822
823//-----------------------------------------------------------------------------
824// Wait for commands from reader
825// Stop when button is pressed
826// Or return TRUE when command is captured
827//-----------------------------------------------------------------------------
828static int GetIClassCommandFromReader(uint8_t *received, int *len, int maxLen)
829{
912a3e94 830 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1e262141 831 // only, since we are receiving, not transmitting).
832 // Signal field is off with the appropriate LED
833 LED_D_OFF();
834 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
835
836 // Now run a `software UART' on the stream of incoming samples.
837 Uart.output = received;
838 Uart.byteCntMax = maxLen;
839 Uart.state = STATE_UNSYNCD;
840
841 for(;;) {
842 WDT_HIT();
843
844 if(BUTTON_PRESS()) return FALSE;
845
846 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
847 AT91C_BASE_SSC->SSC_THR = 0x00;
848 }
849 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
850 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
3fe4ff4f 851
1e262141 852 if(OutOfNDecoding(b & 0x0f)) {
853 *len = Uart.byteCnt;
854 return TRUE;
855 }
856 }
857 }
858}
859
645c960f
MHS		 860static uint8_t encode4Bits(const uint8_t b)
861{
862 uint8_t c = b & 0xF;
863 // OTA, the least significant bits first
864 // The columns are
865 // 1 - Bit value to send
866 // 2 - Reversed (big-endian)
867 // 3 - Encoded
868 // 4 - Hex values
869
870 switch(c){
871 // 1 2 3 4
872 case 15: return 0x55; // 1111 -> 1111 -> 01010101 -> 0x55
873 case 14: return 0x95; // 1110 -> 0111 -> 10010101 -> 0x95
874 case 13: return 0x65; // 1101 -> 1011 -> 01100101 -> 0x65
875 case 12: return 0xa5; // 1100 -> 0011 -> 10100101 -> 0xa5
876 case 11: return 0x59; // 1011 -> 1101 -> 01011001 -> 0x59
877 case 10: return 0x99; // 1010 -> 0101 -> 10011001 -> 0x99
878 case 9: return 0x69; // 1001 -> 1001 -> 01101001 -> 0x69
879 case 8: return 0xa9; // 1000 -> 0001 -> 10101001 -> 0xa9
880 case 7: return 0x56; // 0111 -> 1110 -> 01010110 -> 0x56
881 case 6: return 0x96; // 0110 -> 0110 -> 10010110 -> 0x96
882 case 5: return 0x66; // 0101 -> 1010 -> 01100110 -> 0x66
883 case 4: return 0xa6; // 0100 -> 0010 -> 10100110 -> 0xa6
884 case 3: return 0x5a; // 0011 -> 1100 -> 01011010 -> 0x5a
885 case 2: return 0x9a; // 0010 -> 0100 -> 10011010 -> 0x9a
886 case 1: return 0x6a; // 0001 -> 1000 -> 01101010 -> 0x6a
887 default: return 0xaa; // 0000 -> 0000 -> 10101010 -> 0xaa
888
889 }
890}
1e262141 891
892//-----------------------------------------------------------------------------
893// Prepare tag messages
894//-----------------------------------------------------------------------------
895static void CodeIClassTagAnswer(const uint8_t *cmd, int len)
896{
645c960f
MHS		 897
898 /*
899 * SOF comprises 3 parts;
900 * * An unmodulated time of 56.64 us
901 * * 24 pulses of 423.75 KHz (fc/32)
902 * * A logic 1, which starts with an unmodulated time of 18.88us
903 * followed by 8 pulses of 423.75kHz (fc/32)
904 *
905 *
906 * EOF comprises 3 parts:
907 * - A logic 0 (which starts with 8 pulses of fc/32 followed by an unmodulated
908 * time of 18.88us.
909 * - 24 pulses of fc/32
910 * - An unmodulated time of 56.64 us
911 *
912 *
913 * A logic 0 starts with 8 pulses of fc/32
914 * followed by an unmodulated time of 256/fc (~18,88us).
915 *
916 * A logic 0 starts with unmodulated time of 256/fc (~18,88us) followed by
917 * 8 pulses of fc/32 (also 18.88us)
918 *
919 * The mode FPGA_HF_SIMULATOR_MODULATE_424K_8BIT which we use to simulate tag,
920 * works like this.
921 * - A 1-bit input to the FPGA becomes 8 pulses on 423.5kHz (fc/32) (18.88us).
922 * - A 0-bit inptu to the FPGA becomes an unmodulated time of 18.88us
923 *
6b038d19 924 * In this mode the SOF can be written as 00011101 = 0x1D
645c960f
MHS		 925 * The EOF can be written as 10111000 = 0xb8
926 * A logic 1 is 01
927 * A logic 0 is 10
928 *
929 * */
930
1e262141 931 int i;
932
933 ToSendReset();
934
935 // Send SOF
645c960f 936 ToSend[++ToSendMax] = 0x1D;
1e262141 937
938 for(i = 0; i < len; i++) {
1e262141 939 uint8_t b = cmd[i];
645c960f
MHS		 940 ToSend[++ToSendMax] = encode4Bits(b & 0xF); //Least significant half
941 ToSend[++ToSendMax] = encode4Bits((b >>4) & 0xF);//Most significant half
1e262141 942 }
943
944 // Send EOF
645c960f 945 ToSend[++ToSendMax] = 0xB8;
81012e67 946 //lastProxToAirDuration = 8*ToSendMax - 3*8 - 3*8;//Not counting zeroes in the beginning or end
1e262141 947 // Convert from last byte pos to length
948 ToSendMax++;
949}
950
951// Only SOF
952static void CodeIClassTagSOF()
953{
81012e67
MHS		 954 //So far a dummy implementation, not used
955 //int lastProxToAirDuration =0;
1e262141 956
81012e67 957 ToSendReset();
1e262141 958 // Send SOF
645c960f 959 ToSend[++ToSendMax] = 0x1D;
81012e67
MHS		 960// lastProxToAirDuration = 8*ToSendMax - 3*8;//Not counting zeroes in the beginning
961
1e262141 962 // Convert from last byte pos to length
963 ToSendMax++;
964}
55eaed8f 965
9f6e9d15 966int doIClassSimulation(uint8_t csn[], int breakAfterMacReceived, uint8_t *reader_mac_buf);
ff7bb4ef
MHS		 967/**
968 * @brief SimulateIClass simulates an iClass card.
969 * @param arg0 type of simulation
970 * - 0 uses the first 8 bytes in usb data as CSN
971 * - 2 "dismantling iclass"-attack. This mode iterates through all CSN's specified
972 * in the usb data. This mode collects MAC from the reader, in order to do an offline
973 * attack on the keys. For more info, see "dismantling iclass" and proxclone.com.
974 * - Other : Uses the default CSN (031fec8af7ff12e0)
975 * @param arg1 - number of CSN's contained in datain (applicable for mode 2 only)
976 * @param arg2
977 * @param datain
978 */
979void SimulateIClass(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain)
1e262141 980{
ff7bb4ef
MHS		 981 uint32_t simType = arg0;
982 uint32_t numberOfCSNS = arg1;
7cc204bf 983 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1e262141 984
ff7bb4ef
MHS		 985 // Enable and clear the trace
986 iso14a_set_tracing(TRUE);
987 iso14a_clear_trace();
81cd0474 988
ff7bb4ef 989 uint8_t csn_crc[] = { 0x03, 0x1f, 0xec, 0x8a, 0xf7, 0xff, 0x12, 0xe0, 0x00, 0x00 };
ff7bb4ef
MHS		 990 if(simType == 0) {
991 // Use the CSN from commandline
992 memcpy(csn_crc, datain, 8);
9f6e9d15 993 doIClassSimulation(csn_crc,0,NULL);
ff7bb4ef
MHS		 994 }else if(simType == 1)
995 {
9f6e9d15 996 doIClassSimulation(csn_crc,0,NULL);
ff7bb4ef
MHS		 997 }
998 else if(simType == 2)
999 {
9f6e9d15 1000
7b941c8d 1001 uint8_t mac_responses[USB_CMD_DATA_SIZE] = { 0 };
eabba3df 1002 Dbprintf("Going into attack mode, %d CSNS sent", numberOfCSNS);
ff7bb4ef
MHS		 1003 // In this mode, a number of csns are within datain. We'll simulate each one, one at a time
1004 // in order to collect MAC's from the reader. This can later be used in an offlne-attack
1005 // in order to obtain the keys, as in the "dismantling iclass"-paper.
9f6e9d15
MHS		 1006 int i = 0;
1007 for( ; i < numberOfCSNS && i*8+8 < USB_CMD_DATA_SIZE; i++)
ff7bb4ef
MHS		 1008 {
1009 // The usb data is 512 bytes, fitting 65 8-byte CSNs in there.
1010
1011 memcpy(csn_crc, datain+(i*8), 8);
6116c796 1012 if(doIClassSimulation(csn_crc,1,mac_responses+i*8))
f83cc126 1013 {
645c960f 1014 cmd_send(CMD_ACK,CMD_SIMULATE_TAG_ICLASS,i,0,mac_responses,i*8);
f83cc126
MHS		 1015 return; // Button pressed
1016 }
ff7bb4ef 1017 }
9f6e9d15
MHS		 1018 cmd_send(CMD_ACK,CMD_SIMULATE_TAG_ICLASS,i,0,mac_responses,i*8);
1019
81012e67
MHS		 1020 }
1021 else{
ff7bb4ef
MHS		 1022 // We may want a mode here where we hardcode the csns to use (from proxclone).
1023 // That will speed things up a little, but not required just yet.
1024 Dbprintf("The mode is not implemented, reserved for future use");
1025 }
9f6e9d15 1026 Dbprintf("Done...");
ff7bb4ef
MHS		 1027
1028}
1029/**
1030 * @brief Does the actual simulation
1031 * @param csn - csn to use
1032 * @param breakAfterMacReceived if true, returns after reader MAC has been received.
1033 */
9f6e9d15 1034int doIClassSimulation(uint8_t csn[], int breakAfterMacReceived, uint8_t *reader_mac_buf)
ff7bb4ef 1035{
55eaed8f 1036
1e262141 1037 // CSN followed by two CRC bytes
55eaed8f 1038 uint8_t response1[] = { 0x0F} ;
1e262141 1039 uint8_t response2[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
ff7bb4ef
MHS		 1040 uint8_t response3[] = { 0,0,0,0,0,0,0,0,0,0};
1041 memcpy(response3,csn,sizeof(response3));
f83cc126 1042 Dbprintf("Simulating CSN %02x%02x%02x%02x%02x%02x%02x%02x",csn[0],csn[1],csn[2],csn[3],csn[4],csn[5],csn[6],csn[7]);
1e262141 1043 // e-Purse
1044 uint8_t response4[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1e262141 1045
1e262141 1046 // Construct anticollision-CSN
912a3e94 1047 rotateCSN(response3,response2);
1e262141 1048
1049 // Compute CRC on both CSNs
1050 ComputeCrc14443(CRC_ICLASS, response2, 8, &response2[8], &response2[9]);
1051 ComputeCrc14443(CRC_ICLASS, response3, 8, &response3[8], &response3[9]);
1052
ff7bb4ef 1053 int exitLoop = 0;
1e262141 1054 // Reader 0a
1055 // Tag 0f
1056 // Reader 0c
1057 // Tag anticoll. CSN
1058 // Reader 81 anticoll. CSN
1059 // Tag CSN
1060
55eaed8f
MHS		 1061 uint8_t *modulated_response;
1062 int modulated_response_size;
1063 uint8_t* trace_data = NULL;
1064 int trace_data_size = 0;
1065 //uint8_t sof = 0x0f;
1e262141 1066
645c960f 1067 // Respond SOF -- takes 1 bytes
81cd0474 1068 uint8_t *resp1 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);
1e262141 1069 int resp1Len;
1070
1071 // Anticollision CSN (rotated CSN)
645c960f
MHS		 1072 // 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
1073 uint8_t *resp2 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 2);
1e262141 1074 int resp2Len;
1075
1076 // CSN
645c960f
MHS		 1077 // 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
1078 uint8_t *resp3 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 30);
912a3e94 1079 int resp3Len;
1e262141 1080
1081 // e-Purse
645c960f
MHS		 1082 // 18: Takes 2 bytes for SOF/EOF and 8 * 2 = 16 bytes (2 bytes/byte)
1083 uint8_t *resp4 = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + 60);
1e262141 1084 int resp4Len;
1085
1086 // + 1720..
ff7bb4ef 1087 uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);
6a1f2d82 1088 memset(receivedCmd, 0x44, MAX_FRAME_SIZE);
1e262141 1089 int len;
1090
1e262141 1091 // Prepare card messages
1092 ToSendMax = 0;
1093
1094 // First card answer: SOF
1095 CodeIClassTagSOF();
1096 memcpy(resp1, ToSend, ToSendMax); resp1Len = ToSendMax;
1097
1098 // Anticollision CSN
1099 CodeIClassTagAnswer(response2, sizeof(response2));
1100 memcpy(resp2, ToSend, ToSendMax); resp2Len = ToSendMax;
1101
1102 // CSN
1103 CodeIClassTagAnswer(response3, sizeof(response3));
912a3e94 1104 memcpy(resp3, ToSend, ToSendMax); resp3Len = ToSendMax;
1e262141 1105
1106 // e-Purse
1107 CodeIClassTagAnswer(response4, sizeof(response4));
1108 memcpy(resp4, ToSend, ToSendMax); resp4Len = ToSendMax;
1109
e3dc1e4c
MHS		 1110
1111 // Start from off (no field generated)
fa541aca
MHS		 1112 //FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1113 //SpinDelay(200);
1114 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1115 SpinDelay(100);
1116 StartCountSspClk();
1e262141 1117 // We need to listen to the high-frequency, peak-detected path.
1118 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1119 FpgaSetupSsc();
1120
1121 // To control where we are in the protocol
1e262141 1122 int cmdsRecvd = 0;
81012e67
MHS		 1123 uint32_t time_0 = GetCountSspClk();
1124 uint32_t t2r_time =0;
1125 uint32_t r2t_time =0;
912a3e94 1126
1e262141 1127 LED_A_ON();
f83cc126 1128 bool buttonPressed = false;
9f6e9d15 1129
ff7bb4ef 1130 while(!exitLoop) {
81012e67 1131
1e262141 1132 LED_B_OFF();
e3dc1e4c
MHS		 1133 //Signal tracer
1134 // Can be used to get a trigger for an oscilloscope..
1135 LED_C_OFF();
3fe4ff4f 1136
1e262141 1137 if(!GetIClassCommandFromReader(receivedCmd, &len, 100)) {
f83cc126 1138 buttonPressed = true;
1e262141 1139 break;
81cd0474 1140 }
81012e67 1141 r2t_time = GetCountSspClk();
e3dc1e4c
MHS		 1142 //Signal tracer
1143 LED_C_ON();
1e262141 1144
81cd0474 1145 // Okay, look at the command now.
f83cc126 1146 if(receivedCmd[0] == 0x0a ) {
1e262141 1147 // Reader in anticollission phase
55eaed8f
MHS		 1148 modulated_response = resp1; modulated_response_size = resp1Len; //order = 1;
1149 trace_data = response1;
1150 trace_data_size = sizeof(response1);
1e262141 1151 } else if(receivedCmd[0] == 0x0c) {
1152 // Reader asks for anticollission CSN
55eaed8f
MHS		 1153 modulated_response = resp2; modulated_response_size = resp2Len; //order = 2;
1154 trace_data = response2;
1155 trace_data_size = sizeof(response2);
1e262141 1156 //DbpString("Reader requests anticollission CSN:");
1157 } else if(receivedCmd[0] == 0x81) {
1158 // Reader selects anticollission CSN.
1159 // Tag sends the corresponding real CSN
55eaed8f
MHS		 1160 modulated_response = resp3; modulated_response_size = resp3Len; //order = 3;
1161 trace_data = response3;
1162 trace_data_size = sizeof(response3);
1e262141 1163 //DbpString("Reader selects anticollission CSN:");
1164 } else if(receivedCmd[0] == 0x88) {
1165 // Read e-purse (88 02)
55eaed8f
MHS		 1166 modulated_response = resp4; modulated_response_size = resp4Len; //order = 4;
1167 trace_data = response4;
1168 trace_data_size = sizeof(response4);
1e262141 1169 LED_B_ON();
1170 } else if(receivedCmd[0] == 0x05) {
1171 // Reader random and reader MAC!!!
1e262141 1172 // Do not respond
26c0d833 1173 // We do not know what to answer, so lets keep quiet
55eaed8f
MHS		 1174 modulated_response = resp1; modulated_response_size = 0; //order = 5;
1175 trace_data = NULL;
1176 trace_data_size = 0;
ff7bb4ef 1177 if (breakAfterMacReceived){
ff7bb4ef 1178 // dbprintf:ing ...
6116c796
MHS		 1179 Dbprintf("CSN: %02x %02x %02x %02x %02x %02x %02x %02x"
1180 ,csn[0],csn[1],csn[2],csn[3],csn[4],csn[5],csn[6],csn[7]);
ff7bb4ef 1181 Dbprintf("RDR: (len=%02d): %02x %02x %02x %02x %02x %02x %02x %02x %02x",len,
6116c796 1182 receivedCmd[0], receivedCmd[1], receivedCmd[2],
ff7bb4ef
MHS		 1183 receivedCmd[3], receivedCmd[4], receivedCmd[5],
1184 receivedCmd[6], receivedCmd[7], receivedCmd[8]);
9f6e9d15
MHS		 1185 if (reader_mac_buf != NULL)
1186 {
1187 memcpy(reader_mac_buf,receivedCmd+1,8);
1188 }
ff7bb4ef
MHS		 1189 exitLoop = true;
1190 }
1e262141 1191 } else if(receivedCmd[0] == 0x00 && len == 1) {
1192 // Reader ends the session
55eaed8f
MHS		 1193 modulated_response = resp1; modulated_response_size = 0; //order = 0;
1194 trace_data = NULL;
1195 trace_data_size = 0;
81cd0474 1196 } else {
17cba269 1197 //#db# Unknown command received from reader (len=5): 26 1 0 f6 a 44 44 44 44
1e262141 1198 // Never seen this command before
1199 Dbprintf("Unknown command received from reader (len=%d): %x %x %x %x %x %x %x %x %x",
1200 len,
1201 receivedCmd[0], receivedCmd[1], receivedCmd[2],
1202 receivedCmd[3], receivedCmd[4], receivedCmd[5],
1203 receivedCmd[6], receivedCmd[7], receivedCmd[8]);
1204 // Do not respond
55eaed8f
MHS		 1205 modulated_response = resp1; modulated_response_size = 0; //order = 0;
1206 trace_data = NULL;
1207 trace_data_size = 0;
1e262141 1208 }
1209
81012e67
MHS		 1210 if(cmdsRecvd > 100) {
1211 //DbpString("100 commands later...");
9f6e9d15 1212 //break;
1e262141 1213 }
1214 else {
1215 cmdsRecvd++;
1216 }
55eaed8f 1217 /**
6b038d19 1218 A legit tag has about 380us delay between reader EOT and tag SOF.
55eaed8f
MHS		 1219 **/
1220 if(modulated_response_size > 0) {
645c960f 1221 SendIClassAnswer(modulated_response, modulated_response_size, 1);
81012e67 1222 t2r_time = GetCountSspClk();
81cd0474 1223 }
f83cc126 1224
81cd0474 1225 if (tracing) {
6a1f2d82 1226 uint8_t parity[MAX_PARITY_SIZE];
1227 GetParity(receivedCmd, len, parity);
1228 LogTrace(receivedCmd,len, (r2t_time-time_0)<< 4, (r2t_time-time_0) << 4, parity, TRUE);
17cba269 1229
55eaed8f
MHS		 1230 if (trace_data != NULL) {
1231 GetParity(trace_data, trace_data_size, parity);
1232 LogTrace(trace_data, trace_data_size, (t2r_time-time_0) << 4, (t2r_time-time_0) << 4, parity, FALSE);
17cba269 1233 }
81012e67
MHS		 1234 if(!tracing) {
1235 DbpString("Trace full");
1236 //break;
1237 }
1238
81cd0474 1239 }
6a1f2d82 1240 memset(receivedCmd, 0x44, MAX_FRAME_SIZE);
81cd0474 1241 }
1e262141 1242
9f6e9d15 1243 //Dbprintf("%x", cmdsRecvd);
1e262141 1244 LED_A_OFF();
1245 LED_B_OFF();
7b941c8d
MHS		 1246 LED_C_OFF();
1247
f83cc126
MHS		 1248 if(buttonPressed)
1249 {
1250 DbpString("Button pressed");
1251 }
f83cc126 1252 return buttonPressed;
1e262141 1253}
1254
1255static int SendIClassAnswer(uint8_t *resp, int respLen, int delay)
1256{
e3dc1e4c 1257 int i = 0, d=0;//, u = 0, d = 0;
1e262141 1258 uint8_t b = 0;
e3dc1e4c 1259
645c960f
MHS		 1260 //FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K);
1261 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K_8BIT);
e3dc1e4c 1262
1e262141 1263 AT91C_BASE_SSC->SSC_THR = 0x00;
1264 FpgaSetupSsc();
e3dc1e4c
MHS		 1265 while(!BUTTON_PRESS()) {
1266 if((AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)){
1267 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1e262141 1268 }
e3dc1e4c
MHS		 1269 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)){
1270 b = 0x00;
1e262141 1271 if(d < delay) {
1e262141 1272 d++;
1273 }
e3dc1e4c
MHS		 1274 else {
1275 if( i < respLen){
1276 b = resp[i];
1277 //Hack
1278 //b = 0xAC;
1279 }
1280 i++;
1e262141 1281 }
1282 AT91C_BASE_SSC->SSC_THR = b;
1e262141 1283 }
e3dc1e4c 1284
645c960f
MHS		 1285// if (i > respLen +4) break;
1286 if (i > respLen +1) break;
1e262141 1287 }
1288
1289 return 0;
1290}
1291
1292/// THE READER CODE
1293
1294//-----------------------------------------------------------------------------
1295// Transmit the command (to the tag) that was placed in ToSend[].
1296//-----------------------------------------------------------------------------
1297static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait)
1298{
1299 int c;
1e262141 1300 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1301 AT91C_BASE_SSC->SSC_THR = 0x00;
1302 FpgaSetupSsc();
1303
1304 if (wait)
2ed270a8
MHS		 1305 {
1306 if(*wait < 10) *wait = 10;
1307
1308 for(c = 0; c < *wait;) {
1309 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1310 AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing!
1311 c++;
1312 }
1313 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1314 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1315 (void)r;
1316 }
1317 WDT_HIT();
1318 }
1319
1320 }
1e262141 1321
1e262141 1322
1323 uint8_t sendbyte;
1324 bool firstpart = TRUE;
1325 c = 0;
1326 for(;;) {
1327 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1328
1329 // DOUBLE THE SAMPLES!
1330 if(firstpart) {
1331 sendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4);
1332 }
1333 else {
1334 sendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4);
1335 c++;
1336 }
1337 if(sendbyte == 0xff) {
1338 sendbyte = 0xfe;
1339 }
1340 AT91C_BASE_SSC->SSC_THR = sendbyte;
1341 firstpart = !firstpart;
1342
1343 if(c >= len) {
1344 break;
1345 }
1346 }
1347 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1348 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1349 (void)r;
1350 }
1351 WDT_HIT();
1352 }
1353 if (samples) *samples = (c + *wait) << 3;
1354}
1355
1356
1357//-----------------------------------------------------------------------------
1358// Prepare iClass reader command to send to FPGA
1359//-----------------------------------------------------------------------------
1360void CodeIClassCommand(const uint8_t * cmd, int len)
1361{
1362 int i, j, k;
1363 uint8_t b;
1364
1365 ToSendReset();
1366
1367 // Start of Communication: 1 out of 4
1368 ToSend[++ToSendMax] = 0xf0;
1369 ToSend[++ToSendMax] = 0x00;
1370 ToSend[++ToSendMax] = 0x0f;
1371 ToSend[++ToSendMax] = 0x00;
1372
1373 // Modulate the bytes
1374 for (i = 0; i < len; i++) {
1375 b = cmd[i];
1376 for(j = 0; j < 4; j++) {
1377 for(k = 0; k < 4; k++) {
e3dc1e4c
MHS		 1378 if(k == (b & 3)) {
1379 ToSend[++ToSendMax] = 0x0f;
1380 }
1381 else {
1382 ToSend[++ToSendMax] = 0x00;
1383 }
1e262141 1384 }
1385 b >>= 2;
1386 }
1387 }
1388
1389 // End of Communication
1390 ToSend[++ToSendMax] = 0x00;
1391 ToSend[++ToSendMax] = 0x00;
1392 ToSend[++ToSendMax] = 0xf0;
1393 ToSend[++ToSendMax] = 0x00;
1394
1395 // Convert from last character reference to length
1396 ToSendMax++;
1397}
1398
1399void ReaderTransmitIClass(uint8_t* frame, int len)
1400{
6a1f2d82 1401 int wait = 0;
1402 int samples = 0;
1403
1404 // This is tied to other size changes
6a1f2d82 1405 CodeIClassCommand(frame,len);
1406
1407 // Select the card
1408 TransmitIClassCommand(ToSend, ToSendMax, &samples, &wait);
1409 if(trigger)
1410 LED_A_ON();
1411
1412 // Store reader command in buffer
1413 if (tracing) {
1414 uint8_t par[MAX_PARITY_SIZE];
1415 GetParity(frame, len, par);
1416 LogTrace(frame, len, rsamples, rsamples, par, TRUE);
1417 }
1e262141 1418}
1419
1420//-----------------------------------------------------------------------------
1421// Wait a certain time for tag response
1422// If a response is captured return TRUE
1423// If it takes too long return FALSE
1424//-----------------------------------------------------------------------------
1425static int GetIClassAnswer(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed) //uint8_t *buffer
1426{
1427 // buffer needs to be 512 bytes
1428 int c;
1429
1430 // Set FPGA mode to "reader listen mode", no modulation (listen
1431 // only, since we are receiving, not transmitting).
1432 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1433
1434 // Now get the answer from the card
1435 Demod.output = receivedResponse;
1436 Demod.len = 0;
1437 Demod.state = DEMOD_UNSYNCD;
1438
1439 uint8_t b;
1440 if (elapsed) *elapsed = 0;
1441
1442 bool skip = FALSE;
1443
1444 c = 0;
1445 for(;;) {
1446 WDT_HIT();
1447
1448 if(BUTTON_PRESS()) return FALSE;
1449
1450 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1451 AT91C_BASE_SSC->SSC_THR = 0x00; // To make use of exact timing of next command from reader!!
1452 if (elapsed) (*elapsed)++;
1453 }
1454 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1455 if(c < timeout) { c++; } else { return FALSE; }
1456 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1457 skip = !skip;
1458 if(skip) continue;
3fe4ff4f 1459
1e262141 1460 if(ManchesterDecoding(b & 0x0f)) {
1461 *samples = c << 3;
1462 return TRUE;
1463 }
1464 }
1465 }
1466}
1467
1468int ReaderReceiveIClass(uint8_t* receivedAnswer)
1469{
1470 int samples = 0;
1471 if (!GetIClassAnswer(receivedAnswer,160,&samples,0)) return FALSE;
7bc95e2e 1472 rsamples += samples;
6a1f2d82 1473 if (tracing) {
1474 uint8_t parity[MAX_PARITY_SIZE];
1475 GetParity(receivedAnswer, Demod.len, parity);
1476 LogTrace(receivedAnswer,Demod.len,rsamples,rsamples,parity,FALSE);
1477 }
1e262141 1478 if(samples == 0) return FALSE;
1479 return Demod.len;
1480}
1481
aa41c605
MHS		 1482void setupIclassReader()
1483{
1484 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1485 // Reset trace buffer
1486 iso14a_set_tracing(TRUE);
1487 iso14a_clear_trace();
1488
1489 // Setup SSC
1490 FpgaSetupSsc();
1491 // Start from off (no field generated)
1492 // Signal field is off with the appropriate LED
1493 LED_D_OFF();
1494 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1495 SpinDelay(200);
1496
1497 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1498
1499 // Now give it time to spin up.
1500 // Signal field is on with the appropriate LED
1501 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1502 SpinDelay(200);
1503 LED_A_ON();
1504
1505}
1506
c8dd9b09
MHS		 1507size_t sendCmdGetResponseWithRetries(uint8_t* command, size_t cmdsize, uint8_t* resp, uint8_t expected_size, uint8_t retries)
1508{
1509 while(retries-- > 0)
1510 {
1511 ReaderTransmitIClass(command, cmdsize);
1512 if(expected_size == ReaderReceiveIClass(resp)){
1513 return 0;
1514 }
1515 }
1516 return 1;//Error
1517}
1518
1519/**
1520 * @brief Talks to an iclass tag, sends the commands to get CSN and CC.
1521 * @param card_data where the CSN and CC are stored for return
1522 * @return 0 = fail
1523 * 1 = Got CSN
1524 * 2 = Got CSN and CC
1525 */
1526uint8_t handshakeIclassTag(uint8_t *card_data)
1527{
1528 static uint8_t act_all[] = { 0x0a };
1529 static uint8_t identify[] = { 0x0c };
1530 static uint8_t select[] = { 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1531 static uint8_t readcheck_cc[]= { 0x88, 0x02 };
1532 uint8_t *resp = (((uint8_t *)BigBuf) + RECV_RESP_OFFSET);
1533
1534 uint8_t read_status = 0;
1535
1536 // Send act_all
1537 ReaderTransmitIClass(act_all, 1);
1538 // Card present?
1539 if(!ReaderReceiveIClass(resp)) return read_status;//Fail
1540 //Send Identify
1541 ReaderTransmitIClass(identify, 1);
1542 //We expect a 10-byte response here, 8 byte anticollision-CSN and 2 byte CRC
1543 uint8_t len = ReaderReceiveIClass(resp);
1544 if(len != 10) return read_status;//Fail
1545
1546 //Copy the Anti-collision CSN to our select-packet
1547 memcpy(&select[1],resp,8);
1548 //Select the card
1549 ReaderTransmitIClass(select, sizeof(select));
1550 //We expect a 10-byte response here, 8 byte CSN and 2 byte CRC
1551 len = ReaderReceiveIClass(resp);
1552 if(len != 10) return read_status;//Fail
1553
1554 //Success - level 1, we got CSN
1555 //Save CSN in response data
1556 memcpy(card_data,resp,8);
1557
1558 //Flag that we got to at least stage 1, read CSN
1559 read_status = 1;
1560
1561 // Card selected, now read e-purse (cc)
1562 ReaderTransmitIClass(readcheck_cc, sizeof(readcheck_cc));
1563 if(ReaderReceiveIClass(resp) == 8) {
1564 //Save CC (e-purse) in response data
1565 memcpy(card_data+8,resp,8);
1566
1567 //Got both
1568 read_status = 2;
1569 }
1570
1571 return read_status;
1572}
1573
1e262141 1574// Reader iClass Anticollission
1575void ReaderIClass(uint8_t arg0) {
1e262141 1576
aa41c605
MHS		 1577 uint8_t card_data[24]={0};
1578 uint8_t last_csn[8]={0};
6a1f2d82 1579
aa41c605
MHS		 1580 int read_status= 0;
1581 bool abort_after_read = arg0 & FLAG_ICLASS_READER_ONLY_ONCE;
c8dd9b09 1582 bool get_cc = arg0 & FLAG_ICLASS_READER_GET_CC;
1e262141 1583
aa41c605 1584 setupIclassReader();
1e262141 1585
aa41c605
MHS		 1586 size_t datasize = 0;
1587 while(!BUTTON_PRESS())
1588 {
1e262141 1589
c8dd9b09
MHS		 1590 if(traceLen > TRACE_SIZE) {
1591 DbpString("Trace full");
1592 break;
1593 }
1594 WDT_HIT();
4ab4336a 1595
c8dd9b09 1596 read_status = handshakeIclassTag(card_data);
2e9d4b3f 1597
c8dd9b09
MHS		 1598 if(read_status == 0) continue;
1599 if(read_status == 1) datasize = 8;
1600 if(read_status == 2) datasize = 16;
1601
1602 LED_B_ON();
1603 //Send back to client, but don't bother if we already sent this
1604 if(memcmp(last_csn, card_data, 8) != 0)
1605 {
2e9d4b3f 1606
c8dd9b09
MHS		 1607 if(!get_cc || (get_cc && read_status == 2))
1608 {
1609 cmd_send(CMD_ACK,read_status,0,0,card_data,datasize);
1610 if(abort_after_read) {
1611 LED_A_OFF();
1612 return;
1613 }
1614 //Save that we already sent this....
1615 memcpy(last_csn, card_data, 8);
1616 }
1617 //If 'get_cc' was specified and we didn't get a CC, we'll just keep trying...
1618 }
1619 LED_B_OFF();
1620 }
1621 cmd_send(CMD_ACK,0,0,0,card_data, 0);
aa41c605 1622 LED_A_OFF();
cee5a30d 1623}
1624
c3963755 1625void ReaderIClass_Replay(uint8_t arg0, uint8_t *MAC) {
c8dd9b09 1626
cb29e00a 1627 uint8_t card_data[USB_CMD_DATA_SIZE]={0};
39d3ce5d
MHS		 1628 uint16_t block_crc_LUT[255] = {0};
1629
1630 {//Generate a lookup table for block crc
1631 for(int block = 0; block < 255; block++){
1632 char bl = block;
1633 block_crc_LUT[block] = iclass_crc16(&bl ,1);
1634 }
1635 }
1636 //Dbprintf("Lookup table: %02x %02x %02x" ,block_crc_LUT[0],block_crc_LUT[1],block_crc_LUT[2]);
c8dd9b09 1637
c3963755 1638 uint8_t check[] = { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1639 uint8_t read[] = { 0x0c, 0x00, 0x00, 0x00 };
1640
fecd8202 1641 uint16_t crc = 0;
c3963755 1642 uint8_t cardsize=0;
c3963755 1643 uint8_t mem=0;
1644
1645 static struct memory_t{
1646 int k16;
1647 int book;
1648 int k2;
1649 int lockauth;
1650 int keyaccess;
1651 } memory;
1652
6a1f2d82 1653 uint8_t* resp = (((uint8_t *)BigBuf) + RECV_RESP_OFFSET);
1654
9b82de75 1655 setupIclassReader();
c3963755 1656
c3963755 1657
c8dd9b09 1658 while(!BUTTON_PRESS()) {
c3963755 1659
39d3ce5d
MHS		 1660 WDT_HIT();
1661
c3963755 1662 if(traceLen > TRACE_SIZE) {
1663 DbpString("Trace full");
1664 break;
1665 }
1666
c8dd9b09
MHS		 1667 uint8_t read_status = handshakeIclassTag(card_data);
1668 if(read_status < 2) continue;
1669
1670 //for now replay captured auth (as cc not updated)
1671 memcpy(check+5,MAC,4);
1672
1673 if(sendCmdGetResponseWithRetries(check, sizeof(check),resp, 4, 5))
1674 {
1675 Dbprintf("Error: Authentication Fail!");
1676 continue;
1677 }
1678
39d3ce5d
MHS		 1679 //first get configuration block (block 1)
1680 crc = block_crc_LUT[1];
c8dd9b09 1681 read[1]=1;
c8dd9b09
MHS		 1682 read[2] = crc >> 8;
1683 read[3] = crc & 0xff;
1684
1685 if(sendCmdGetResponseWithRetries(read, sizeof(read),resp, 10, 10))
1686 {
39d3ce5d 1687 Dbprintf("Dump config (block 1) failed");
c8dd9b09
MHS		 1688 continue;
1689 }
1690
1691 mem=resp[5];
1692 memory.k16= (mem & 0x80);
1693 memory.book= (mem & 0x20);
1694 memory.k2= (mem & 0x8);
1695 memory.lockauth= (mem & 0x2);
1696 memory.keyaccess= (mem & 0x1);
1697
1698 cardsize = memory.k16 ? 255 : 32;
1699 WDT_HIT();
cb29e00a
MHS		 1700 //Set card_data to all zeroes, we'll fill it with data
1701 memset(card_data,0x0,USB_CMD_DATA_SIZE);
1702 uint8_t failedRead =0;
1703 uint8_t stored_data_length =0;
c8dd9b09 1704 //then loop around remaining blocks
39d3ce5d 1705 for(int block=0; block < cardsize; block++){
c8dd9b09
MHS		 1706
1707 read[1]= block;
39d3ce5d 1708 crc = block_crc_LUT[block];
c8dd9b09
MHS		 1709 read[2] = crc >> 8;
1710 read[3] = crc & 0xff;
1711
1712 if(!sendCmdGetResponseWithRetries(read, sizeof(read), resp, 10, 10))
1713 {
1714 Dbprintf(" %02x: %02x %02x %02x %02x %02x %02x %02x %02x",
1715 block, resp[0], resp[1], resp[2],
1716 resp[3], resp[4], resp[5],
1717 resp[6], resp[7]);
1718
cb29e00a
MHS		 1719 //Fill up the buffer
1720 memcpy(card_data+stored_data_length,resp,8);
1721 stored_data_length += 8;
1722
1723 if(stored_data_length +8 > USB_CMD_DATA_SIZE)
1724 {//Time to send this off and start afresh
1725 cmd_send(CMD_ACK,
1726 stored_data_length,//data length
1727 failedRead,//Failed blocks?
1728 0,//Not used ATM
1729 card_data, stored_data_length);
1730 //reset
1731 stored_data_length = 0;
1732 failedRead = 0;
1733 }
1734
c8dd9b09 1735 }else{
cb29e00a
MHS		 1736 failedRead = 1;
1737 stored_data_length +=8;//Otherwise, data becomes misaligned
c8dd9b09 1738 Dbprintf("Failed to dump block %d", block);
c3963755 1739 }
1740 }
cb29e00a
MHS		 1741 //Send off any remaining data
1742 if(stored_data_length > 0)
1743 {
1744 cmd_send(CMD_ACK,
1745 stored_data_length,//data length
1746 failedRead,//Failed blocks?
1747 0,//Not used ATM
1748 card_data, stored_data_length);
1749 }
c8dd9b09
MHS		 1750 //If we got here, let's break
1751 break;
c3963755 1752 }
cb29e00a
MHS		 1753 //Signal end of transmission
1754 cmd_send(CMD_ACK,
1755 0,//data length
1756 0,//Failed blocks?
1757 0,//Not used ATM
1758 card_data, 0);
1759
c3963755 1760 LED_A_OFF();
1761}
1762
fecd8202 1763//2. Create Read method (cut-down from above) based off responses from 1.
1764// Since we have the MAC could continue to use replay function.
1765//3. Create Write method
1766/*
1767void IClass_iso14443A_write(uint8_t arg0, uint8_t blockNo, uint8_t *data, uint8_t *MAC) {
1768 uint8_t act_all[] = { 0x0a };
1769 uint8_t identify[] = { 0x0c };
1770 uint8_t select[] = { 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1771 uint8_t readcheck_cc[]= { 0x88, 0x02 };
1772 uint8_t check[] = { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1773 uint8_t read[] = { 0x0c, 0x00, 0x00, 0x00 };
1774 uint8_t write[] = { 0x87, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1775
1776 uint16_t crc = 0;
1777
6a1f2d82 1778 uint8_t* resp = (((uint8_t *)BigBuf) + 3560);
912a3e94 1779
fecd8202 1780 // Reset trace buffer
1781 memset(trace, 0x44, RECV_CMD_OFFSET);
1782 traceLen = 0;
1783
1784 // Setup SSC
1785 FpgaSetupSsc();
1786 // Start from off (no field generated)
1787 // Signal field is off with the appropriate LED
1788 LED_D_OFF();
1789 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1790 SpinDelay(200);
1791
1792 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1793
1794 // Now give it time to spin up.
1795 // Signal field is on with the appropriate LED
1796 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1797 SpinDelay(200);
1798
1799 LED_A_ON();
1800
1801 for(int i=0;i<1;i++) {
1802
1803 if(traceLen > TRACE_SIZE) {
1804 DbpString("Trace full");
1805 break;
1806 }
1807
1808 if (BUTTON_PRESS()) break;
1809
1810 // Send act_all
1811 ReaderTransmitIClass(act_all, 1);
1812 // Card present?
1813 if(ReaderReceiveIClass(resp)) {
1814 ReaderTransmitIClass(identify, 1);
1815 if(ReaderReceiveIClass(resp) == 10) {
1816 // Select card
1817 memcpy(&select[1],resp,8);
1818 ReaderTransmitIClass(select, sizeof(select));
1819
1820 if(ReaderReceiveIClass(resp) == 10) {
1821 Dbprintf(" Selected CSN: %02x %02x %02x %02x %02x %02x %02x %02x",
1822 resp[0], resp[1], resp[2],
1823 resp[3], resp[4], resp[5],
1824 resp[6], resp[7]);
1825 }
1826 // Card selected
1827 Dbprintf("Readcheck on Sector 2");
1828 ReaderTransmitIClass(readcheck_cc, sizeof(readcheck_cc));
1829 if(ReaderReceiveIClass(resp) == 8) {
1830 Dbprintf(" CC: %02x %02x %02x %02x %02x %02x %02x %02x",
1831 resp[0], resp[1], resp[2],
1832 resp[3], resp[4], resp[5],
1833 resp[6], resp[7]);
1834 }else return;
1835 Dbprintf("Authenticate");
1836 //for now replay captured auth (as cc not updated)
1837 memcpy(check+5,MAC,4);
1838 Dbprintf(" AA: %02x %02x %02x %02x",
1839 check[5], check[6], check[7],check[8]);
1840 ReaderTransmitIClass(check, sizeof(check));
1841 if(ReaderReceiveIClass(resp) == 4) {
1842 Dbprintf(" AR: %02x %02x %02x %02x",
1843 resp[0], resp[1], resp[2],resp[3]);
1844 }else {
1845 Dbprintf("Error: Authentication Fail!");
1846 return;
1847 }
1848 Dbprintf("Write Block");
1849
1850 //read configuration for max block number
1851 read_success=false;
1852 read[1]=1;
1853 uint8_t *blockno=&read[1];
1854 crc = iclass_crc16((char *)blockno,1);
1855 read[2] = crc >> 8;
1856 read[3] = crc & 0xff;
1857 while(!read_success){
1858 ReaderTransmitIClass(read, sizeof(read));
1859 if(ReaderReceiveIClass(resp) == 10) {
1860 read_success=true;
1861 mem=resp[5];
1862 memory.k16= (mem & 0x80);
1863 memory.book= (mem & 0x20);
1864 memory.k2= (mem & 0x8);
1865 memory.lockauth= (mem & 0x2);
1866 memory.keyaccess= (mem & 0x1);
1867
1868 }
1869 }
1870 if (memory.k16){
1871 cardsize=255;
1872 }else cardsize=32;
1873 //check card_size
1874
1875 memcpy(write+1,blockNo,1);
1876 memcpy(write+2,data,8);
1877 memcpy(write+10,mac,4);
1878 while(!send_success){
1879 ReaderTransmitIClass(write, sizeof(write));
1880 if(ReaderReceiveIClass(resp) == 10) {
1881 write_success=true;
1882 }
1883 }//
1884 }
1885 WDT_HIT();
1886 }
1887
1888 LED_A_OFF();
1889}*/
Proxmark3 GIT tracking
Impressum, Datenschutz