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d19929cb | 1 | //----------------------------------------------------------------------------- |
2 | // The way that we connect things in low-frequency simulation mode. In this | |
3 | // case just pass everything through to the ARM, which can bit-bang this | |
4 | // (because it is so slow). | |
5 | // | |
6 | // Jonathan Westhues, April 2006 | |
7 | //----------------------------------------------------------------------------- | |
8 | ||
9 | module lo_edge_detect( | |
7cc204bf | 10 | input pck0, input [7:0] pck_cnt, input pck_divclk, |
11 | output pwr_lo, output pwr_hi, | |
12 | output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4, | |
13 | input [7:0] adc_d, output adc_clk, | |
14 | output ssp_frame, input ssp_dout, output ssp_clk, | |
15 | input cross_lo, | |
16 | output dbg, | |
17 | input lf_field | |
d19929cb | 18 | ); |
d19929cb | 19 | |
7cc204bf | 20 | wire tag_modulation = ssp_dout & !lf_field; |
21 | wire reader_modulation = !ssp_dout & lf_field & pck_divclk; | |
d19929cb | 22 | |
23 | // No logic, straight through. | |
24 | assign pwr_oe1 = 1'b0; // not used in LF mode | |
25 | assign pwr_oe2 = tag_modulation; | |
26 | assign pwr_oe3 = tag_modulation; | |
27 | assign pwr_oe4 = tag_modulation; | |
28 | assign ssp_clk = cross_lo; | |
29 | assign pwr_lo = reader_modulation; | |
30 | assign pwr_hi = 1'b0; | |
31 | assign dbg = ssp_frame; | |
32 | ||
7cc204bf | 33 | assign adc_clk = ~pck_divclk; |
d19929cb | 34 | |
35 | // Toggle the output with hysteresis | |
36 | // Set to high if the ADC value is above 200 | |
37 | // Set to low if the ADC value is below 64 | |
38 | reg is_high; | |
39 | reg is_low; | |
40 | reg output_state; | |
41 | ||
42 | always @(posedge pck0) | |
43 | begin | |
7cc204bf | 44 | if((pck_cnt == 8'd7) && !pck_divclk) begin |
d19929cb | 45 | is_high = (adc_d >= 8'd190); |
46 | is_low = (adc_d <= 8'd70); | |
47 | end | |
48 | end | |
49 | ||
50 | always @(posedge is_high or posedge is_low) | |
51 | begin | |
52 | if(is_high) | |
53 | output_state <= 1'd1; | |
54 | else if(is_low) | |
55 | output_state <= 1'd0; | |
56 | end | |
57 | ||
58 | assign ssp_frame = output_state; | |
59 | ||
60 | endmodule | |
61 |