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Decreased BigBuff mem, some elf flasher fixes (needs more work) but flashing correctl...
[proxmark3-svn] / armsrc / lfops.c
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9bea179a 1//-----------------------------------------------------------------------------\r
2// Miscellaneous routines for low frequency tag operations.\r
3// Tags supported here so far are Texas Instruments (TI), HID\r
4// Also routines for raw mode reading/simulating of LF waveform\r
5//\r
6//-----------------------------------------------------------------------------\r
7#include <proxmark3.h>\r
8#include "apps.h"\r
0fa9ca5b 9#include "hitag2.h"\r
9bea179a 10#include "../common/crc16.c"\r
11\r
12void AcquireRawAdcSamples125k(BOOL at134khz)\r
13{\r
0d974852 14 if (at134khz)\r
9bea179a 15 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 16 else\r
9bea179a 17 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 18\r
19 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 20\r
21 // Connect the A/D to the peak-detected low-frequency path.\r
22 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
23\r
24 // Give it a bit of time for the resonant antenna to settle.\r
25 SpinDelay(50);\r
26\r
27 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
28 FpgaSetupSsc();\r
29\r
30 // Now call the acquisition routine\r
0d974852 31 DoAcquisition125k();\r
9bea179a 32}\r
33\r
34// split into two routines so we can avoid timing issues after sending commands //\r
0d974852 35void DoAcquisition125k(void)\r
9bea179a 36{\r
37 BYTE *dest = (BYTE *)BigBuf;\r
38 int n = sizeof(BigBuf);\r
39 int i;\r
6f5cb60c 40 \r
0d974852 41 memset(dest, 0, n);\r
9bea179a 42 i = 0;\r
43 for(;;) {\r
6f5cb60c 44 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {\r
6949aca9 45 AT91C_BASE_SSC->SSC_THR = 0x43;\r
9bea179a 46 LED_D_ON();\r
47 }\r
0d974852 48 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r
6949aca9 49 dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
9bea179a 50 i++;\r
51 LED_D_OFF();\r
6f5cb60c 52 if (i >= n) break;\r
9bea179a 53 }\r
54 }\r
1e1b3030 55 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",\r
56 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);\r
9bea179a 57}\r
58\r
0d974852 59void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, BYTE *command)\r
9bea179a 60{\r
61 BOOL at134khz;\r
62\r
0fa9ca5b 63 /* Make sure the tag is reset */\r
64 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
65 SpinDelay(2500);\r
66 \r
9bea179a 67 // see if 'h' was specified\r
0d974852 68 if (command[strlen((char *) command) - 1] == 'h')\r
69 at134khz = TRUE;\r
9bea179a 70 else\r
0d974852 71 at134khz = FALSE;\r
9bea179a 72\r
0d974852 73 if (at134khz)\r
9bea179a 74 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 75 else\r
9bea179a 76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 77\r
78 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 79\r
80 // Give it a bit of time for the resonant antenna to settle.\r
81 SpinDelay(50);\r
0fa9ca5b 82 // And a little more time for the tag to fully power up\r
83 SpinDelay(2000);\r
9bea179a 84\r
85 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
86 FpgaSetupSsc();\r
87\r
88 // now modulate the reader field\r
0d974852 89 while(*command != '\0' && *command != ' ') {\r
9bea179a 90 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
91 LED_D_OFF();\r
92 SpinDelayUs(delay_off);\r
0d974852 93 if (at134khz)\r
9bea179a 94 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 95 else\r
9bea179a 96 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 97\r
98 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 99 LED_D_ON();\r
0d974852 100 if(*(command++) == '0')\r
9bea179a 101 SpinDelayUs(period_0);\r
0d974852 102 else\r
9bea179a 103 SpinDelayUs(period_1);\r
0d974852 104 }\r
9bea179a 105 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
106 LED_D_OFF();\r
107 SpinDelayUs(delay_off);\r
0d974852 108 if (at134khz)\r
9bea179a 109 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 110 else\r
9bea179a 111 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 112\r
113 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 114\r
115 // now do the read\r
0d974852 116 DoAcquisition125k();\r
9bea179a 117}\r
118\r
7381e8f2 119/* blank r/w tag data stream\r
120...0000000000000000 01111111\r
1211010101010101010101010101010101010101010101010101010101010101010\r
1220011010010100001\r
12301111111\r
124101010101010101[0]000...\r
125\r
126[5555fe852c5555555555555555fe0000]\r
127*/\r
0d974852 128void ReadTItag(void)\r
7381e8f2 129{\r
130 // some hardcoded initial params\r
131 // when we read a TI tag we sample the zerocross line at 2Mhz\r
132 // TI tags modulate a 1 as 16 cycles of 123.2Khz\r
133 // TI tags modulate a 0 as 16 cycles of 134.2Khz\r
134 #define FSAMPLE 2000000\r
135 #define FREQLO 123200\r
136 #define FREQHI 134200\r
137\r
138 signed char *dest = (signed char *)BigBuf;\r
139 int n = sizeof(BigBuf);\r
140// int *dest = GraphBuffer;\r
141// int n = GraphTraceLen;\r
142\r
143 // 128 bit shift register [shift3:shift2:shift1:shift0]\r
144 DWORD shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;\r
145\r
146 int i, cycles=0, samples=0;\r
147 // how many sample points fit in 16 cycles of each frequency\r
148 DWORD sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;\r
149 // when to tell if we're close enough to one freq or another\r
150 DWORD threshold = (sampleslo - sampleshi + 1)>>1;\r
151\r
152 // TI tags charge at 134.2Khz\r
153 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
154\r
155 // Place FPGA in passthrough mode, in this mode the CROSS_LO line\r
156 // connects to SSP_DIN and the SSP_DOUT logic level controls\r
157 // whether we're modulating the antenna (high)\r
158 // or listening to the antenna (low)\r
159 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r
160\r
161 // get TI tag data into the buffer\r
162 AcquireTiType();\r
163\r
164 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
165\r
166 for (i=0; i<n-1; i++) {\r
167 // count cycles by looking for lo to hi zero crossings\r
168 if ( (dest[i]<0) && (dest[i+1]>0) ) {\r
169 cycles++;\r
170 // after 16 cycles, measure the frequency\r
171 if (cycles>15) {\r
172 cycles=0;\r
173 samples=i-samples; // number of samples in these 16 cycles\r
174\r
175 // TI bits are coming to us lsb first so shift them\r
176 // right through our 128 bit right shift register\r
177 shift0 = (shift0>>1) | (shift1 << 31);\r
178 shift1 = (shift1>>1) | (shift2 << 31);\r
179 shift2 = (shift2>>1) | (shift3 << 31);\r
180 shift3 >>= 1;\r
181\r
182 // check if the cycles fall close to the number\r
183 // expected for either the low or high frequency\r
184 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {\r
185 // low frequency represents a 1\r
186 shift3 |= (1<<31);\r
187 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {\r
188 // high frequency represents a 0\r
189 } else {\r
190 // probably detected a gay waveform or noise\r
191 // use this as gaydar or discard shift register and start again\r
192 shift3 = shift2 = shift1 = shift0 = 0;\r
193 }\r
194 samples = i;\r
195\r
196 // for each bit we receive, test if we've detected a valid tag\r
197\r
198 // if we see 17 zeroes followed by 6 ones, we might have a tag\r
199 // remember the bits are backwards\r
200 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {\r
201 // if start and end bytes match, we have a tag so break out of the loop\r
202 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {\r
203 cycles = 0xF0B; //use this as a flag (ugly but whatever)\r
204 break;\r
205 }\r
206 }\r
207 }\r
208 }\r
209 }\r
210\r
211 // if flag is set we have a tag\r
212 if (cycles!=0xF0B) {\r
213 DbpString("Info: No valid tag detected.");\r
214 } else {\r
215 // put 64 bit data into shift1 and shift0\r
216 shift0 = (shift0>>24) | (shift1 << 8);\r
217 shift1 = (shift1>>24) | (shift2 << 8);\r
218\r
219 // align 16 bit crc into lower half of shift2\r
220 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;\r
221\r
222 // if r/w tag, check ident match\r
223 if ( shift3&(1<<15) ) {\r
224 DbpString("Info: TI tag is rewriteable");\r
225 // only 15 bits compare, last bit of ident is not valid\r
226 if ( ((shift3>>16)^shift0)&0x7fff ) {\r
227 DbpString("Error: Ident mismatch!");\r
228 } else {\r
229 DbpString("Info: TI tag ident is valid");\r
230 }\r
231 } else {\r
232 DbpString("Info: TI tag is readonly");\r
233 }\r
234\r
235 // WARNING the order of the bytes in which we calc crc below needs checking\r
236 // i'm 99% sure the crc algorithm is correct, but it may need to eat the\r
237 // bytes in reverse or something\r
238 // calculate CRC\r
239 DWORD crc=0;\r
240\r
241 crc = update_crc16(crc, (shift0)&0xff);\r
242 crc = update_crc16(crc, (shift0>>8)&0xff);\r
243 crc = update_crc16(crc, (shift0>>16)&0xff);\r
244 crc = update_crc16(crc, (shift0>>24)&0xff);\r
245 crc = update_crc16(crc, (shift1)&0xff);\r
246 crc = update_crc16(crc, (shift1>>8)&0xff);\r
247 crc = update_crc16(crc, (shift1>>16)&0xff);\r
248 crc = update_crc16(crc, (shift1>>24)&0xff);\r
249\r
1e1b3030 250 Dbprintf("Info: Tag data: %x%08x, crc=%x",\r
6f5cb60c 251 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);\r
7381e8f2 252 if (crc != (shift2&0xffff)) {\r
a9bc033b 253 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);\r
7381e8f2 254 } else {\r
255 DbpString("Info: CRC is good");\r
256 }\r
257 }\r
258}\r
259\r
260void WriteTIbyte(BYTE b)\r
261{\r
262 int i = 0;\r
263\r
264 // modulate 8 bits out to the antenna\r
265 for (i=0; i<8; i++)\r
266 {\r
267 if (b&(1<<i)) {\r
268 // stop modulating antenna\r
6949aca9 269 LOW(GPIO_SSC_DOUT);\r
7381e8f2 270 SpinDelayUs(1000);\r
271 // modulate antenna\r
6949aca9 272 HIGH(GPIO_SSC_DOUT);\r
7381e8f2 273 SpinDelayUs(1000);\r
274 } else {\r
275 // stop modulating antenna\r
6949aca9 276 LOW(GPIO_SSC_DOUT);\r
7381e8f2 277 SpinDelayUs(300);\r
278 // modulate antenna\r
6949aca9 279 HIGH(GPIO_SSC_DOUT);\r
7381e8f2 280 SpinDelayUs(1700);\r
281 }\r
282 }\r
283}\r
284\r
9bea179a 285void AcquireTiType(void)\r
286{\r
7381e8f2 287 int i, j, n;\r
9bea179a 288 // tag transmission is <20ms, sampling at 2M gives us 40K samples max\r
289 // each sample is 1 bit stuffed into a DWORD so we need 1250 DWORDS\r
7381e8f2 290 #define TIBUFLEN 1250\r
9bea179a 291\r
292 // clear buffer\r
293 memset(BigBuf,0,sizeof(BigBuf));\r
294\r
295 // Set up the synchronous serial port\r
6949aca9 296 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;\r
297 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;\r
9bea179a 298\r
299 // steal this pin from the SSP and use it to control the modulation\r
6949aca9 300 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r
0d974852 301 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
9bea179a 302\r
6949aca9 303 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;\r
304 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;\r
9bea179a 305\r
6949aca9 306 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long\r
307 // 48/2 = 24 MHz clock must be divided by 12\r
308 AT91C_BASE_SSC->SSC_CMR = 12;\r
9bea179a 309\r
6949aca9 310 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);\r
311 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;\r
312 AT91C_BASE_SSC->SSC_TCMR = 0;\r
313 AT91C_BASE_SSC->SSC_TFMR = 0;\r
9bea179a 314\r
315 LED_D_ON();\r
316\r
317 // modulate antenna\r
6949aca9 318 HIGH(GPIO_SSC_DOUT);\r
9bea179a 319\r
320 // Charge TI tag for 50ms.\r
321 SpinDelay(50);\r
322\r
323 // stop modulating antenna and listen\r
6949aca9 324 LOW(GPIO_SSC_DOUT);\r
9bea179a 325\r
326 LED_D_OFF();\r
327\r
328 i = 0;\r
329 for(;;) {\r
6949aca9 330 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r
331 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer\r
332 i++; if(i >= TIBUFLEN) break;\r
333 }\r
334 WDT_HIT();\r
9bea179a 335 }\r
336\r
337 // return stolen pin to SSP\r
6949aca9 338 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;\r
339 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;\r
9bea179a 340\r
7381e8f2 341 char *dest = (char *)BigBuf;\r
342 n = TIBUFLEN*32;\r
343 // unpack buffer\r
344 for (i=TIBUFLEN-1; i>=0; i--) {\r
7381e8f2 345 for (j=0; j<32; j++) {\r
346 if(BigBuf[i] & (1 << j)) {\r
347 dest[--n] = 1;\r
348 } else {\r
349 dest[--n] = -1;\r
350 }\r
9bea179a 351 }\r
352 }\r
353}\r
354\r
9bea179a 355// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc\r
356// if crc provided, it will be written with the data verbatim (even if bogus)\r
357// if not provided a valid crc will be computed from the data and written.\r
358void WriteTItag(DWORD idhi, DWORD idlo, WORD crc)\r
359{\r
9bea179a 360 if(crc == 0) {\r
361 crc = update_crc16(crc, (idlo)&0xff);\r
362 crc = update_crc16(crc, (idlo>>8)&0xff);\r
363 crc = update_crc16(crc, (idlo>>16)&0xff);\r
364 crc = update_crc16(crc, (idlo>>24)&0xff);\r
365 crc = update_crc16(crc, (idhi)&0xff);\r
366 crc = update_crc16(crc, (idhi>>8)&0xff);\r
367 crc = update_crc16(crc, (idhi>>16)&0xff);\r
368 crc = update_crc16(crc, (idhi>>24)&0xff);\r
369 }\r
1e1b3030 370 Dbprintf("Writing to tag: %x%08x, crc=%x",\r
6f5cb60c 371 (unsigned int) idhi, (unsigned int) idlo, crc);\r
9bea179a 372\r
373 // TI tags charge at 134.2Khz\r
374 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
375 // Place FPGA in passthrough mode, in this mode the CROSS_LO line\r
376 // connects to SSP_DIN and the SSP_DOUT logic level controls\r
377 // whether we're modulating the antenna (high)\r
378 // or listening to the antenna (low)\r
379 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r
380 LED_A_ON();\r
381\r
382 // steal this pin from the SSP and use it to control the modulation\r
6949aca9 383 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r
6f5cb60c 384 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
9bea179a 385\r
386 // writing algorithm:\r
387 // a high bit consists of a field off for 1ms and field on for 1ms\r
388 // a low bit consists of a field off for 0.3ms and field on for 1.7ms\r
389 // initiate a charge time of 50ms (field on) then immediately start writing bits\r
390 // start by writing 0xBB (keyword) and 0xEB (password)\r
391 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)\r
392 // finally end with 0x0300 (write frame)\r
393 // all data is sent lsb firts\r
394 // finish with 15ms programming time\r
395\r
396 // modulate antenna\r
6949aca9 397 HIGH(GPIO_SSC_DOUT);\r
9bea179a 398 SpinDelay(50); // charge time\r
399\r
400 WriteTIbyte(0xbb); // keyword\r
401 WriteTIbyte(0xeb); // password\r
402 WriteTIbyte( (idlo )&0xff );\r
403 WriteTIbyte( (idlo>>8 )&0xff );\r
404 WriteTIbyte( (idlo>>16)&0xff );\r
405 WriteTIbyte( (idlo>>24)&0xff );\r
406 WriteTIbyte( (idhi )&0xff );\r
407 WriteTIbyte( (idhi>>8 )&0xff );\r
408 WriteTIbyte( (idhi>>16)&0xff );\r
409 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo\r
410 WriteTIbyte( (crc )&0xff ); // crc lo\r
411 WriteTIbyte( (crc>>8 )&0xff ); // crc hi\r
412 WriteTIbyte(0x00); // write frame lo\r
413 WriteTIbyte(0x03); // write frame hi\r
6949aca9 414 HIGH(GPIO_SSC_DOUT);\r
9bea179a 415 SpinDelay(50); // programming time\r
416\r
417 LED_A_OFF();\r
418\r
419 // get TI tag data into the buffer\r
420 AcquireTiType();\r
421\r
422 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
7381e8f2 423 DbpString("Now use tiread to check");\r
9bea179a 424}\r
425\r
426void SimulateTagLowFrequency(int period, int ledcontrol)\r
427{\r
428 int i;\r
429 BYTE *tab = (BYTE *)BigBuf;\r
430\r
431 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
432\r
6949aca9 433 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;\r
9bea179a 434\r
6949aca9 435 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
436 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;\r
9bea179a 437\r
438#define SHORT_COIL() LOW(GPIO_SSC_DOUT)\r
6949aca9 439#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)\r
9bea179a 440\r
441 i = 0;\r
442 for(;;) {\r
6949aca9 443 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {\r
9bea179a 444 if(BUTTON_PRESS()) {\r
445 DbpString("Stopped");\r
446 return;\r
447 }\r
448 WDT_HIT();\r
449 }\r
450\r
451 if (ledcontrol)\r
452 LED_D_ON();\r
453\r
454 if(tab[i])\r
455 OPEN_COIL();\r
456 else\r
457 SHORT_COIL();\r
458\r
459 if (ledcontrol)\r
460 LED_D_OFF();\r
461\r
6949aca9 462 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {\r
9bea179a 463 if(BUTTON_PRESS()) {\r
464 DbpString("Stopped");\r
465 return;\r
466 }\r
467 WDT_HIT();\r
468 }\r
469\r
470 i++;\r
471 if(i == period) i = 0;\r
472 }\r
473}\r
474\r
0fa9ca5b 475/* Provides a framework for bidirectional LF tag communication\r
476 * Encoding is currently Hitag2, but the general idea can probably\r
477 * be transferred to other encodings.\r
478 * \r
479 * The new FPGA code will, for the LF simulator mode, give on SSC_FRAME\r
480 * (PA15) a thresholded version of the signal from the ADC. Setting the\r
481 * ADC path to the low frequency peak detection signal, will enable a\r
482 * somewhat reasonable receiver for modulation on the carrier signal\r
483 * that is generated by the reader. The signal is low when the reader\r
484 * field is switched off, and high when the reader field is active. Due\r
485 * to the way that the signal looks like, mostly only the rising edge is\r
486 * useful, your mileage may vary.\r
487 * \r
488 * Neat perk: PA15 can not only be used as a bit-banging GPIO, but is also\r
489 * TIOA1, which can be used as the capture input for timer 1. This should\r
490 * make it possible to measure the exact edge-to-edge time, without processor\r
491 * intervention.\r
492 * \r
493 * Arguments: divisor is the divisor to be sent to the FPGA (e.g. 95 for 125kHz)\r
494 * t0 is the carrier frequency cycle duration in terms of MCK (384 for 125kHz)\r
495 * \r
496 * The following defines are in carrier periods: \r
497 */\r
498#define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */ \r
499#define HITAG_T_1_MIN 24 /* T[1] should be 26..30 */\r
500#define HITAG_T_EOF 40 /* T_EOF should be > 36 */\r
501#define HITAG_T_WRESP 208 /* T_wresp should be 204..212 */\r
502\r
503static void hitag_handle_frame(int t0, int frame_len, char *frame);\r
504//#define DEBUG_RA_VALUES 1\r
505#define DEBUG_FRAME_CONTENTS 1\r
506void SimulateTagLowFrequencyBidir(int divisor, int t0)\r
507{\r
508#if DEBUG_RA_VALUES || DEBUG_FRAME_CONTENTS\r
509 int i = 0;\r
510#endif\r
511 char frame[10];\r
512 int frame_pos=0;\r
513 \r
514 DbpString("Starting Hitag2 emulator, press button to end");\r
515 hitag2_init();\r
516 \r
517 /* Set up simulator mode, frequency divisor which will drive the FPGA\r
6949aca9 518 * and analog mux selection.\r
0fa9ca5b 519 */\r
520 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
521 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);\r
522 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
523 RELAY_OFF();\r
524 \r
525 /* Set up Timer 1:\r
526 * Capture mode, timer source MCK/2 (TIMER_CLOCK1), TIOA is external trigger,\r
527 * external trigger rising edge, load RA on rising edge of TIOA, load RB on rising\r
6949aca9 528 * edge of TIOA. Assign PA15 to TIOA1 (peripheral B)\r
0fa9ca5b 529 */\r
530 \r
6949aca9 531 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);\r
532 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;\r
533 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r
534 AT91C_BASE_TC1->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 |\r
535 AT91C_TC_ETRGEDG_RISING |\r
536 AT91C_TC_ABETRG |\r
537 AT91C_TC_LDRA_RISING |\r
538 AT91C_TC_LDRB_RISING;\r
539 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN |\r
540 AT91C_TC_SWTRG;\r
0fa9ca5b 541 \r
542 /* calculate the new value for the carrier period in terms of TC1 values */\r
543 t0 = t0/2;\r
544 \r
545 int overflow = 0;\r
546 while(!BUTTON_PRESS()) {\r
547 WDT_HIT();\r
6949aca9 548 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {\r
549 int ra = AT91C_BASE_TC1->TC_RA;\r
0fa9ca5b 550 if((ra > t0*HITAG_T_EOF) | overflow) ra = t0*HITAG_T_EOF+1;\r
551#if DEBUG_RA_VALUES\r
552 if(ra > 255 || overflow) ra = 255;\r
553 ((char*)BigBuf)[i] = ra;\r
554 i = (i+1) % 8000;\r
555#endif\r
556 \r
557 if(overflow || (ra > t0*HITAG_T_EOF) || (ra < t0*HITAG_T_0_MIN)) {\r
558 /* Ignore */\r
559 } else if(ra >= t0*HITAG_T_1_MIN ) {\r
560 /* '1' bit */\r
561 if(frame_pos < 8*sizeof(frame)) {\r
562 frame[frame_pos / 8] |= 1<<( 7-(frame_pos%8) );\r
563 frame_pos++;\r
564 }\r
565 } else if(ra >= t0*HITAG_T_0_MIN) {\r
566 /* '0' bit */\r
567 if(frame_pos < 8*sizeof(frame)) {\r
568 frame[frame_pos / 8] |= 0<<( 7-(frame_pos%8) );\r
569 frame_pos++;\r
570 }\r
571 }\r
572 \r
573 overflow = 0;\r
574 LED_D_ON();\r
575 } else {\r
6949aca9 576 if(AT91C_BASE_TC1->TC_CV > t0*HITAG_T_EOF) {\r
0fa9ca5b 577 /* Minor nuisance: In Capture mode, the timer can not be\r
578 * stopped by a Compare C. There's no way to stop the clock\r
579 * in software, so we'll just have to note the fact that an\r
580 * overflow happened and the next loaded timer value might\r
581 * have wrapped. Also, this marks the end of frame, and the\r
582 * still running counter can be used to determine the correct\r
6949aca9 583 * time for the start of the reply.\r
0fa9ca5b 584 */ \r
585 overflow = 1;\r
586 \r
587 if(frame_pos > 0) {\r
588 /* Have a frame, do something with it */\r
589#if DEBUG_FRAME_CONTENTS\r
590 ((char*)BigBuf)[i++] = frame_pos;\r
591 memcpy( ((char*)BigBuf)+i, frame, 7);\r
592 i+=7;\r
593 i = i % sizeof(BigBuf);\r
594#endif\r
595 hitag_handle_frame(t0, frame_pos, frame);\r
596 memset(frame, 0, sizeof(frame));\r
597 }\r
598 frame_pos = 0;\r
599\r
600 }\r
601 LED_D_OFF();\r
602 }\r
603 }\r
604 DbpString("All done");\r
605}\r
606\r
607static void hitag_send_bit(int t0, int bit) {\r
608 if(bit == 1) {\r
609 /* Manchester: Loaded, then unloaded */\r
610 LED_A_ON();\r
611 SHORT_COIL();\r
6949aca9 612 while(AT91C_BASE_TC1->TC_CV < t0*15);\r
0fa9ca5b 613 OPEN_COIL();\r
6949aca9 614 while(AT91C_BASE_TC1->TC_CV < t0*31);\r
0fa9ca5b 615 LED_A_OFF();\r
616 } else if(bit == 0) {\r
617 /* Manchester: Unloaded, then loaded */\r
618 LED_B_ON();\r
619 OPEN_COIL();\r
6949aca9 620 while(AT91C_BASE_TC1->TC_CV < t0*15);\r
0fa9ca5b 621 SHORT_COIL();\r
6949aca9 622 while(AT91C_BASE_TC1->TC_CV < t0*31);\r
0fa9ca5b 623 LED_B_OFF();\r
624 }\r
6949aca9 625 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset clock for the next bit */\r
0fa9ca5b 626 \r
627}\r
628static void hitag_send_frame(int t0, int frame_len, const char const * frame, int fdt)\r
629{\r
630 OPEN_COIL();\r
6949aca9 631 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
0fa9ca5b 632 \r
633 /* Wait for HITAG_T_WRESP carrier periods after the last reader bit,\r
634 * not that since the clock counts since the rising edge, but T_wresp is\r
635 * with respect to the falling edge, we need to wait actually (T_wresp - T_g)\r
6949aca9 636 * periods. The gap time T_g varies (4..10).\r
0fa9ca5b 637 */\r
6949aca9 638 while(AT91C_BASE_TC1->TC_CV < t0*(fdt-8));\r
0fa9ca5b 639\r
6949aca9 640 int saved_cmr = AT91C_BASE_TC1->TC_CMR;\r
641 AT91C_BASE_TC1->TC_CMR &= ~AT91C_TC_ETRGEDG; /* Disable external trigger for the clock */\r
642 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset the clock and use it for response timing */\r
0fa9ca5b 643 \r
644 int i;\r
645 for(i=0; i<5; i++)\r
646 hitag_send_bit(t0, 1); /* Start of frame */\r
647 \r
648 for(i=0; i<frame_len; i++) {\r
649 hitag_send_bit(t0, !!(frame[i/ 8] & (1<<( 7-(i%8) ))) );\r
650 }\r
651 \r
652 OPEN_COIL();\r
6949aca9 653 AT91C_BASE_TC1->TC_CMR = saved_cmr;\r
0fa9ca5b 654}\r
655\r
656/* Callback structure to cleanly separate tag emulation code from the radio layer. */\r
657static int hitag_cb(const char* response_data, const int response_length, const int fdt, void *cb_cookie)\r
658{\r
659 hitag_send_frame(*(int*)cb_cookie, response_length, response_data, fdt);\r
660 return 0;\r
661}\r
662/* Frame length in bits, frame contents in MSBit first format */\r
663static void hitag_handle_frame(int t0, int frame_len, char *frame)\r
664{\r
665 hitag2_handle_command(frame, frame_len, hitag_cb, &t0);\r
666}\r
667\r
9bea179a 668// compose fc/8 fc/10 waveform\r
669static void fc(int c, int *n) {\r
670 BYTE *dest = (BYTE *)BigBuf;\r
671 int idx;\r
672\r
673 // for when we want an fc8 pattern every 4 logical bits\r
674 if(c==0) {\r
675 dest[((*n)++)]=1;\r
676 dest[((*n)++)]=1;\r
677 dest[((*n)++)]=0;\r
678 dest[((*n)++)]=0;\r
679 dest[((*n)++)]=0;\r
680 dest[((*n)++)]=0;\r
681 dest[((*n)++)]=0;\r
682 dest[((*n)++)]=0;\r
683 }\r
684 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples\r
685 if(c==8) {\r
686 for (idx=0; idx<6; idx++) {\r
687 dest[((*n)++)]=1;\r
688 dest[((*n)++)]=1;\r
689 dest[((*n)++)]=0;\r
690 dest[((*n)++)]=0;\r
691 dest[((*n)++)]=0;\r
692 dest[((*n)++)]=0;\r
693 dest[((*n)++)]=0;\r
694 dest[((*n)++)]=0;\r
695 }\r
696 }\r
697\r
698 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples\r
699 if(c==10) {\r
700 for (idx=0; idx<5; idx++) {\r
701 dest[((*n)++)]=1;\r
702 dest[((*n)++)]=1;\r
703 dest[((*n)++)]=1;\r
704 dest[((*n)++)]=0;\r
705 dest[((*n)++)]=0;\r
706 dest[((*n)++)]=0;\r
707 dest[((*n)++)]=0;\r
708 dest[((*n)++)]=0;\r
709 dest[((*n)++)]=0;\r
710 dest[((*n)++)]=0;\r
711 }\r
712 }\r
713}\r
714\r
715// prepare a waveform pattern in the buffer based on the ID given then\r
716// simulate a HID tag until the button is pressed\r
717void CmdHIDsimTAG(int hi, int lo, int ledcontrol)\r
718{\r
719 int n=0, i=0;\r
720 /*\r
721 HID tag bitstream format\r
722 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits\r
723 A 1 bit is represented as 6 fc8 and 5 fc10 patterns\r
724 A 0 bit is represented as 5 fc10 and 6 fc8 patterns\r
725 A fc8 is inserted before every 4 bits\r
726 A special start of frame pattern is used consisting a0b0 where a and b are neither 0\r
727 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)\r
728 */\r
729\r
730 if (hi>0xFFF) {\r
731 DbpString("Tags can only have 44 bits.");\r
732 return;\r
733 }\r
734 fc(0,&n);\r
735 // special start of frame marker containing invalid bit sequences\r
736 fc(8, &n); fc(8, &n); // invalid\r
737 fc(8, &n); fc(10, &n); // logical 0\r
738 fc(10, &n); fc(10, &n); // invalid\r
739 fc(8, &n); fc(10, &n); // logical 0\r
740\r
741 WDT_HIT();\r
742 // manchester encode bits 43 to 32\r
743 for (i=11; i>=0; i--) {\r
744 if ((i%4)==3) fc(0,&n);\r
745 if ((hi>>i)&1) {\r
746 fc(10, &n); fc(8, &n); // low-high transition\r
747 } else {\r
748 fc(8, &n); fc(10, &n); // high-low transition\r
749 }\r
750 }\r
751\r
752 WDT_HIT();\r
753 // manchester encode bits 31 to 0\r
754 for (i=31; i>=0; i--) {\r
755 if ((i%4)==3) fc(0,&n);\r
756 if ((lo>>i)&1) {\r
757 fc(10, &n); fc(8, &n); // low-high transition\r
758 } else {\r
759 fc(8, &n); fc(10, &n); // high-low transition\r
760 }\r
761 }\r
762\r
763 if (ledcontrol)\r
764 LED_A_ON();\r
765 SimulateTagLowFrequency(n, ledcontrol);\r
766\r
767 if (ledcontrol)\r
768 LED_A_OFF();\r
769}\r
770\r
771\r
772// loop to capture raw HID waveform then FSK demodulate the TAG ID from it\r
773void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)\r
774{\r
775 BYTE *dest = (BYTE *)BigBuf;\r
776 int m=0, n=0, i=0, idx=0, found=0, lastval=0;\r
777 DWORD hi=0, lo=0;\r
778\r
779 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
780 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
781\r
782 // Connect the A/D to the peak-detected low-frequency path.\r
783 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
784\r
785 // Give it a bit of time for the resonant antenna to settle.\r
786 SpinDelay(50);\r
787\r
788 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
789 FpgaSetupSsc();\r
790\r
791 for(;;) {\r
792 WDT_HIT();\r
793 if (ledcontrol)\r
794 LED_A_ON();\r
795 if(BUTTON_PRESS()) {\r
796 DbpString("Stopped");\r
797 if (ledcontrol)\r
798 LED_A_OFF();\r
799 return;\r
800 }\r
801\r
802 i = 0;\r
803 m = sizeof(BigBuf);\r
804 memset(dest,128,m);\r
805 for(;;) {\r
6949aca9 806 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
807 AT91C_BASE_SSC->SSC_THR = 0x43;\r
9bea179a 808 if (ledcontrol)\r
809 LED_D_ON();\r
810 }\r
6949aca9 811 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
812 dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
9bea179a 813 // we don't care about actual value, only if it's more or less than a\r
814 // threshold essentially we capture zero crossings for later analysis\r
815 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;\r
816 i++;\r
817 if (ledcontrol)\r
818 LED_D_OFF();\r
819 if(i >= m) {\r
820 break;\r
821 }\r
822 }\r
823 }\r
824\r
825 // FSK demodulator\r
826\r
827 // sync to first lo-hi transition\r
828 for( idx=1; idx<m; idx++) {\r
829 if (dest[idx-1]<dest[idx])\r
830 lastval=idx;\r
831 break;\r
832 }\r
833 WDT_HIT();\r
834\r
835 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)\r
836 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere\r
837 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10\r
838 for( i=0; idx<m; idx++) {\r
839 if (dest[idx-1]<dest[idx]) {\r
840 dest[i]=idx-lastval;\r
841 if (dest[i] <= 8) {\r
842 dest[i]=1;\r
843 } else {\r
844 dest[i]=0;\r
845 }\r
846\r
847 lastval=idx;\r
848 i++;\r
849 }\r
850 }\r
851 m=i;\r
852 WDT_HIT();\r
853\r
854 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns\r
855 lastval=dest[0];\r
856 idx=0;\r
857 i=0;\r
858 n=0;\r
859 for( idx=0; idx<m; idx++) {\r
860 if (dest[idx]==lastval) {\r
861 n++;\r
862 } else {\r
863 // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,\r
864 // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets\r
865 // swallowed up by rounding\r
866 // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding\r
867 // special start of frame markers use invalid manchester states (no transitions) by using sequences\r
868 // like 111000\r
869 if (dest[idx-1]) {\r
870 n=(n+1)/6; // fc/8 in sets of 6\r
871 } else {\r
872 n=(n+1)/5; // fc/10 in sets of 5\r
873 }\r
874 switch (n) { // stuff appropriate bits in buffer\r
875 case 0:\r
876 case 1: // one bit\r
877 dest[i++]=dest[idx-1];\r
878 break;\r
879 case 2: // two bits\r
880 dest[i++]=dest[idx-1];\r
881 dest[i++]=dest[idx-1];\r
882 break;\r
883 case 3: // 3 bit start of frame markers\r
884 dest[i++]=dest[idx-1];\r
885 dest[i++]=dest[idx-1];\r
886 dest[i++]=dest[idx-1];\r
887 break;\r
888 // When a logic 0 is immediately followed by the start of the next transmisson\r
889 // (special pattern) a pattern of 4 bit duration lengths is created.\r
890 case 4:\r
891 dest[i++]=dest[idx-1];\r
892 dest[i++]=dest[idx-1];\r
893 dest[i++]=dest[idx-1];\r
894 dest[i++]=dest[idx-1];\r
895 break;\r
896 default: // this shouldn't happen, don't stuff any bits\r
897 break;\r
898 }\r
899 n=0;\r
900 lastval=dest[idx];\r
901 }\r
902 }\r
903 m=i;\r
904 WDT_HIT();\r
905\r
906 // final loop, go over previously decoded manchester data and decode into usable tag ID\r
907 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0\r
908 for( idx=0; idx<m-6; idx++) {\r
909 // search for a start of frame marker\r
910 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )\r
911 {\r
912 found=1;\r
913 idx+=6;\r
914 if (found && (hi|lo)) {\r
1e1b3030 915 Dbprintf("TAG ID: %x%08x (%d)",\r
6f5cb60c 916 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r
9bea179a 917 /* if we're only looking for one tag */\r
918 if (findone)\r
919 {\r
920 *high = hi;\r
921 *low = lo;\r
922 return;\r
923 }\r
924 hi=0;\r
925 lo=0;\r
926 found=0;\r
927 }\r
928 }\r
929 if (found) {\r
930 if (dest[idx] && (!dest[idx+1]) ) {\r
931 hi=(hi<<1)|(lo>>31);\r
932 lo=(lo<<1)|0;\r
933 } else if ( (!dest[idx]) && dest[idx+1]) {\r
934 hi=(hi<<1)|(lo>>31);\r
935 lo=(lo<<1)|1;\r
936 } else {\r
937 found=0;\r
938 hi=0;\r
939 lo=0;\r
940 }\r
941 idx++;\r
942 }\r
943 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )\r
944 {\r
945 found=1;\r
946 idx+=6;\r
947 if (found && (hi|lo)) {\r
1e1b3030 948 Dbprintf("TAG ID: %x%08x (%d)",\r
6f5cb60c 949 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r
9bea179a 950 /* if we're only looking for one tag */\r
951 if (findone)\r
952 {\r
953 *high = hi;\r
954 *low = lo;\r
955 return;\r
956 }\r
957 hi=0;\r
958 lo=0;\r
959 found=0;\r
960 }\r
961 }\r
962 }\r
963 WDT_HIT();\r
964 }\r
965}\r
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