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22f4dca8 | 1 | //----------------------------------------------------------------------------- |
2 | // Jonathan Westhues, Sept 2005 | |
3 | // Iceman, Sept 2016 | |
4 | // | |
5 | // This code is licensed to you under the terms of the GNU GPL, version 2 or, | |
6 | // at your option, any later version. See the LICENSE.txt file for the text of | |
7 | // the license. | |
8 | //----------------------------------------------------------------------------- | |
9 | // Timers, Clocks functions used in LF or Legic where you would need detailed time. | |
10 | //----------------------------------------------------------------------------- | |
11 | ||
12 | #include "ticks.h" | |
13 | ||
14 | // attempt at high resolution microsecond timer | |
15 | // beware: timer counts in 21.3uS increments (1024/48Mhz) | |
16 | void SpinDelayUs(int us) { | |
17 | int ticks = (48 * us) >> 10; | |
18 | ||
19 | // Borrow a PWM unit for my real-time clock | |
20 | AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0); | |
21 | ||
22 | // 48 MHz / 1024 gives 46.875 kHz | |
23 | AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10); | |
24 | AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0; | |
25 | AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff; | |
26 | ||
27 | uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; | |
28 | ||
29 | for(;;) { | |
30 | uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; | |
31 | if (now == (uint16_t)(start + ticks)) | |
32 | return; | |
33 | ||
34 | WDT_HIT(); | |
35 | } | |
36 | } | |
37 | ||
38 | void SpinDelay(int ms) { | |
39 | // convert to uS and call microsecond delay function | |
40 | SpinDelayUs(ms*1000); | |
41 | } | |
42 | // ------------------------------------------------------------------------- | |
43 | // timer lib | |
44 | // ------------------------------------------------------------------------- | |
45 | // test procedure: | |
46 | // | |
47 | // ti = GetTickCount(); | |
48 | // SpinDelay(1000); | |
49 | // ti = GetTickCount() - ti; | |
50 | // Dbprintf("timer(1s): %d t=%d", ti, GetTickCount()); | |
22f4dca8 | 51 | void StartTickCount() { |
52 | // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz. | |
53 | // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register. | |
54 | uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff; // = 16 * main clock frequency (16MHz) / slow clock frequency | |
55 | // set RealTimeCounter divider to count at 1kHz: | |
56 | AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf); | |
57 | // note: worst case precision is approx 2.5% | |
58 | } | |
59 | ||
60 | /* | |
61 | * Get the current count. | |
62 | */ | |
63 | uint32_t RAMFUNC GetTickCount(){ | |
64 | return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2; | |
65 | } | |
66 | ||
67 | // ------------------------------------------------------------------------- | |
68 | // microseconds timer | |
69 | // ------------------------------------------------------------------------- | |
70 | void StartCountUS() { | |
71 | AT91C_BASE_PMC->PMC_PCER |= (1 << 12) | (1 << 13) | (1 << 14); | |
72 | AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE; | |
73 | ||
74 | // fast clock | |
75 | // tick=1.5mks | |
76 | AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable | |
77 | AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32 | |
78 | AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR | | |
79 | AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET; | |
80 | AT91C_BASE_TC0->TC_RA = 1; | |
81 | AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000 | |
82 | ||
83 | AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable | |
84 | AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0 | |
85 | ||
86 | AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | |
87 | AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | |
88 | AT91C_BASE_TCB->TCB_BCR = 1; | |
89 | ||
24c49d36 | 90 | while (AT91C_BASE_TC1->TC_CV > 1); |
22f4dca8 | 91 | } |
92 | ||
93 | uint32_t RAMFUNC GetCountUS(){ | |
94 | //return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10); | |
95 | // By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548 | |
96 | return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); | |
97 | } | |
98 | void ResetUSClock(void) { | |
99 | //enable clock of timer and software trigger | |
100 | AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | |
101 | AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | |
24c49d36 | 102 | while (AT91C_BASE_TC1->TC_CV > 1); |
22f4dca8 | 103 | } |
24c49d36 | 104 | |
22f4dca8 | 105 | // ------------------------------------------------------------------------- |
106 | // Timer for iso14443 commands. Uses ssp_clk from FPGA | |
107 | // ------------------------------------------------------------------------- | |
108 | void StartCountSspClk() { | |
109 | AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2); // Enable Clock to all timers | |
110 | AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1 | |
111 | | AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none | |
112 | | AT91C_TCB_TC2XC2S_TIOA0; // XC2 Clock = TIOA0 | |
113 | ||
114 | // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs: | |
115 | AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // disable TC1 | |
116 | AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz | |
117 | | AT91C_TC_CPCSTOP // Stop clock on RC compare | |
118 | | AT91C_TC_EEVTEDG_RISING // Trigger on rising edge of Event | |
119 | | AT91C_TC_EEVT_TIOB // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16) | |
120 | | AT91C_TC_ENETRG // Enable external trigger event | |
121 | | AT91C_TC_WAVESEL_UP // Upmode without automatic trigger on RC compare | |
122 | | AT91C_TC_WAVE // Waveform Mode | |
123 | | AT91C_TC_AEEVT_SET // Set TIOA1 on external event | |
124 | | AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare | |
125 | AT91C_BASE_TC1->TC_RC = 0x04; // RC Compare value = 0x04 | |
126 | ||
127 | // use TC0 to count TIOA1 pulses | |
128 | AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0 | |
129 | AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0 // TC0 clock = XC0 clock = TIOA1 | |
130 | | AT91C_TC_WAVE // Waveform Mode | |
131 | | AT91C_TC_WAVESEL_UP // just count | |
132 | | AT91C_TC_ACPA_CLEAR // Clear TIOA0 on RA Compare | |
133 | | AT91C_TC_ACPC_SET; // Set TIOA0 on RC Compare | |
134 | AT91C_BASE_TC0->TC_RA = 1; // RA Compare value = 1; pulse width to TC2 | |
135 | AT91C_BASE_TC0->TC_RC = 0; // RC Compare value = 0; increment TC2 on overflow | |
136 | ||
137 | // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk) | |
138 | AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; // disable TC2 | |
139 | AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2 // TC2 clock = XC2 clock = TIOA0 | |
140 | | AT91C_TC_WAVE // Waveform Mode | |
141 | | AT91C_TC_WAVESEL_UP; // just count | |
142 | ||
143 | AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // enable and reset TC0 | |
144 | AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // enable and reset TC1 | |
145 | AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // enable and reset TC2 | |
146 | ||
147 | // synchronize the counter with the ssp_frame signal. | |
148 | // Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present | |
149 | while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); // wait for ssp_frame to go high (start of frame) | |
150 | while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); // wait for ssp_frame to be low | |
151 | while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high | |
152 | ||
153 | // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame | |
154 | // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge | |
155 | AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge) | |
156 | // at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0) | |
157 | // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on, | |
158 | // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer. | |
159 | // (just started with the transfer of the 4th Bit). | |
160 | ||
161 | // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. | |
162 | // Therefore need to wait quite some time before we can use the counter. | |
24c49d36 | 163 | while (AT91C_BASE_TC2->TC_CV > 1); |
22f4dca8 | 164 | } |
165 | void ResetSspClk(void) { | |
166 | //enable clock of timer and software trigger | |
167 | AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | |
168 | AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | |
169 | AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | |
170 | } | |
171 | ||
172 | uint32_t RAMFUNC GetCountSspClk(){ | |
173 | ||
174 | uint32_t tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV; | |
175 | if ((tmp_count & 0x0000ffff) == 0) //small chance that we may have missed an increment in TC2 | |
176 | return (AT91C_BASE_TC2->TC_CV << 16); | |
177 | return tmp_count; | |
178 | } | |
179 | ||
180 | ||
24c49d36 | 181 | // ------------------------------------------------------------------------- |
182 | // Timer for bitbanging, or LF stuff when you need a very precis timer | |
183 | // 1us = 1.5ticks | |
184 | // ------------------------------------------------------------------------- | |
22f4dca8 | 185 | void StartTicks(void){ |
186 | //initialization of the timer | |
187 | AT91C_BASE_PMC->PMC_PCER |= (1 << 12) | (1 << 13) | (1 << 14); | |
188 | AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE; | |
24c49d36 | 189 | AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; |
22f4dca8 | 190 | AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK; //clock at 48/32 MHz |
22f4dca8 | 191 | AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; |
192 | AT91C_BASE_TCB->TCB_BCR = 1; | |
193 | // wait until timer becomes zero. | |
194 | while (AT91C_BASE_TC0->TC_CV > 1); | |
195 | } | |
196 | // Wait - Spindelay in ticks. | |
197 | // if called with a high number, this will trigger the WDT... | |
198 | void WaitTicks(uint32_t ticks){ | |
199 | if ( ticks == 0 ) return; | |
200 | ticks += GET_TICKS; | |
201 | while (GET_TICKS < ticks); | |
202 | } | |
203 | // Wait / Spindelay in us (microseconds) | |
204 | // 1us = 1.5ticks. | |
205 | void WaitUS(uint16_t us){ | |
206 | if ( us == 0 ) return; | |
207 | WaitTicks( (uint32_t)(us * 1.5) ); | |
208 | } | |
209 | void WaitMS(uint16_t ms){ | |
210 | if (ms == 0) return; | |
211 | WaitTicks( (uint32_t)(ms * 1500) ); | |
212 | } | |
213 | // Starts Clock and waits until its reset | |
214 | void ResetTicks(){ | |
215 | ResetTimer(AT91C_BASE_TC0); | |
216 | } | |
217 | void ResetTimer(AT91PS_TC timer){ | |
218 | timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | |
219 | while(timer->TC_CV > 1) ; | |
220 | } |