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[proxmark3-svn] / armsrc / lfops.c
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e09f21fa 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
9//-----------------------------------------------------------------------------
10
11#include "proxmark3.h"
12#include "apps.h"
13#include "util.h"
14#include "hitag2.h"
15#include "crc16.h"
16#include "string.h"
17#include "lfdemod.h"
18#include "lfsampling.h"
f7048dc8 19#include "usb_cdc.h"
e09f21fa 20
21
22/**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
30{
31
32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
34
35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
71
72 // now do the read
73 DoAcquisition_config(false);
74}
75
76
77
78/* blank r/w tag data stream
79...0000000000000000 01111111
801010101010101010101010101010101010101010101010101010101010101010
810011010010100001
8201111111
83101010101010101[0]000...
84
85[5555fe852c5555555555555555fe0000]
86*/
87void ReadTItag(void)
88{
89 // some hardcoded initial params
90 // when we read a TI tag we sample the zerocross line at 2Mhz
91 // TI tags modulate a 1 as 16 cycles of 123.2Khz
92 // TI tags modulate a 0 as 16 cycles of 134.2Khz
93 #define FSAMPLE 2000000
94 #define FREQLO 123200
95 #define FREQHI 134200
96
97 signed char *dest = (signed char *)BigBuf_get_addr();
98 uint16_t n = BigBuf_max_traceLen();
99 // 128 bit shift register [shift3:shift2:shift1:shift0]
100 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
101
102 int i, cycles=0, samples=0;
103 // how many sample points fit in 16 cycles of each frequency
104 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
105 // when to tell if we're close enough to one freq or another
106 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
107
108 // TI tags charge at 134.2Khz
109 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
111
112 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
113 // connects to SSP_DIN and the SSP_DOUT logic level controls
114 // whether we're modulating the antenna (high)
115 // or listening to the antenna (low)
116 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
117
118 // get TI tag data into the buffer
119 AcquireTiType();
120
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
122
123 for (i=0; i<n-1; i++) {
124 // count cycles by looking for lo to hi zero crossings
125 if ( (dest[i]<0) && (dest[i+1]>0) ) {
126 cycles++;
127 // after 16 cycles, measure the frequency
128 if (cycles>15) {
129 cycles=0;
130 samples=i-samples; // number of samples in these 16 cycles
131
132 // TI bits are coming to us lsb first so shift them
133 // right through our 128 bit right shift register
134 shift0 = (shift0>>1) | (shift1 << 31);
135 shift1 = (shift1>>1) | (shift2 << 31);
136 shift2 = (shift2>>1) | (shift3 << 31);
137 shift3 >>= 1;
138
139 // check if the cycles fall close to the number
140 // expected for either the low or high frequency
141 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
142 // low frequency represents a 1
143 shift3 |= (1<<31);
144 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
145 // high frequency represents a 0
146 } else {
147 // probably detected a gay waveform or noise
148 // use this as gaydar or discard shift register and start again
149 shift3 = shift2 = shift1 = shift0 = 0;
150 }
151 samples = i;
152
153 // for each bit we receive, test if we've detected a valid tag
154
155 // if we see 17 zeroes followed by 6 ones, we might have a tag
156 // remember the bits are backwards
157 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
158 // if start and end bytes match, we have a tag so break out of the loop
159 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
160 cycles = 0xF0B; //use this as a flag (ugly but whatever)
161 break;
162 }
163 }
164 }
165 }
166 }
167
168 // if flag is set we have a tag
169 if (cycles!=0xF0B) {
170 DbpString("Info: No valid tag detected.");
171 } else {
172 // put 64 bit data into shift1 and shift0
173 shift0 = (shift0>>24) | (shift1 << 8);
174 shift1 = (shift1>>24) | (shift2 << 8);
175
176 // align 16 bit crc into lower half of shift2
177 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
178
179 // if r/w tag, check ident match
180 if (shift3 & (1<<15) ) {
181 DbpString("Info: TI tag is rewriteable");
182 // only 15 bits compare, last bit of ident is not valid
183 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
184 DbpString("Error: Ident mismatch!");
185 } else {
186 DbpString("Info: TI tag ident is valid");
187 }
188 } else {
189 DbpString("Info: TI tag is readonly");
190 }
191
192 // WARNING the order of the bytes in which we calc crc below needs checking
193 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
194 // bytes in reverse or something
195 // calculate CRC
196 uint32_t crc=0;
197
198 crc = update_crc16(crc, (shift0)&0xff);
199 crc = update_crc16(crc, (shift0>>8)&0xff);
200 crc = update_crc16(crc, (shift0>>16)&0xff);
201 crc = update_crc16(crc, (shift0>>24)&0xff);
202 crc = update_crc16(crc, (shift1)&0xff);
203 crc = update_crc16(crc, (shift1>>8)&0xff);
204 crc = update_crc16(crc, (shift1>>16)&0xff);
205 crc = update_crc16(crc, (shift1>>24)&0xff);
206
207 Dbprintf("Info: Tag data: %x%08x, crc=%x",
208 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
209 if (crc != (shift2&0xffff)) {
210 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
211 } else {
212 DbpString("Info: CRC is good");
213 }
214 }
215}
216
217void WriteTIbyte(uint8_t b)
218{
219 int i = 0;
220
221 // modulate 8 bits out to the antenna
222 for (i=0; i<8; i++)
223 {
224 if (b&(1<<i)) {
225 // stop modulating antenna
226 LOW(GPIO_SSC_DOUT);
227 SpinDelayUs(1000);
228 // modulate antenna
229 HIGH(GPIO_SSC_DOUT);
230 SpinDelayUs(1000);
231 } else {
232 // stop modulating antenna
233 LOW(GPIO_SSC_DOUT);
234 SpinDelayUs(300);
235 // modulate antenna
236 HIGH(GPIO_SSC_DOUT);
237 SpinDelayUs(1700);
238 }
239 }
240}
241
242void AcquireTiType(void)
243{
244 int i, j, n;
245 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
246 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
247 #define TIBUFLEN 1250
248
249 // clear buffer
250 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
251 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
252
253 // Set up the synchronous serial port
254 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
255 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
256
257 // steal this pin from the SSP and use it to control the modulation
258 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
259 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
260
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
262 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
263
264 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
265 // 48/2 = 24 MHz clock must be divided by 12
266 AT91C_BASE_SSC->SSC_CMR = 12;
267
268 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
269 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
270 AT91C_BASE_SSC->SSC_TCMR = 0;
271 AT91C_BASE_SSC->SSC_TFMR = 0;
272
273 LED_D_ON();
274
275 // modulate antenna
276 HIGH(GPIO_SSC_DOUT);
277
278 // Charge TI tag for 50ms.
279 SpinDelay(50);
280
281 // stop modulating antenna and listen
282 LOW(GPIO_SSC_DOUT);
283
284 LED_D_OFF();
285
286 i = 0;
287 for(;;) {
288 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
289 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
290 i++; if(i >= TIBUFLEN) break;
291 }
292 WDT_HIT();
293 }
294
295 // return stolen pin to SSP
296 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
297 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
298
299 char *dest = (char *)BigBuf_get_addr();
300 n = TIBUFLEN*32;
301 // unpack buffer
302 for (i=TIBUFLEN-1; i>=0; i--) {
303 for (j=0; j<32; j++) {
304 if(BigBuf[i] & (1 << j)) {
305 dest[--n] = 1;
306 } else {
307 dest[--n] = -1;
308 }
309 }
310 }
311}
312
313// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
314// if crc provided, it will be written with the data verbatim (even if bogus)
315// if not provided a valid crc will be computed from the data and written.
316void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
317{
318 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
319 if(crc == 0) {
320 crc = update_crc16(crc, (idlo)&0xff);
321 crc = update_crc16(crc, (idlo>>8)&0xff);
322 crc = update_crc16(crc, (idlo>>16)&0xff);
323 crc = update_crc16(crc, (idlo>>24)&0xff);
324 crc = update_crc16(crc, (idhi)&0xff);
325 crc = update_crc16(crc, (idhi>>8)&0xff);
326 crc = update_crc16(crc, (idhi>>16)&0xff);
327 crc = update_crc16(crc, (idhi>>24)&0xff);
328 }
329 Dbprintf("Writing to tag: %x%08x, crc=%x",
330 (unsigned int) idhi, (unsigned int) idlo, crc);
331
332 // TI tags charge at 134.2Khz
333 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
334 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
335 // connects to SSP_DIN and the SSP_DOUT logic level controls
336 // whether we're modulating the antenna (high)
337 // or listening to the antenna (low)
338 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
339 LED_A_ON();
340
341 // steal this pin from the SSP and use it to control the modulation
342 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344
345 // writing algorithm:
346 // a high bit consists of a field off for 1ms and field on for 1ms
347 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
348 // initiate a charge time of 50ms (field on) then immediately start writing bits
349 // start by writing 0xBB (keyword) and 0xEB (password)
350 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
351 // finally end with 0x0300 (write frame)
352 // all data is sent lsb firts
353 // finish with 15ms programming time
354
355 // modulate antenna
356 HIGH(GPIO_SSC_DOUT);
357 SpinDelay(50); // charge time
358
359 WriteTIbyte(0xbb); // keyword
360 WriteTIbyte(0xeb); // password
361 WriteTIbyte( (idlo )&0xff );
362 WriteTIbyte( (idlo>>8 )&0xff );
363 WriteTIbyte( (idlo>>16)&0xff );
364 WriteTIbyte( (idlo>>24)&0xff );
365 WriteTIbyte( (idhi )&0xff );
366 WriteTIbyte( (idhi>>8 )&0xff );
367 WriteTIbyte( (idhi>>16)&0xff );
368 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
369 WriteTIbyte( (crc )&0xff ); // crc lo
370 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
371 WriteTIbyte(0x00); // write frame lo
372 WriteTIbyte(0x03); // write frame hi
373 HIGH(GPIO_SSC_DOUT);
374 SpinDelay(50); // programming time
375
376 LED_A_OFF();
377
378 // get TI tag data into the buffer
379 AcquireTiType();
380
381 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
382 DbpString("Now use tiread to check");
383}
384
385void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
386{
387 int i;
388 uint8_t *tab = BigBuf_get_addr();
389
390 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
391 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
392
393 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
394
395 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
396 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
397
398 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
399 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
400
401 i = 0;
402 for(;;) {
403 //wait until SSC_CLK goes HIGH
404 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
f7048dc8 405 if(BUTTON_PRESS() || usb_poll()) {
e09f21fa 406 DbpString("Stopped");
407 return;
408 }
409 WDT_HIT();
410 }
411 if (ledcontrol)
412 LED_D_ON();
413
414 if(tab[i])
415 OPEN_COIL();
416 else
417 SHORT_COIL();
418
419 if (ledcontrol)
420 LED_D_OFF();
421 //wait until SSC_CLK goes LOW
422 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
423 if(BUTTON_PRESS()) {
424 DbpString("Stopped");
425 return;
426 }
427 WDT_HIT();
428 }
429
430 i++;
431 if(i == period) {
432
433 i = 0;
434 if (gap) {
435 SHORT_COIL();
436 SpinDelayUs(gap);
437 }
438 }
439 }
440}
441
e09f21fa 442#define DEBUG_FRAME_CONTENTS 1
443void SimulateTagLowFrequencyBidir(int divisor, int t0)
444{
445}
446
447// compose fc/8 fc/10 waveform (FSK2)
448static void fc(int c, int *n)
449{
450 uint8_t *dest = BigBuf_get_addr();
451 int idx;
452
453 // for when we want an fc8 pattern every 4 logical bits
454 if(c==0) {
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=1;
458 dest[((*n)++)]=1;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 dest[((*n)++)]=0;
462 dest[((*n)++)]=0;
463 }
464
712ebfa6 465 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
e09f21fa 466 if(c==8) {
467 for (idx=0; idx<6; idx++) {
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=1;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 dest[((*n)++)]=0;
475 dest[((*n)++)]=0;
476 }
477 }
478
712ebfa6 479 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
e09f21fa 480 if(c==10) {
481 for (idx=0; idx<5; idx++) {
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=1;
486 dest[((*n)++)]=1;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 dest[((*n)++)]=0;
491 dest[((*n)++)]=0;
492 }
493 }
494}
495// compose fc/X fc/Y waveform (FSKx)
712ebfa6 496static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
e09f21fa 497{
498 uint8_t *dest = BigBuf_get_addr();
712ebfa6 499 uint8_t halfFC = fc/2;
500 uint8_t wavesPerClock = clock/fc;
501 uint8_t mod = clock % fc; //modifier
502 uint8_t modAdj = fc/mod; //how often to apply modifier
503 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
e09f21fa 504 // loop through clock - step field clock
712ebfa6 505 for (uint8_t idx=0; idx < wavesPerClock; idx++){
506 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
507 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
508 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
509 *n += fc;
e09f21fa 510 }
511 if (mod>0) (*modCnt)++;
512 if ((mod>0) && modAdjOk){ //fsk2
513 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
712ebfa6 514 memset(dest+(*n), 0, fc-halfFC);
515 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
516 *n += fc;
e09f21fa 517 }
518 }
e09f21fa 519 if (mod>0 && !modAdjOk){ //fsk1
712ebfa6 520 memset(dest+(*n), 0, mod-(mod/2));
521 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
522 *n += mod;
e09f21fa 523 }
524}
525
526// prepare a waveform pattern in the buffer based on the ID given then
527// simulate a HID tag until the button is pressed
528void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
529{
530 int n=0, i=0;
531 /*
532 HID tag bitstream format
533 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
534 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
535 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
536 A fc8 is inserted before every 4 bits
537 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
538 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
539 */
540
541 if (hi>0xFFF) {
78f5b1a7 542 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
e09f21fa 543 return;
544 }
545 fc(0,&n);
546 // special start of frame marker containing invalid bit sequences
547 fc(8, &n); fc(8, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549 fc(10, &n); fc(10, &n); // invalid
550 fc(8, &n); fc(10, &n); // logical 0
551
552 WDT_HIT();
553 // manchester encode bits 43 to 32
554 for (i=11; i>=0; i--) {
555 if ((i%4)==3) fc(0,&n);
556 if ((hi>>i)&1) {
557 fc(10, &n); fc(8, &n); // low-high transition
558 } else {
559 fc(8, &n); fc(10, &n); // high-low transition
560 }
561 }
562
563 WDT_HIT();
564 // manchester encode bits 31 to 0
565 for (i=31; i>=0; i--) {
566 if ((i%4)==3) fc(0,&n);
567 if ((lo>>i)&1) {
568 fc(10, &n); fc(8, &n); // low-high transition
569 } else {
570 fc(8, &n); fc(10, &n); // high-low transition
571 }
572 }
573
574 if (ledcontrol)
575 LED_A_ON();
576 SimulateTagLowFrequency(n, 0, ledcontrol);
577
578 if (ledcontrol)
579 LED_A_OFF();
580}
581
582// prepare a waveform pattern in the buffer based on the ID given then
583// simulate a FSK tag until the button is pressed
584// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
585void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
586{
587 int ledcontrol=1;
588 int n=0, i=0;
589 uint8_t fcHigh = arg1 >> 8;
590 uint8_t fcLow = arg1 & 0xFF;
591 uint16_t modCnt = 0;
e09f21fa 592 uint8_t clk = arg2 & 0xFF;
593 uint8_t invert = (arg2 >> 8) & 1;
712ebfa6 594
e09f21fa 595 for (i=0; i<size; i++){
596 if (BitStream[i] == invert){
597 fcAll(fcLow, &n, clk, &modCnt);
598 } else {
599 fcAll(fcHigh, &n, clk, &modCnt);
600 }
601 }
602 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
712ebfa6 603 /*Dbprintf("DEBUG: First 32:");
e09f21fa 604 uint8_t *dest = BigBuf_get_addr();
605 i=0;
606 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
607 i+=16;
608 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
78f5b1a7 609 */
e09f21fa 610 if (ledcontrol)
611 LED_A_ON();
712ebfa6 612
78f5b1a7 613 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 614
615 if (ledcontrol)
616 LED_A_OFF();
617}
618
619// compose ask waveform for one bit(ASK)
620static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
621{
622 uint8_t *dest = BigBuf_get_addr();
712ebfa6 623 uint8_t halfClk = clock/2;
e09f21fa 624 // c = current bit 1 or 0
712ebfa6 625 if (manchester){
626 memset(dest+(*n), c, halfClk);
627 memset(dest+(*n) + halfClk, c^1, halfClk);
e09f21fa 628 } else {
712ebfa6 629 memset(dest+(*n), c, clock);
e09f21fa 630 }
712ebfa6 631 *n += clock;
e09f21fa 632}
633
634// args clock, ask/man or askraw, invert, transmission separator
635void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
636{
637 int ledcontrol = 1;
638 int n=0, i=0;
639 uint8_t clk = (arg1 >> 8) & 0xFF;
640 uint8_t manchester = arg1 & 1;
641 uint8_t separator = arg2 & 1;
642 uint8_t invert = (arg2 >> 8) & 1;
e09f21fa 643 for (i=0; i<size; i++){
644 askSimBit(BitStream[i]^invert, &n, clk, manchester);
645 }
ada339a1 646 if (manchester==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
647 for (i=0; i<size; i++){
648 askSimBit(BitStream[i]^invert^1, &n, clk, manchester);
649 }
650 }
712ebfa6 651 if (separator==1) Dbprintf("sorry but separator option not yet available");
e09f21fa 652
653 Dbprintf("Simulating with clk: %d, invert: %d, manchester: %d, separator: %d, n: %d",clk, invert, manchester, separator, n);
654 //DEBUG
712ebfa6 655 //Dbprintf("First 32:");
e09f21fa 656 //uint8_t *dest = BigBuf_get_addr();
657 //i=0;
658 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
659 //i+=16;
660 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
e09f21fa 661
662 if (ledcontrol)
663 LED_A_ON();
712ebfa6 664
78f5b1a7 665 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 666
667 if (ledcontrol)
668 LED_A_OFF();
669}
670
671//carrier can be 2,4 or 8
672static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
673{
674 uint8_t *dest = BigBuf_get_addr();
712ebfa6 675 uint8_t halfWave = waveLen/2;
676 //uint8_t idx;
e09f21fa 677 int i = 0;
678 if (phaseChg){
679 // write phase change
712ebfa6 680 memset(dest+(*n), *curPhase^1, halfWave);
681 memset(dest+(*n) + halfWave, *curPhase, halfWave);
682 *n += waveLen;
e09f21fa 683 *curPhase ^= 1;
712ebfa6 684 i += waveLen;
e09f21fa 685 }
686 //write each normal clock wave for the clock duration
687 for (; i < clk; i+=waveLen){
712ebfa6 688 memset(dest+(*n), *curPhase, halfWave);
689 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
690 *n += waveLen;
e09f21fa 691 }
692}
693
694// args clock, carrier, invert,
695void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
696{
697 int ledcontrol=1;
698 int n=0, i=0;
699 uint8_t clk = arg1 >> 8;
700 uint8_t carrier = arg1 & 0xFF;
701 uint8_t invert = arg2 & 0xFF;
78f5b1a7 702 uint8_t curPhase = 0;
e09f21fa 703 for (i=0; i<size; i++){
704 if (BitStream[i] == curPhase){
705 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
706 } else {
707 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
708 }
709 }
710 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
712ebfa6 711 //Dbprintf("DEBUG: First 32:");
712 //uint8_t *dest = BigBuf_get_addr();
713 //i=0;
714 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
715 //i+=16;
716 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
e09f21fa 717
718 if (ledcontrol)
719 LED_A_ON();
78f5b1a7 720 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 721
722 if (ledcontrol)
723 LED_A_OFF();
724}
725
726// loop to get raw HID waveform then FSK demodulate the TAG ID from it
727void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
728{
729 uint8_t *dest = BigBuf_get_addr();
730 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
731 size_t size = 0;
732 uint32_t hi2=0, hi=0, lo=0;
733 int idx=0;
734 // Configure to go in 125Khz listen mode
735 LFSetupFPGAForADC(95, true);
736
737 while(!BUTTON_PRESS()) {
738
739 WDT_HIT();
740 if (ledcontrol) LED_A_ON();
741
742 DoAcquisition_default(-1,true);
743 // FSK demodulator
744 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
745 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
746
747 if (idx>0 && lo>0){
748 // final loop, go over previously decoded manchester data and decode into usable tag ID
749 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
750 if (hi2 != 0){ //extra large HID tags
751 Dbprintf("TAG ID: %x%08x%08x (%d)",
752 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
753 }else { //standard HID tags <38 bits
754 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
755 uint8_t bitlen = 0;
756 uint32_t fc = 0;
757 uint32_t cardnum = 0;
758 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
759 uint32_t lo2=0;
760 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
761 uint8_t idx3 = 1;
762 while(lo2 > 1){ //find last bit set to 1 (format len bit)
763 lo2=lo2 >> 1;
764 idx3++;
765 }
766 bitlen = idx3+19;
767 fc =0;
768 cardnum=0;
769 if(bitlen == 26){
770 cardnum = (lo>>1)&0xFFFF;
771 fc = (lo>>17)&0xFF;
772 }
773 if(bitlen == 37){
774 cardnum = (lo>>1)&0x7FFFF;
775 fc = ((hi&0xF)<<12)|(lo>>20);
776 }
777 if(bitlen == 34){
778 cardnum = (lo>>1)&0xFFFF;
779 fc= ((hi&1)<<15)|(lo>>17);
780 }
781 if(bitlen == 35){
782 cardnum = (lo>>1)&0xFFFFF;
783 fc = ((hi&1)<<11)|(lo>>21);
784 }
785 }
786 else { //if bit 38 is not set then 37 bit format is used
787 bitlen= 37;
788 fc =0;
789 cardnum=0;
790 if(bitlen==37){
791 cardnum = (lo>>1)&0x7FFFF;
792 fc = ((hi&0xF)<<12)|(lo>>20);
793 }
794 }
795 //Dbprintf("TAG ID: %x%08x (%d)",
796 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
797 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
798 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
799 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
800 }
801 if (findone){
802 if (ledcontrol) LED_A_OFF();
803 *high = hi;
804 *low = lo;
805 return;
806 }
807 // reset
808 hi2 = hi = lo = 0;
809 }
810 WDT_HIT();
811 }
812 DbpString("Stopped");
813 if (ledcontrol) LED_A_OFF();
814}
815
816void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
817{
818 uint8_t *dest = BigBuf_get_addr();
819
820 size_t size=0, idx=0;
821 int clk=0, invert=0, errCnt=0, maxErr=20;
822 uint64_t lo=0;
823 // Configure to go in 125Khz listen mode
824 LFSetupFPGAForADC(95, true);
825
826 while(!BUTTON_PRESS()) {
827
828 WDT_HIT();
829 if (ledcontrol) LED_A_ON();
830
831 DoAcquisition_default(-1,true);
832 size = BigBuf_max_traceLen();
833 //Dbprintf("DEBUG: Buffer got");
834 //askdemod and manchester decode
835 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
836 //Dbprintf("DEBUG: ASK Got");
837 WDT_HIT();
838
839 if (errCnt>=0){
840 lo = Em410xDecode(dest, &size, &idx);
841 //Dbprintf("DEBUG: EM GOT");
842 if (lo>0){
843 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
844 (uint32_t)(lo>>32),
845 (uint32_t)lo,
846 (uint32_t)(lo&0xFFFF),
847 (uint32_t)((lo>>16LL) & 0xFF),
848 (uint32_t)(lo & 0xFFFFFF));
849 }
850 if (findone){
851 if (ledcontrol) LED_A_OFF();
852 *high=lo>>32;
853 *low=lo & 0xFFFFFFFF;
854 return;
855 }
856 } else{
857 //Dbprintf("DEBUG: No Tag");
858 }
859 WDT_HIT();
860 lo = 0;
861 clk=0;
862 invert=0;
863 errCnt=0;
864 size=0;
865 }
866 DbpString("Stopped");
867 if (ledcontrol) LED_A_OFF();
868}
869
870void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
871{
872 uint8_t *dest = BigBuf_get_addr();
873 int idx=0;
874 uint32_t code=0, code2=0;
875 uint8_t version=0;
876 uint8_t facilitycode=0;
877 uint16_t number=0;
878 // Configure to go in 125Khz listen mode
879 LFSetupFPGAForADC(95, true);
880
881 while(!BUTTON_PRESS()) {
882 WDT_HIT();
883 if (ledcontrol) LED_A_ON();
884 DoAcquisition_default(-1,true);
885 //fskdemod and get start index
886 WDT_HIT();
887 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
888 if (idx>0){
889 //valid tag found
890
891 //Index map
892 //0 10 20 30 40 50 60
893 //| | | | | | |
894 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
895 //-----------------------------------------------------------------------------
896 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
897 //
898 //XSF(version)facility:codeone+codetwo
899 //Handle the data
900 if(findone){ //only print binary if we are doing one
901 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
902 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
903 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
904 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
905 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
906 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
907 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
908 }
909 code = bytebits_to_byte(dest+idx,32);
910 code2 = bytebits_to_byte(dest+idx+32,32);
911 version = bytebits_to_byte(dest+idx+27,8); //14,4
912 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
913 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
914
915 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
916 // if we're only looking for one tag
917 if (findone){
918 if (ledcontrol) LED_A_OFF();
919 //LED_A_OFF();
920 *high=code;
921 *low=code2;
922 return;
923 }
924 code=code2=0;
925 version=facilitycode=0;
926 number=0;
927 idx=0;
928 }
929 WDT_HIT();
930 }
931 DbpString("Stopped");
932 if (ledcontrol) LED_A_OFF();
933}
934
935/*------------------------------
936 * T5555/T5557/T5567 routines
937 *------------------------------
938 */
939
940/* T55x7 configuration register definitions */
941#define T55x7_POR_DELAY 0x00000001
942#define T55x7_ST_TERMINATOR 0x00000008
943#define T55x7_PWD 0x00000010
944#define T55x7_MAXBLOCK_SHIFT 5
945#define T55x7_AOR 0x00000200
946#define T55x7_PSKCF_RF_2 0
947#define T55x7_PSKCF_RF_4 0x00000400
948#define T55x7_PSKCF_RF_8 0x00000800
949#define T55x7_MODULATION_DIRECT 0
950#define T55x7_MODULATION_PSK1 0x00001000
951#define T55x7_MODULATION_PSK2 0x00002000
952#define T55x7_MODULATION_PSK3 0x00003000
953#define T55x7_MODULATION_FSK1 0x00004000
954#define T55x7_MODULATION_FSK2 0x00005000
955#define T55x7_MODULATION_FSK1a 0x00006000
956#define T55x7_MODULATION_FSK2a 0x00007000
957#define T55x7_MODULATION_MANCHESTER 0x00008000
958#define T55x7_MODULATION_BIPHASE 0x00010000
959#define T55x7_BITRATE_RF_8 0
960#define T55x7_BITRATE_RF_16 0x00040000
961#define T55x7_BITRATE_RF_32 0x00080000
962#define T55x7_BITRATE_RF_40 0x000C0000
963#define T55x7_BITRATE_RF_50 0x00100000
964#define T55x7_BITRATE_RF_64 0x00140000
965#define T55x7_BITRATE_RF_100 0x00180000
966#define T55x7_BITRATE_RF_128 0x001C0000
967
968/* T5555 (Q5) configuration register definitions */
969#define T5555_ST_TERMINATOR 0x00000001
970#define T5555_MAXBLOCK_SHIFT 0x00000001
971#define T5555_MODULATION_MANCHESTER 0
972#define T5555_MODULATION_PSK1 0x00000010
973#define T5555_MODULATION_PSK2 0x00000020
974#define T5555_MODULATION_PSK3 0x00000030
975#define T5555_MODULATION_FSK1 0x00000040
976#define T5555_MODULATION_FSK2 0x00000050
977#define T5555_MODULATION_BIPHASE 0x00000060
978#define T5555_MODULATION_DIRECT 0x00000070
979#define T5555_INVERT_OUTPUT 0x00000080
980#define T5555_PSK_RF_2 0
981#define T5555_PSK_RF_4 0x00000100
982#define T5555_PSK_RF_8 0x00000200
983#define T5555_USE_PWD 0x00000400
984#define T5555_USE_AOR 0x00000800
985#define T5555_BITRATE_SHIFT 12
986#define T5555_FAST_WRITE 0x00004000
987#define T5555_PAGE_SELECT 0x00008000
988
989/*
990 * Relevant times in microsecond
991 * To compensate antenna falling times shorten the write times
992 * and enlarge the gap ones.
993 */
994#define START_GAP 250
995#define WRITE_GAP 160
996#define WRITE_0 144 // 192
997#define WRITE_1 400 // 432 for T55x7; 448 for E5550
998
999// Write one bit to card
1000void T55xxWriteBit(int bit)
1001{
1002 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1003 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1004 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1005 if (bit == 0)
1006 SpinDelayUs(WRITE_0);
1007 else
1008 SpinDelayUs(WRITE_1);
1009 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1010 SpinDelayUs(WRITE_GAP);
1011}
1012
1013// Write one card block in page 0, no lock
1014void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1015{
1016 //unsigned int i; //enio adjustment 12/10/14
1017 uint32_t i;
1018
1019 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1020 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1021 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1022
1023 // Give it a bit of time for the resonant antenna to settle.
1024 // And for the tag to fully power up
1025 SpinDelay(150);
1026
1027 // Now start writting
1028 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1029 SpinDelayUs(START_GAP);
1030
1031 // Opcode
1032 T55xxWriteBit(1);
1033 T55xxWriteBit(0); //Page 0
1034 if (PwdMode == 1){
1035 // Pwd
1036 for (i = 0x80000000; i != 0; i >>= 1)
1037 T55xxWriteBit(Pwd & i);
1038 }
1039 // Lock bit
1040 T55xxWriteBit(0);
1041
1042 // Data
1043 for (i = 0x80000000; i != 0; i >>= 1)
1044 T55xxWriteBit(Data & i);
1045
1046 // Block
1047 for (i = 0x04; i != 0; i >>= 1)
1048 T55xxWriteBit(Block & i);
1049
1050 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1051 // so wait a little more)
1052 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1053 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1054 SpinDelay(20);
1055 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1056}
1057
1058// Read one card block in page 0
1059void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1060{
1061 uint8_t *dest = BigBuf_get_addr();
1062 //int m=0, i=0; //enio adjustment 12/10/14
1063 uint32_t m=0, i=0;
1064 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1065 m = BigBuf_max_traceLen();
1066 // Clear destination buffer before sending the command
1067 memset(dest, 128, m);
1068 // Connect the A/D to the peak-detected low-frequency path.
1069 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1070 // Now set up the SSC to get the ADC samples that are now streaming at us.
1071 FpgaSetupSsc();
1072
1073 LED_D_ON();
1074 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1075 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1076
1077 // Give it a bit of time for the resonant antenna to settle.
1078 // And for the tag to fully power up
1079 SpinDelay(150);
1080
1081 // Now start writting
1082 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1083 SpinDelayUs(START_GAP);
1084
1085 // Opcode
1086 T55xxWriteBit(1);
1087 T55xxWriteBit(0); //Page 0
1088 if (PwdMode == 1){
1089 // Pwd
1090 for (i = 0x80000000; i != 0; i >>= 1)
1091 T55xxWriteBit(Pwd & i);
1092 }
1093 // Lock bit
1094 T55xxWriteBit(0);
1095 // Block
1096 for (i = 0x04; i != 0; i >>= 1)
1097 T55xxWriteBit(Block & i);
1098
1099 // Turn field on to read the response
1100 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1101 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1102
1103 // Now do the acquisition
1104 i = 0;
1105 for(;;) {
1106 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1107 AT91C_BASE_SSC->SSC_THR = 0x43;
1108 }
1109 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1110 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1111 // we don't care about actual value, only if it's more or less than a
1112 // threshold essentially we capture zero crossings for later analysis
1113 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1114 i++;
1115 if (i >= m) break;
1116 }
1117 }
1118
1119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1120 LED_D_OFF();
1121 DbpString("DONE!");
1122}
1123
1124// Read card traceability data (page 1)
1125void T55xxReadTrace(void){
1126 uint8_t *dest = BigBuf_get_addr();
1127 int m=0, i=0;
1128
1129 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1130 m = BigBuf_max_traceLen();
1131 // Clear destination buffer before sending the command
1132 memset(dest, 128, m);
1133 // Connect the A/D to the peak-detected low-frequency path.
1134 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1135 // Now set up the SSC to get the ADC samples that are now streaming at us.
1136 FpgaSetupSsc();
1137
1138 LED_D_ON();
1139 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1140 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1141
1142 // Give it a bit of time for the resonant antenna to settle.
1143 // And for the tag to fully power up
1144 SpinDelay(150);
1145
1146 // Now start writting
1147 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1148 SpinDelayUs(START_GAP);
1149
1150 // Opcode
1151 T55xxWriteBit(1);
1152 T55xxWriteBit(1); //Page 1
1153
1154 // Turn field on to read the response
1155 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1156 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1157
1158 // Now do the acquisition
1159 i = 0;
1160 for(;;) {
1161 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1162 AT91C_BASE_SSC->SSC_THR = 0x43;
1163 }
1164 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1165 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1166 i++;
1167 if (i >= m) break;
1168 }
1169 }
1170
1171 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1172 LED_D_OFF();
1173 DbpString("DONE!");
1174}
1175
1176/*-------------- Cloning routines -----------*/
1177// Copy HID id to card and setup block 0 config
1178void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1179{
1180 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1181 int last_block = 0;
1182
1183 if (longFMT){
1184 // Ensure no more than 84 bits supplied
1185 if (hi2>0xFFFFF) {
1186 DbpString("Tags can only have 84 bits.");
1187 return;
1188 }
1189 // Build the 6 data blocks for supplied 84bit ID
1190 last_block = 6;
1191 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1192 for (int i=0;i<4;i++) {
1193 if (hi2 & (1<<(19-i)))
1194 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1195 else
1196 data1 |= (1<<((3-i)*2)); // 0 -> 01
1197 }
1198
1199 data2 = 0;
1200 for (int i=0;i<16;i++) {
1201 if (hi2 & (1<<(15-i)))
1202 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1203 else
1204 data2 |= (1<<((15-i)*2)); // 0 -> 01
1205 }
1206
1207 data3 = 0;
1208 for (int i=0;i<16;i++) {
1209 if (hi & (1<<(31-i)))
1210 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1211 else
1212 data3 |= (1<<((15-i)*2)); // 0 -> 01
1213 }
1214
1215 data4 = 0;
1216 for (int i=0;i<16;i++) {
1217 if (hi & (1<<(15-i)))
1218 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1219 else
1220 data4 |= (1<<((15-i)*2)); // 0 -> 01
1221 }
1222
1223 data5 = 0;
1224 for (int i=0;i<16;i++) {
1225 if (lo & (1<<(31-i)))
1226 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1227 else
1228 data5 |= (1<<((15-i)*2)); // 0 -> 01
1229 }
1230
1231 data6 = 0;
1232 for (int i=0;i<16;i++) {
1233 if (lo & (1<<(15-i)))
1234 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1235 else
1236 data6 |= (1<<((15-i)*2)); // 0 -> 01
1237 }
1238 }
1239 else {
1240 // Ensure no more than 44 bits supplied
1241 if (hi>0xFFF) {
1242 DbpString("Tags can only have 44 bits.");
1243 return;
1244 }
1245
1246 // Build the 3 data blocks for supplied 44bit ID
1247 last_block = 3;
1248
1249 data1 = 0x1D000000; // load preamble
1250
1251 for (int i=0;i<12;i++) {
1252 if (hi & (1<<(11-i)))
1253 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1254 else
1255 data1 |= (1<<((11-i)*2)); // 0 -> 01
1256 }
1257
1258 data2 = 0;
1259 for (int i=0;i<16;i++) {
1260 if (lo & (1<<(31-i)))
1261 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1262 else
1263 data2 |= (1<<((15-i)*2)); // 0 -> 01
1264 }
1265
1266 data3 = 0;
1267 for (int i=0;i<16;i++) {
1268 if (lo & (1<<(15-i)))
1269 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1270 else
1271 data3 |= (1<<((15-i)*2)); // 0 -> 01
1272 }
1273 }
1274
1275 LED_D_ON();
1276 // Program the data blocks for supplied ID
1277 // and the block 0 for HID format
1278 T55xxWriteBlock(data1,1,0,0);
1279 T55xxWriteBlock(data2,2,0,0);
1280 T55xxWriteBlock(data3,3,0,0);
1281
1282 if (longFMT) { // if long format there are 6 blocks
1283 T55xxWriteBlock(data4,4,0,0);
1284 T55xxWriteBlock(data5,5,0,0);
1285 T55xxWriteBlock(data6,6,0,0);
1286 }
1287
1288 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1289 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1290 T55x7_MODULATION_FSK2a |
1291 last_block << T55x7_MAXBLOCK_SHIFT,
1292 0,0,0);
1293
1294 LED_D_OFF();
1295
1296 DbpString("DONE!");
1297}
1298
1299void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1300{
1301 int data1=0, data2=0; //up to six blocks for long format
1302
1303 data1 = hi; // load preamble
1304 data2 = lo;
1305
1306 LED_D_ON();
1307 // Program the data blocks for supplied ID
1308 // and the block 0 for HID format
1309 T55xxWriteBlock(data1,1,0,0);
1310 T55xxWriteBlock(data2,2,0,0);
1311
1312 //Config Block
1313 T55xxWriteBlock(0x00147040,0,0,0);
1314 LED_D_OFF();
1315
1316 DbpString("DONE!");
1317}
1318
1319// Define 9bit header for EM410x tags
1320#define EM410X_HEADER 0x1FF
1321#define EM410X_ID_LENGTH 40
1322
1323void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1324{
1325 int i, id_bit;
1326 uint64_t id = EM410X_HEADER;
1327 uint64_t rev_id = 0; // reversed ID
1328 int c_parity[4]; // column parity
1329 int r_parity = 0; // row parity
1330 uint32_t clock = 0;
1331
1332 // Reverse ID bits given as parameter (for simpler operations)
1333 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1334 if (i < 32) {
1335 rev_id = (rev_id << 1) | (id_lo & 1);
1336 id_lo >>= 1;
1337 } else {
1338 rev_id = (rev_id << 1) | (id_hi & 1);
1339 id_hi >>= 1;
1340 }
1341 }
1342
1343 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1344 id_bit = rev_id & 1;
1345
1346 if (i % 4 == 0) {
1347 // Don't write row parity bit at start of parsing
1348 if (i)
1349 id = (id << 1) | r_parity;
1350 // Start counting parity for new row
1351 r_parity = id_bit;
1352 } else {
1353 // Count row parity
1354 r_parity ^= id_bit;
1355 }
1356
1357 // First elements in column?
1358 if (i < 4)
1359 // Fill out first elements
1360 c_parity[i] = id_bit;
1361 else
1362 // Count column parity
1363 c_parity[i % 4] ^= id_bit;
1364
1365 // Insert ID bit
1366 id = (id << 1) | id_bit;
1367 rev_id >>= 1;
1368 }
1369
1370 // Insert parity bit of last row
1371 id = (id << 1) | r_parity;
1372
1373 // Fill out column parity at the end of tag
1374 for (i = 0; i < 4; ++i)
1375 id = (id << 1) | c_parity[i];
1376
1377 // Add stop bit
1378 id <<= 1;
1379
1380 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1381 LED_D_ON();
1382
1383 // Write EM410x ID
1384 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1385 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1386
1387 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1388 if (card) {
1389 // Clock rate is stored in bits 8-15 of the card value
1390 clock = (card & 0xFF00) >> 8;
1391 Dbprintf("Clock rate: %d", clock);
1392 switch (clock)
1393 {
1394 case 32:
1395 clock = T55x7_BITRATE_RF_32;
1396 break;
1397 case 16:
1398 clock = T55x7_BITRATE_RF_16;
1399 break;
1400 case 0:
1401 // A value of 0 is assumed to be 64 for backwards-compatibility
1402 // Fall through...
1403 case 64:
1404 clock = T55x7_BITRATE_RF_64;
1405 break;
1406 default:
1407 Dbprintf("Invalid clock rate: %d", clock);
1408 return;
1409 }
1410
1411 // Writing configuration for T55x7 tag
1412 T55xxWriteBlock(clock |
1413 T55x7_MODULATION_MANCHESTER |
1414 2 << T55x7_MAXBLOCK_SHIFT,
1415 0, 0, 0);
1416 }
1417 else
1418 // Writing configuration for T5555(Q5) tag
1419 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1420 T5555_MODULATION_MANCHESTER |
1421 2 << T5555_MAXBLOCK_SHIFT,
1422 0, 0, 0);
1423
1424 LED_D_OFF();
1425 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1426 (uint32_t)(id >> 32), (uint32_t)id);
1427}
1428
1429// Clone Indala 64-bit tag by UID to T55x7
1430void CopyIndala64toT55x7(int hi, int lo)
1431{
1432
1433 //Program the 2 data blocks for supplied 64bit UID
1434 // and the block 0 for Indala64 format
1435 T55xxWriteBlock(hi,1,0,0);
1436 T55xxWriteBlock(lo,2,0,0);
1437 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1438 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1439 T55x7_MODULATION_PSK1 |
1440 2 << T55x7_MAXBLOCK_SHIFT,
1441 0, 0, 0);
1442 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1443 // T5567WriteBlock(0x603E1042,0);
1444
1445 DbpString("DONE!");
1446
1447}
1448
1449void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1450{
1451
1452 //Program the 7 data blocks for supplied 224bit UID
1453 // and the block 0 for Indala224 format
1454 T55xxWriteBlock(uid1,1,0,0);
1455 T55xxWriteBlock(uid2,2,0,0);
1456 T55xxWriteBlock(uid3,3,0,0);
1457 T55xxWriteBlock(uid4,4,0,0);
1458 T55xxWriteBlock(uid5,5,0,0);
1459 T55xxWriteBlock(uid6,6,0,0);
1460 T55xxWriteBlock(uid7,7,0,0);
1461 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1462 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1463 T55x7_MODULATION_PSK1 |
1464 7 << T55x7_MAXBLOCK_SHIFT,
1465 0,0,0);
1466 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1467 // T5567WriteBlock(0x603E10E2,0);
1468
1469 DbpString("DONE!");
1470
1471}
1472
1473
1474#define abs(x) ( ((x)<0) ? -(x) : (x) )
1475#define max(x,y) ( x<y ? y:x)
1476
1477int DemodPCF7931(uint8_t **outBlocks) {
1478 uint8_t BitStream[256];
1479 uint8_t Blocks[8][16];
1480 uint8_t *GraphBuffer = BigBuf_get_addr();
1481 int GraphTraceLen = BigBuf_max_traceLen();
1482 int i, j, lastval, bitidx, half_switch;
1483 int clock = 64;
1484 int tolerance = clock / 8;
1485 int pmc, block_done;
1486 int lc, warnings = 0;
1487 int num_blocks = 0;
1488 int lmin=128, lmax=128;
1489 uint8_t dir;
1490
1491 LFSetupFPGAForADC(95, true);
1492 DoAcquisition_default(0, 0);
1493
1494
1495 lmin = 64;
1496 lmax = 192;
1497
1498 i = 2;
1499
1500 /* Find first local max/min */
1501 if(GraphBuffer[1] > GraphBuffer[0]) {
1502 while(i < GraphTraceLen) {
1503 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1504 break;
1505 i++;
1506 }
1507 dir = 0;
1508 }
1509 else {
1510 while(i < GraphTraceLen) {
1511 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1512 break;
1513 i++;
1514 }
1515 dir = 1;
1516 }
1517
1518 lastval = i++;
1519 half_switch = 0;
1520 pmc = 0;
1521 block_done = 0;
1522
1523 for (bitidx = 0; i < GraphTraceLen; i++)
1524 {
1525 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1526 {
1527 lc = i - lastval;
1528 lastval = i;
1529
1530 // Switch depending on lc length:
1531 // Tolerance is 1/8 of clock rate (arbitrary)
1532 if (abs(lc-clock/4) < tolerance) {
1533 // 16T0
1534 if((i - pmc) == lc) { /* 16T0 was previous one */
1535 /* It's a PMC ! */
1536 i += (128+127+16+32+33+16)-1;
1537 lastval = i;
1538 pmc = 0;
1539 block_done = 1;
1540 }
1541 else {
1542 pmc = i;
1543 }
1544 } else if (abs(lc-clock/2) < tolerance) {
1545 // 32TO
1546 if((i - pmc) == lc) { /* 16T0 was previous one */
1547 /* It's a PMC ! */
1548 i += (128+127+16+32+33)-1;
1549 lastval = i;
1550 pmc = 0;
1551 block_done = 1;
1552 }
1553 else if(half_switch == 1) {
1554 BitStream[bitidx++] = 0;
1555 half_switch = 0;
1556 }
1557 else
1558 half_switch++;
1559 } else if (abs(lc-clock) < tolerance) {
1560 // 64TO
1561 BitStream[bitidx++] = 1;
1562 } else {
1563 // Error
1564 warnings++;
1565 if (warnings > 10)
1566 {
1567 Dbprintf("Error: too many detection errors, aborting.");
1568 return 0;
1569 }
1570 }
1571
1572 if(block_done == 1) {
1573 if(bitidx == 128) {
1574 for(j=0; j<16; j++) {
1575 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1576 64*BitStream[j*8+6]+
1577 32*BitStream[j*8+5]+
1578 16*BitStream[j*8+4]+
1579 8*BitStream[j*8+3]+
1580 4*BitStream[j*8+2]+
1581 2*BitStream[j*8+1]+
1582 BitStream[j*8];
1583 }
1584 num_blocks++;
1585 }
1586 bitidx = 0;
1587 block_done = 0;
1588 half_switch = 0;
1589 }
1590 if(i < GraphTraceLen)
1591 {
1592 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1593 else dir = 1;
1594 }
1595 }
1596 if(bitidx==255)
1597 bitidx=0;
1598 warnings = 0;
1599 if(num_blocks == 4) break;
1600 }
1601 memcpy(outBlocks, Blocks, 16*num_blocks);
1602 return num_blocks;
1603}
1604
1605int IsBlock0PCF7931(uint8_t *Block) {
1606 // Assume RFU means 0 :)
1607 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1608 return 1;
1609 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1610 return 1;
1611 return 0;
1612}
1613
1614int IsBlock1PCF7931(uint8_t *Block) {
1615 // Assume RFU means 0 :)
1616 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1617 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1618 return 1;
1619
1620 return 0;
1621}
1622
1623#define ALLOC 16
1624
1625void ReadPCF7931() {
1626 uint8_t Blocks[8][17];
1627 uint8_t tmpBlocks[4][16];
1628 int i, j, ind, ind2, n;
1629 int num_blocks = 0;
1630 int max_blocks = 8;
1631 int ident = 0;
1632 int error = 0;
1633 int tries = 0;
1634
1635 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1636
1637 do {
1638 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1639 n = DemodPCF7931((uint8_t**)tmpBlocks);
1640 if(!n)
1641 error++;
1642 if(error==10 && num_blocks == 0) {
1643 Dbprintf("Error, no tag or bad tag");
1644 return;
1645 }
1646 else if (tries==20 || error==10) {
1647 Dbprintf("Error reading the tag");
1648 Dbprintf("Here is the partial content");
1649 goto end;
1650 }
1651
1652 for(i=0; i<n; i++)
1653 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1654 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1655 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1656 if(!ident) {
1657 for(i=0; i<n; i++) {
1658 if(IsBlock0PCF7931(tmpBlocks[i])) {
1659 // Found block 0 ?
1660 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1661 // Found block 1!
1662 // \o/
1663 ident = 1;
1664 memcpy(Blocks[0], tmpBlocks[i], 16);
1665 Blocks[0][ALLOC] = 1;
1666 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1667 Blocks[1][ALLOC] = 1;
1668 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1669 // Debug print
1670 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1671 num_blocks = 2;
1672 // Handle following blocks
1673 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1674 if(j==n) j=0;
1675 if(j==i) break;
1676 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1677 Blocks[ind2][ALLOC] = 1;
1678 }
1679 break;
1680 }
1681 }
1682 }
1683 }
1684 else {
1685 for(i=0; i<n; i++) { // Look for identical block in known blocks
1686 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1687 for(j=0; j<max_blocks; j++) {
1688 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1689 // Found an identical block
1690 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1691 if(ind2 < 0)
1692 ind2 = max_blocks;
1693 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1694 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1695 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1696 Blocks[ind2][ALLOC] = 1;
1697 num_blocks++;
1698 if(num_blocks == max_blocks) goto end;
1699 }
1700 }
1701 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1702 if(ind2 > max_blocks)
1703 ind2 = 0;
1704 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1705 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1706 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1707 Blocks[ind2][ALLOC] = 1;
1708 num_blocks++;
1709 if(num_blocks == max_blocks) goto end;
1710 }
1711 }
1712 }
1713 }
1714 }
1715 }
1716 }
1717 tries++;
1718 if (BUTTON_PRESS()) return;
1719 } while (num_blocks != max_blocks);
1720 end:
1721 Dbprintf("-----------------------------------------");
1722 Dbprintf("Memory content:");
1723 Dbprintf("-----------------------------------------");
1724 for(i=0; i<max_blocks; i++) {
1725 if(Blocks[i][ALLOC]==1)
1726 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1727 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1728 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1729 else
1730 Dbprintf("<missing block %d>", i);
1731 }
1732 Dbprintf("-----------------------------------------");
1733
1734 return ;
1735}
1736
1737
1738//-----------------------------------
1739// EM4469 / EM4305 routines
1740//-----------------------------------
1741#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1742#define FWD_CMD_WRITE 0xA
1743#define FWD_CMD_READ 0x9
1744#define FWD_CMD_DISABLE 0x5
1745
1746
1747uint8_t forwardLink_data[64]; //array of forwarded bits
1748uint8_t * forward_ptr; //ptr for forward message preparation
1749uint8_t fwd_bit_sz; //forwardlink bit counter
1750uint8_t * fwd_write_ptr; //forwardlink bit pointer
1751
1752//====================================================================
1753// prepares command bits
1754// see EM4469 spec
1755//====================================================================
1756//--------------------------------------------------------------------
1757uint8_t Prepare_Cmd( uint8_t cmd ) {
1758 //--------------------------------------------------------------------
1759
1760 *forward_ptr++ = 0; //start bit
1761 *forward_ptr++ = 0; //second pause for 4050 code
1762
1763 *forward_ptr++ = cmd;
1764 cmd >>= 1;
1765 *forward_ptr++ = cmd;
1766 cmd >>= 1;
1767 *forward_ptr++ = cmd;
1768 cmd >>= 1;
1769 *forward_ptr++ = cmd;
1770
1771 return 6; //return number of emited bits
1772}
1773
1774//====================================================================
1775// prepares address bits
1776// see EM4469 spec
1777//====================================================================
1778
1779//--------------------------------------------------------------------
1780uint8_t Prepare_Addr( uint8_t addr ) {
1781 //--------------------------------------------------------------------
1782
1783 register uint8_t line_parity;
1784
1785 uint8_t i;
1786 line_parity = 0;
1787 for(i=0;i<6;i++) {
1788 *forward_ptr++ = addr;
1789 line_parity ^= addr;
1790 addr >>= 1;
1791 }
1792
1793 *forward_ptr++ = (line_parity & 1);
1794
1795 return 7; //return number of emited bits
1796}
1797
1798//====================================================================
1799// prepares data bits intreleaved with parity bits
1800// see EM4469 spec
1801//====================================================================
1802
1803//--------------------------------------------------------------------
1804uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1805 //--------------------------------------------------------------------
1806
1807 register uint8_t line_parity;
1808 register uint8_t column_parity;
1809 register uint8_t i, j;
1810 register uint16_t data;
1811
1812 data = data_low;
1813 column_parity = 0;
1814
1815 for(i=0; i<4; i++) {
1816 line_parity = 0;
1817 for(j=0; j<8; j++) {
1818 line_parity ^= data;
1819 column_parity ^= (data & 1) << j;
1820 *forward_ptr++ = data;
1821 data >>= 1;
1822 }
1823 *forward_ptr++ = line_parity;
1824 if(i == 1)
1825 data = data_hi;
1826 }
1827
1828 for(j=0; j<8; j++) {
1829 *forward_ptr++ = column_parity;
1830 column_parity >>= 1;
1831 }
1832 *forward_ptr = 0;
1833
1834 return 45; //return number of emited bits
1835}
1836
1837//====================================================================
1838// Forward Link send function
1839// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1840// fwd_bit_count set with number of bits to be sent
1841//====================================================================
1842void SendForward(uint8_t fwd_bit_count) {
1843
1844 fwd_write_ptr = forwardLink_data;
1845 fwd_bit_sz = fwd_bit_count;
1846
1847 LED_D_ON();
1848
1849 //Field on
1850 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1851 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1852 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1853
1854 // Give it a bit of time for the resonant antenna to settle.
1855 // And for the tag to fully power up
1856 SpinDelay(150);
1857
1858 // force 1st mod pulse (start gap must be longer for 4305)
1859 fwd_bit_sz--; //prepare next bit modulation
1860 fwd_write_ptr++;
1861 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1862 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1863 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1864 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1865 SpinDelayUs(16*8); //16 cycles on (8us each)
1866
1867 // now start writting
1868 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1869 if(((*fwd_write_ptr++) & 1) == 1)
1870 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1871 else {
1872 //These timings work for 4469/4269/4305 (with the 55*8 above)
1873 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1874 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1875 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1876 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1877 SpinDelayUs(9*8); //16 cycles on (8us each)
1878 }
1879 }
1880}
1881
1882void EM4xLogin(uint32_t Password) {
1883
1884 uint8_t fwd_bit_count;
1885
1886 forward_ptr = forwardLink_data;
1887 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1888 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1889
1890 SendForward(fwd_bit_count);
1891
1892 //Wait for command to complete
1893 SpinDelay(20);
1894
1895}
1896
1897void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1898
1899 uint8_t fwd_bit_count;
1900 uint8_t *dest = BigBuf_get_addr();
1901 int m=0, i=0;
1902
1903 //If password mode do login
1904 if (PwdMode == 1) EM4xLogin(Pwd);
1905
1906 forward_ptr = forwardLink_data;
1907 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1908 fwd_bit_count += Prepare_Addr( Address );
1909
1910 m = BigBuf_max_traceLen();
1911 // Clear destination buffer before sending the command
1912 memset(dest, 128, m);
1913 // Connect the A/D to the peak-detected low-frequency path.
1914 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1915 // Now set up the SSC to get the ADC samples that are now streaming at us.
1916 FpgaSetupSsc();
1917
1918 SendForward(fwd_bit_count);
1919
1920 // Now do the acquisition
1921 i = 0;
1922 for(;;) {
1923 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1924 AT91C_BASE_SSC->SSC_THR = 0x43;
1925 }
1926 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1927 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1928 i++;
1929 if (i >= m) break;
1930 }
1931 }
1932 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1933 LED_D_OFF();
1934}
1935
1936void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1937
1938 uint8_t fwd_bit_count;
1939
1940 //If password mode do login
1941 if (PwdMode == 1) EM4xLogin(Pwd);
1942
1943 forward_ptr = forwardLink_data;
1944 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1945 fwd_bit_count += Prepare_Addr( Address );
1946 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1947
1948 SendForward(fwd_bit_count);
1949
1950 //Wait for write to complete
1951 SpinDelay(20);
1952 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1953 LED_D_OFF();
1954}
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