[proxmark3-svn] / armsrc / fpgaloader.c

//-----------------------------------------------------------------------------\r
// Routines to load the FPGA image, and then to configure the FPGA's major\r
// mode once it is configured.\r
//\r
// Jonathan Westhues, April 2006\r
//-----------------------------------------------------------------------------\r
#include <proxmark3.h>\r
#include "apps.h"\r
\r
//-----------------------------------------------------------------------------\r
// Set up the Serial Peripheral Interface as master\r
// Used to write the FPGA config word\r
// May also be used to write to other SPI attached devices like an LCD\r
//-----------------------------------------------------------------------------\r
void SetupSpi(int mode)\r
{\r
	// PA10 -> SPI_NCS2 chip select (LCD)\r
	// PA11 -> SPI_NCS0 chip select (FPGA)\r
	// PA12 -> SPI_MISO Master-In Slave-Out\r
	// PA13 -> SPI_MOSI Master-Out Slave-In\r
	// PA14 -> SPI_SPCK Serial Clock\r
\r
	// Disable PIO control of the following pins, allows use by the SPI peripheral\r
	PIO_DISABLE			 =	(1 << GPIO_NCS0)	|\r
							(1 << GPIO_NCS2) 	|\r
							(1 << GPIO_MISO)	|\r
							(1 << GPIO_MOSI)	|\r
							(1 << GPIO_SPCK);\r
\r
	PIO_PERIPHERAL_A_SEL =	(1 << GPIO_NCS0)	|\r
							(1 << GPIO_MISO)	|\r
							(1 << GPIO_MOSI)	|\r
							(1 << GPIO_SPCK);\r
\r
	PIO_PERIPHERAL_B_SEL =	(1 << GPIO_NCS2);\r
\r
	//enable the SPI Peripheral clock\r
	PMC_PERIPHERAL_CLK_ENABLE = (1<<PERIPH_SPI);\r
	// Enable SPI\r
	SPI_CONTROL = SPI_CONTROL_ENABLE;\r
\r
	switch (mode) {\r
		case SPI_FPGA_MODE:\r
			SPI_MODE =\r
				( 0 << 24)	|	// Delay between chip selects (take default: 6 MCK periods)\r
				(14 << 16)	|	// Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)\r
				( 0 << 7)	|	// Local Loopback Disabled\r
				( 1 << 4)	|	// Mode Fault Detection disabled\r
				( 0 << 2)	|	// Chip selects connected directly to peripheral\r
				( 0 << 1) 	|	// Fixed Peripheral Select\r
				( 1 << 0);		// Master Mode\r
			SPI_FOR_CHIPSEL_0 =\r
				( 1 << 24)	|	// Delay between Consecutive Transfers (32 MCK periods)\r
				( 1 << 16)	|	// Delay Before SPCK (1 MCK period)\r
				( 6 << 8)	|	// Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
				( 8 << 4)	|	// Bits per Transfer (16 bits)\r
				( 0 << 3)	|	// Chip Select inactive after transfer\r
				( 1 << 1)	|	// Clock Phase data captured on leading edge, changes on following edge\r
				( 0 << 0);		// Clock Polarity inactive state is logic 0\r
			break;\r
		case SPI_LCD_MODE:\r
			SPI_MODE =\r
				( 0 << 24)	|	// Delay between chip selects (take default: 6 MCK periods)\r
				(11 << 16)	|	// Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)\r
				( 0 << 7)	|	// Local Loopback Disabled\r
				( 1 << 4)	|	// Mode Fault Detection disabled\r
				( 0 << 2)	|	// Chip selects connected directly to peripheral\r
				( 0 << 1) 	|	// Fixed Peripheral Select\r
				( 1 << 0);		// Master Mode\r
			SPI_FOR_CHIPSEL_2 =\r
				( 1 << 24)	|	// Delay between Consecutive Transfers (32 MCK periods)\r
				( 1 << 16)	|	// Delay Before SPCK (1 MCK period)\r
				( 6 << 8)	|	// Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
				( 1 << 4)	|	// Bits per Transfer (9 bits)\r
				( 0 << 3)	|	// Chip Select inactive after transfer\r
				( 1 << 1)	|	// Clock Phase data captured on leading edge, changes on following edge\r
				( 0 << 0);		// Clock Polarity inactive state is logic 0\r
			break;\r
		default:				// Disable SPI\r
			SPI_CONTROL = SPI_CONTROL_DISABLE;\r
			break;\r
	}\r
}\r
\r
//-----------------------------------------------------------------------------\r
// Set up the synchronous serial port, with the one set of options that we\r
// always use when we are talking to the FPGA. Both RX and TX are enabled.\r
//-----------------------------------------------------------------------------\r
void FpgaSetupSsc(void)\r
{\r
	// First configure the GPIOs, and get ourselves a clock.\r
	PIO_PERIPHERAL_A_SEL =	(1 << GPIO_SSC_FRAME)	|\r
							(1 << GPIO_SSC_DIN)		|\r
							(1 << GPIO_SSC_DOUT)	|\r
							(1 << GPIO_SSC_CLK);\r
	PIO_DISABLE = (1 << GPIO_SSC_DOUT);\r
\r
	PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_SSC);\r
\r
	// Now set up the SSC proper, starting from a known state.\r
	SSC_CONTROL = SSC_CONTROL_RESET;\r
\r
	// RX clock comes from TX clock, RX starts when TX starts, data changes\r
	// on RX clock rising edge, sampled on falling edge\r
	SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);\r
\r
	// 8 bits per transfer, no loopback, MSB first, 1 transfer per sync\r
	// pulse, no output sync, start on positive-going edge of sync\r
	SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(8) |\r
		SSC_FRAME_MODE_MSB_FIRST | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);\r
\r
	// clock comes from TK pin, no clock output, outputs change on falling\r
	// edge of TK, start on rising edge of TF\r
	SSC_TRANSMIT_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(2) |\r
		SSC_CLOCK_MODE_START(5);\r
\r
	// tx framing is the same as the rx framing\r
	SSC_TRANSMIT_FRAME_MODE = SSC_RECEIVE_FRAME_MODE;\r
\r
	SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;\r
}\r
\r
//-----------------------------------------------------------------------------\r
// Set up DMA to receive samples from the FPGA. We will use the PDC, with\r
// a single buffer as a circular buffer (so that we just chain back to\r
// ourselves, not to another buffer). The stuff to manipulate those buffers\r
// is in apps.h, because it should be inlined, for speed.\r
//-----------------------------------------------------------------------------\r
void FpgaSetupSscDma(BYTE *buf, int len)\r
{\r
	PDC_RX_POINTER(SSC_BASE) = (DWORD)buf;\r
	PDC_RX_COUNTER(SSC_BASE) = len;\r
	PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD)buf;\r
	PDC_RX_NEXT_COUNTER(SSC_BASE) = len;\r
	PDC_CONTROL(SSC_BASE) = PDC_RX_ENABLE;\r
}\r
\r
static void DownloadFPGA_byte(unsigned char w)\r
{\r
#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }\r
	SEND_BIT(7);\r
	SEND_BIT(6);\r
	SEND_BIT(5);\r
	SEND_BIT(4);\r
	SEND_BIT(3);\r
	SEND_BIT(2);\r
	SEND_BIT(1);\r
	SEND_BIT(0);\r
}\r
\r
// Download the fpga image starting at FpgaImage and with length FpgaImageLen bytes\r
// If bytereversal is set: reverse the byte order in each 4-byte word\r
static void DownloadFPGA(const char *FpgaImage, int FpgaImageLen, int bytereversal)\r
{\r
	int i=0;\r
\r
	PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);\r
	PIO_ENABLE = (1 << GPIO_FPGA_ON);\r
	HIGH(GPIO_FPGA_ON);		// ensure everything is powered on\r
\r
	SpinDelay(50);\r
\r
	LED_D_ON();\r
\r
	// These pins are inputs\r
    PIO_OUTPUT_DISABLE =     (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE);\r
	// PIO controls the following pins\r
    PIO_ENABLE =             (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE);\r
	// Enable pull-ups\r
	PIO_NO_PULL_UP_DISABLE = (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE);\r
\r
	// setup initial logic state\r
	HIGH(GPIO_FPGA_NPROGRAM);\r
	LOW(GPIO_FPGA_CCLK);\r
	LOW(GPIO_FPGA_DIN);\r
	// These pins are outputs\r
	PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM)	|\r
						(1 << GPIO_FPGA_CCLK)		|\r
						(1 << GPIO_FPGA_DIN);\r
\r
	// enter FPGA configuration mode\r
	LOW(GPIO_FPGA_NPROGRAM);\r
	SpinDelay(50);\r
	HIGH(GPIO_FPGA_NPROGRAM);\r
\r
	i=100000;\r
	// wait for FPGA ready to accept data signal\r
	while ((i) && ( !(PIO_PIN_DATA_STATUS & (1<<GPIO_FPGA_NINIT) ) ) ) {\r
		i--;\r
	}\r
\r
	// crude error indicator, leave both red LEDs on and return\r
	if (i==0){\r
		LED_C_ON();\r
		LED_D_ON();\r
		return;\r
	}\r
\r
	if(bytereversal) {\r
		/* This is only supported for DWORD aligned images */\r
		if( ((int)FpgaImage % sizeof(DWORD)) == 0 ) {\r
			i=0;\r
			while(FpgaImageLen-->0)\r
				DownloadFPGA_byte(FpgaImage[(i++)^0x3]);\r
			/* Explanation of the magic in the above line: \r
			 * i^0x3 inverts the lower two bits of the integer i, counting backwards\r
			 * for each 4 byte increment. The generated sequence of (i++)^3 is\r
			 * 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 etc. pp. \r
			 */\r
		}\r
	} else {\r
		while(FpgaImageLen-->0)\r
			DownloadFPGA_byte(*FpgaImage++);\r
	}\r
\r
	// continue to clock FPGA until ready signal goes high\r
	i=100000;\r
	while ( (i--) && ( !(PIO_PIN_DATA_STATUS & (1<<GPIO_FPGA_DONE) ) ) ) {\r
		HIGH(GPIO_FPGA_CCLK);\r
		LOW(GPIO_FPGA_CCLK);\r
	}\r
	// crude error indicator, leave both red LEDs on and return\r
	if (i==0){\r
		LED_C_ON();\r
		LED_D_ON();\r
		return;\r
	}\r
	LED_D_OFF();\r
}\r
\r
static char *bitparse_headers_start;\r
static char *bitparse_bitstream_end;\r
static int bitparse_initialized;\r
/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence\r
 * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01\r
 * After that the format is 1 byte section type (ASCII character), 2 byte length\r
 * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes\r
 * length.
 */\r
static const char _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};\r
static int bitparse_init(void * start_address, void *end_address)\r
{\r
	bitparse_initialized = 0;\r
	\r
	if(memcmp(_bitparse_fixed_header, start_address, sizeof(_bitparse_fixed_header)) != 0) {\r
		return 0; /* Not matched */\r
	} else {\r
		bitparse_headers_start= ((char*)start_address) + sizeof(_bitparse_fixed_header);\r
		bitparse_bitstream_end= (char*)end_address;\r
		bitparse_initialized = 1;\r
		return 1;\r
	}\r
}\r
\r
int bitparse_find_section(char section_name, char **section_start, unsigned int *section_length)\r
{\r
	char *pos = bitparse_headers_start;\r
	int result = 0;\r
\r
	if(!bitparse_initialized) return 0;\r
\r
	while(pos < bitparse_bitstream_end) {\r
		char current_name = *pos++;\r
		unsigned int current_length = 0;\r
		if(current_name < 'a' || current_name > 'e') {\r
			/* Strange section name, abort */\r
			break;\r
		}\r
		current_length = 0;\r
		switch(current_name) {\r
		case 'e':\r
			/* Four byte length field */\r
			current_length += (*pos++) << 24;\r
			current_length += (*pos++) << 16;\r
		default: /* Fall through, two byte length field */\r
			current_length += (*pos++) << 8;\r
			current_length += (*pos++) << 0;\r
		}\r
		\r
		if(current_name != 'e' && current_length > 255) {\r
			/* Maybe a parse error */\r
			break;\r
		}\r
		\r
		if(current_name == section_name) {\r
			/* Found it */\r
			*section_start = pos;\r
			*section_length = current_length;\r
			result = 1;\r
			break;\r
		}\r
		\r
		pos += current_length; /* Skip section */\r
	}\r
	\r
	return result;\r
}\r
\r
//-----------------------------------------------------------------------------\r
// Find out which FPGA image format is stored in flash, then call DownloadFPGA\r
// with the right parameters to download the image\r
//-----------------------------------------------------------------------------\r
extern char _binary_fpga_bit_start, _binary_fpga_bit_end;\r
void FpgaDownloadAndGo(void)\r
{\r
	/* Check for the new flash image format: Should have the .bit file at &_binary_fpga_bit_start
	 */\r
	if(bitparse_init(&_binary_fpga_bit_start, &_binary_fpga_bit_end)) {\r
		/* Successfully initialized the .bit parser. Find the 'e' section and\r
		 * send its contents to the FPGA.
		 */\r
		char *bitstream_start;\r
		unsigned int bitstream_length;\r
		if(bitparse_find_section('e', &bitstream_start, &bitstream_length)) {\r
			DownloadFPGA(bitstream_start, bitstream_length, 0);\r
			\r
			return; /* All done */\r
		}\r
	}\r
	\r
	/* Fallback for the old flash image format: Check for the magic marker 0xFFFFFFFF\r
	 * 0xAA995566 at address 0x102000. This is raw bitstream with a size of 336,768 bits \r
	 * = 10,524 DWORDs, stored as DWORDS e.g. little-endian in memory, but each DWORD\r
	 * is still to be transmitted in MSBit first order. Set the invert flag to indicate\r
	 * that the DownloadFPGA function should invert every 4 byte sequence when doing\r
	 * the bytewise download.
	 */\r
	if( *(DWORD*)0x102000 == 0xFFFFFFFF && *(DWORD*)0x102004 == 0xAA995566 )\r
		DownloadFPGA((char*)0x102000, 10524*4, 1);\r
}\r
\r
void FpgaGatherVersion(char *dst, int len)\r
{\r
	char *fpga_info; \r
	unsigned int fpga_info_len;\r
	dst[0] = 0;\r
	if(!bitparse_find_section('e', &fpga_info, &fpga_info_len)) {\r
		strncat(dst, "FPGA image: legacy image without version information", len-1);\r
	} else {\r
		strncat(dst, "FPGA image built", len-1);\r
		/* USB packets only have 48 bytes data payload, so be terse */\r
#if 0\r
		if(bitparse_find_section('a', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r
			strncat(dst, " from ", len-1);\r
			strncat(dst, fpga_info, len-1);\r
		}\r
		if(bitparse_find_section('b', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r
			strncat(dst, " for ", len-1);\r
			strncat(dst, fpga_info, len-1);\r
		}\r
#endif\r
		if(bitparse_find_section('c', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r
			strncat(dst, " on ", len-1);\r
			strncat(dst, fpga_info, len-1);\r
		}\r
		if(bitparse_find_section('d', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r
			strncat(dst, " at ", len-1);\r
			strncat(dst, fpga_info, len-1);\r
		}\r
	}\r
}\r
\r
//-----------------------------------------------------------------------------\r
// Send a 16 bit command/data pair to the FPGA.\r
// The bit format is:  C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0\r
// where C is the 4 bit command and D is the 12 bit data\r
//-----------------------------------------------------------------------------\r
void FpgaSendCommand(WORD cmd, WORD v)\r
{\r
	SetupSpi(SPI_FPGA_MODE);\r
	while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0);		// wait for the transfer to complete\r
	SPI_TX_DATA = SPI_CONTROL_LAST_TRANSFER | cmd | v;		// send the data\r
}\r
//-----------------------------------------------------------------------------\r
// Write the FPGA setup word (that determines what mode the logic is in, read\r
// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to\r
// avoid changing this function's occurence everywhere in the source code.\r
//-----------------------------------------------------------------------------\r
void FpgaWriteConfWord(BYTE v)\r
{\r
	FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);\r
}\r
\r
//-----------------------------------------------------------------------------\r
// Set up the CMOS switches that mux the ADC: four switches, independently\r
// closable, but should only close one at a time. Not an FPGA thing, but\r
// the samples from the ADC always flow through the FPGA.\r
//-----------------------------------------------------------------------------\r
void SetAdcMuxFor(int whichGpio)\r
{\r
	PIO_OUTPUT_ENABLE = (1 << GPIO_MUXSEL_HIPKD) |\r
						(1 << GPIO_MUXSEL_LOPKD) |\r
						(1 << GPIO_MUXSEL_LORAW) |\r
						(1 << GPIO_MUXSEL_HIRAW);\r
\r
	PIO_ENABLE		=	(1 << GPIO_MUXSEL_HIPKD) |\r
						(1 << GPIO_MUXSEL_LOPKD) |\r
						(1 << GPIO_MUXSEL_LORAW) |\r
						(1 << GPIO_MUXSEL_HIRAW);\r
\r
	LOW(GPIO_MUXSEL_HIPKD);\r
	LOW(GPIO_MUXSEL_HIRAW);\r
	LOW(GPIO_MUXSEL_LORAW);\r
	LOW(GPIO_MUXSEL_LOPKD);\r
\r
	HIGH(whichGpio);\r
}\r
Commit	Line	Data
6658905f	1	//-----------------------------------------------------------------------------\r
	2	// Routines to load the FPGA image, and then to configure the FPGA's major\r
	3	// mode once it is configured.\r
	4	//\r
	5	// Jonathan Westhues, April 2006\r
	6	//-----------------------------------------------------------------------------\r
	7	#include <proxmark3.h>\r
	8	#include "apps.h"\r
	9	\r
	10	//-----------------------------------------------------------------------------\r
	11	// Set up the Serial Peripheral Interface as master\r
	12	// Used to write the FPGA config word\r
	13	// May also be used to write to other SPI attached devices like an LCD\r
	14	//-----------------------------------------------------------------------------\r
	15	void SetupSpi(int mode)\r
	16	{\r
	17	// PA10 -> SPI_NCS2 chip select (LCD)\r
	18	// PA11 -> SPI_NCS0 chip select (FPGA)\r
	19	// PA12 -> SPI_MISO Master-In Slave-Out\r
	20	// PA13 -> SPI_MOSI Master-Out Slave-In\r
	21	// PA14 -> SPI_SPCK Serial Clock\r
	22	\r
	23	// Disable PIO control of the following pins, allows use by the SPI peripheral\r
	24	PIO_DISABLE = (1 << GPIO_NCS0) \|\r
	25	(1 << GPIO_NCS2) \|\r
	26	(1 << GPIO_MISO) \|\r
	27	(1 << GPIO_MOSI) \|\r
	28	(1 << GPIO_SPCK);\r
	29	\r
	30	PIO_PERIPHERAL_A_SEL = (1 << GPIO_NCS0) \|\r
	31	(1 << GPIO_MISO) \|\r
	32	(1 << GPIO_MOSI) \|\r
	33	(1 << GPIO_SPCK);\r
	34	\r
	35	PIO_PERIPHERAL_B_SEL = (1 << GPIO_NCS2);\r
	36	\r
	37	//enable the SPI Peripheral clock\r
	38	PMC_PERIPHERAL_CLK_ENABLE = (1<<PERIPH_SPI);\r
	39	// Enable SPI\r
	40	SPI_CONTROL = SPI_CONTROL_ENABLE;\r
	41	\r
	42	switch (mode) {\r
	43	case SPI_FPGA_MODE:\r
	44	SPI_MODE =\r
	45	( 0 << 24) \| // Delay between chip selects (take default: 6 MCK periods)\r
	46	(14 << 16) \| // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)\r
	47	( 0 << 7) \| // Local Loopback Disabled\r
	48	( 1 << 4) \| // Mode Fault Detection disabled\r
	49	( 0 << 2) \| // Chip selects connected directly to peripheral\r
	50	( 0 << 1) \| // Fixed Peripheral Select\r
	51	( 1 << 0); // Master Mode\r
	52	SPI_FOR_CHIPSEL_0 =\r
	53	( 1 << 24) \| // Delay between Consecutive Transfers (32 MCK periods)\r
	54	( 1 << 16) \| // Delay Before SPCK (1 MCK period)\r
	55	( 6 << 8) \| // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
30f2a7d3	56	( 8 << 4) \| // Bits per Transfer (16 bits)\r
6658905f	57	( 0 << 3) \| // Chip Select inactive after transfer\r
	58	( 1 << 1) \| // Clock Phase data captured on leading edge, changes on following edge\r
	59	( 0 << 0); // Clock Polarity inactive state is logic 0\r
	60	break;\r
	61	case SPI_LCD_MODE:\r
	62	SPI_MODE =\r
	63	( 0 << 24) \| // Delay between chip selects (take default: 6 MCK periods)\r
	64	(11 << 16) \| // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)\r
	65	( 0 << 7) \| // Local Loopback Disabled\r
	66	( 1 << 4) \| // Mode Fault Detection disabled\r
	67	( 0 << 2) \| // Chip selects connected directly to peripheral\r
	68	( 0 << 1) \| // Fixed Peripheral Select\r
	69	( 1 << 0); // Master Mode\r
	70	SPI_FOR_CHIPSEL_2 =\r
	71	( 1 << 24) \| // Delay between Consecutive Transfers (32 MCK periods)\r
	72	( 1 << 16) \| // Delay Before SPCK (1 MCK period)\r
	73	( 6 << 8) \| // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
	74	( 1 << 4) \| // Bits per Transfer (9 bits)\r
	75	( 0 << 3) \| // Chip Select inactive after transfer\r
	76	( 1 << 1) \| // Clock Phase data captured on leading edge, changes on following edge\r
	77	( 0 << 0); // Clock Polarity inactive state is logic 0\r
	78	break;\r
	79	default: // Disable SPI\r
	80	SPI_CONTROL = SPI_CONTROL_DISABLE;\r
	81	break;\r
	82	}\r
	83	}\r
	84	\r
	85	//-----------------------------------------------------------------------------\r
	86	// Set up the synchronous serial port, with the one set of options that we\r
	87	// always use when we are talking to the FPGA. Both RX and TX are enabled.\r
	88	//-----------------------------------------------------------------------------\r
	89	void FpgaSetupSsc(void)\r
	90	{\r
	91	// First configure the GPIOs, and get ourselves a clock.\r
	92	PIO_PERIPHERAL_A_SEL = (1 << GPIO_SSC_FRAME) \|\r
	93	(1 << GPIO_SSC_DIN) \|\r
	94	(1 << GPIO_SSC_DOUT) \|\r
	95	(1 << GPIO_SSC_CLK);\r
	96	PIO_DISABLE = (1 << GPIO_SSC_DOUT);\r
	97	\r
	98	PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_SSC);\r
	99	\r
	100	// Now set up the SSC proper, starting from a known state.\r
	101	SSC_CONTROL = SSC_CONTROL_RESET;\r
	102	\r
	103	// RX clock comes from TX clock, RX starts when TX starts, data changes\r
	104	// on RX clock rising edge, sampled on falling edge\r
	105	SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(1) \| SSC_CLOCK_MODE_START(1);\r
	106	\r
	107	// 8 bits per transfer, no loopback, MSB first, 1 transfer per sync\r
	108	// pulse, no output sync, start on positive-going edge of sync\r
	109	SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(8) \|\r
	110	SSC_FRAME_MODE_MSB_FIRST \| SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);\r
	111	\r
	112	// clock comes from TK pin, no clock output, outputs change on falling\r
	113	// edge of TK, start on rising edge of TF\r
	114	SSC_TRANSMIT_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(2) \|\r
	115	SSC_CLOCK_MODE_START(5);\r
	116	\r
	117	// tx framing is the same as the rx framing\r
	118	SSC_TRANSMIT_FRAME_MODE = SSC_RECEIVE_FRAME_MODE;\r
	119	\r
	120	SSC_CONTROL = SSC_CONTROL_RX_ENABLE \| SSC_CONTROL_TX_ENABLE;\r
121	}\r
122	\r
123	//-----------------------------------------------------------------------------\r
124	// Set up DMA to receive samples from the FPGA. We will use the PDC, with\r
125	// a single buffer as a circular buffer (so that we just chain back to\r
126	// ourselves, not to another buffer). The stuff to manipulate those buffers\r
127	// is in apps.h, because it should be inlined, for speed.\r
128	//-----------------------------------------------------------------------------\r
129	void FpgaSetupSscDma(BYTE *buf, int len)\r
130	{\r
131	PDC_RX_POINTER(SSC_BASE) = (DWORD)buf;\r
132	PDC_RX_COUNTER(SSC_BASE) = len;\r
133	PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD)buf;\r
134	PDC_RX_NEXT_COUNTER(SSC_BASE) = len;\r
135	PDC_CONTROL(SSC_BASE) = PDC_RX_ENABLE;\r
136	}\r
137	\r
bb031817	138	static void DownloadFPGA_byte(unsigned char w)\r
	139	{\r
	140	#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }\r
	141	SEND_BIT(7);\r
	142	SEND_BIT(6);\r
	143	SEND_BIT(5);\r
	144	SEND_BIT(4);\r
	145	SEND_BIT(3);\r
	146	SEND_BIT(2);\r
	147	SEND_BIT(1);\r
	148	SEND_BIT(0);\r
	149	}\r
	150	\r
	151	// Download the fpga image starting at FpgaImage and with length FpgaImageLen bytes\r
e73e7172	152	// If bytereversal is set: reverse the byte order in each 4-byte word\r
bb031817	153	static void DownloadFPGA(const char *FpgaImage, int FpgaImageLen, int bytereversal)\r
6658905f	154	{\r
d3ae0de7	155	int i=0;\r
6658905f	156	\r
	157	PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);\r
	158	PIO_ENABLE = (1 << GPIO_FPGA_ON);\r
d3ae0de7	159	HIGH(GPIO_FPGA_ON); // ensure everything is powered on\r
6658905f	160	\r
	161	SpinDelay(50);\r
	162	\r
	163	LED_D_ON();\r
	164	\r
d3ae0de7	165	// These pins are inputs\r
	166	PIO_OUTPUT_DISABLE = (1 << GPIO_FPGA_NINIT) \| (1 << GPIO_FPGA_DONE);\r
	167	// PIO controls the following pins\r
	168	PIO_ENABLE = (1 << GPIO_FPGA_NINIT) \| (1 << GPIO_FPGA_DONE);\r
	169	// Enable pull-ups\r
	170	PIO_NO_PULL_UP_DISABLE = (1 << GPIO_FPGA_NINIT) \| (1 << GPIO_FPGA_DONE);\r
	171	\r
	172	// setup initial logic state\r
6658905f	173	HIGH(GPIO_FPGA_NPROGRAM);\r
	174	LOW(GPIO_FPGA_CCLK);\r
	175	LOW(GPIO_FPGA_DIN);\r
d3ae0de7	176	// These pins are outputs\r
6658905f	177	PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM) \|\r
	178	(1 << GPIO_FPGA_CCLK) \|\r
	179	(1 << GPIO_FPGA_DIN);\r
6658905f	180	\r
d3ae0de7	181	// enter FPGA configuration mode\r
6658905f	182	LOW(GPIO_FPGA_NPROGRAM);\r
	183	SpinDelay(50);\r
	184	HIGH(GPIO_FPGA_NPROGRAM);\r
	185	\r
d3ae0de7	186	i=100000;\r
	187	// wait for FPGA ready to accept data signal\r
	188	while ((i) && ( !(PIO_PIN_DATA_STATUS & (1<<GPIO_FPGA_NINIT) ) ) ) {\r
	189	i--;\r
	190	}\r
	191	\r
	192	// crude error indicator, leave both red LEDs on and return\r
	193	if (i==0){\r
	194	LED_C_ON();\r
	195	LED_D_ON();\r
	196	return;\r
	197	}\r
	198	\r
bb031817	199	if(bytereversal) {\r
	200	/* This is only supported for DWORD aligned images */\r
	201	if( ((int)FpgaImage % sizeof(DWORD)) == 0 ) {\r
	202	i=0;\r
	203	while(FpgaImageLen-->0)\r
	204	DownloadFPGA_byte(FpgaImage[(i++)^0x3]);\r
	205	/* Explanation of the magic in the above line: \r
	206	* i^0x3 inverts the lower two bits of the integer i, counting backwards\r
	207	* for each 4 byte increment. The generated sequence of (i++)^3 is\r
d3ae0de7	208	* 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 etc. pp. \r
bb031817	209	*/\r
6658905f	210	}\r
bb031817	211	} else {\r
	212	while(FpgaImageLen-->0)\r
	213	DownloadFPGA_byte(*FpgaImage++);\r
6658905f	214	}\r
6658905f	215	\r
d3ae0de7	216	// continue to clock FPGA until ready signal goes high\r
	217	i=100000;\r
	218	while ( (i--) && ( !(PIO_PIN_DATA_STATUS & (1<<GPIO_FPGA_DONE) ) ) ) {\r
	219	HIGH(GPIO_FPGA_CCLK);\r
	220	LOW(GPIO_FPGA_CCLK);\r
	221	}\r
	222	// crude error indicator, leave both red LEDs on and return\r
	223	if (i==0){\r
	224	LED_C_ON();\r
	225	LED_D_ON();\r
	226	return;\r
	227	}\r
6658905f	228	LED_D_OFF();\r
	229	}\r
	230	\r
e73e7172	231	static char *bitparse_headers_start;\r
	232	static char *bitparse_bitstream_end;\r
	233	static int bitparse_initialized;\r
	234	/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence\r
	235	* 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01\r
	236	* After that the format is 1 byte section type (ASCII character), 2 byte length\r
	237	* (big endian), <length> bytes content. Except for section 'e' which has 4 bytes\r
	238	* length.
	239	*/\r
	240	static const char _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};\r
	241	static int bitparse_init(void * start_address, void *end_address)\r
	242	{\r
	243	bitparse_initialized = 0;\r
	244	\r
	245	if(memcmp(_bitparse_fixed_header, start_address, sizeof(_bitparse_fixed_header)) != 0) {\r
	246	return 0; /* Not matched */\r
	247	} else {\r
	248	bitparse_headers_start= ((char*)start_address) + sizeof(_bitparse_fixed_header);\r
	249	bitparse_bitstream_end= (char*)end_address;\r
	250	bitparse_initialized = 1;\r
	251	return 1;\r
	252	}\r
	253	}\r
	254	\r
9dbe0941	255	int bitparse_find_section(char section_name, char *section_start, unsigned int section_length)\r
e73e7172	256	{\r
	257	char *pos = bitparse_headers_start;\r
	258	int result = 0;\r
	259	\r
	260	if(!bitparse_initialized) return 0;\r
	261	\r
	262	while(pos < bitparse_bitstream_end) {\r
	263	char current_name = *pos++;\r
	264	unsigned int current_length = 0;\r
	265	if(current_name < 'a' \|\| current_name > 'e') {\r
	266	/* Strange section name, abort */\r
	267	break;\r
	268	}\r
	269	current_length = 0;\r
	270	switch(current_name) {\r
	271	case 'e':\r
	272	/* Four byte length field */\r
	273	current_length += (*pos++) << 24;\r
	274	current_length += (*pos++) << 16;\r
	275	default: /* Fall through, two byte length field */\r
	276	current_length += (*pos++) << 8;\r
	277	current_length += (*pos++) << 0;\r
	278	}\r
	279	\r
	280	if(current_name != 'e' && current_length > 255) {\r
	281	/* Maybe a parse error */\r
	282	break;\r
	283	}\r
	284	\r
	285	if(current_name == section_name) {\r
	286	/* Found it */\r
	287	*section_start = pos;\r
	288	*section_length = current_length;\r
	289	result = 1;\r
	290	break;\r
	291	}\r
	292	\r
	293	pos += current_length; /* Skip section */\r
	294	}\r
	295	\r
	296	return result;\r
	297	}\r
	298	\r
	299	//-----------------------------------------------------------------------------\r
	300	// Find out which FPGA image format is stored in flash, then call DownloadFPGA\r
	301	// with the right parameters to download the image\r
	302	//-----------------------------------------------------------------------------\r
	303	extern char _binary_fpga_bit_start, _binary_fpga_bit_end;\r
	304	void FpgaDownloadAndGo(void)\r
	305	{\r
	306	/* Check for the new flash image format: Should have the .bit file at &_binary_fpga_bit_start
	307	*/\r
	308	if(bitparse_init(&_binary_fpga_bit_start, &_binary_fpga_bit_end)) {\r
	309	/* Successfully initialized the .bit parser. Find the 'e' section and\r
	310	* send its contents to the FPGA.
	311	*/\r
9dbe0941	312	char *bitstream_start;\r
e73e7172	313	unsigned int bitstream_length;\r
e73e7172	314	if(bitparse_find_section('e', &bitstream_start, &bitstream_length)) {\r
bb031817	315	DownloadFPGA(bitstream_start, bitstream_length, 0);\r
e73e7172	316	\r
	317	return; /* All done */\r
	318	}\r
	319	}\r
	320	\r
	321	/* Fallback for the old flash image format: Check for the magic marker 0xFFFFFFFF\r
e3ae0257	322	* 0xAA995566 at address 0x102000. This is raw bitstream with a size of 336,768 bits \r
e73e7172	323	* = 10,524 DWORDs, stored as DWORDS e.g. little-endian in memory, but each DWORD\r
	324	* is still to be transmitted in MSBit first order. Set the invert flag to indicate\r
	325	* that the DownloadFPGA function should invert every 4 byte sequence when doing\r
	326	* the bytewise download.
	327	*/\r
e3ae0257	328	if( (DWORD)0x102000 == 0xFFFFFFFF && (DWORD)0x102004 == 0xAA995566 )\r
bb031817	329	DownloadFPGA((char)0x102000, 105244, 1);\r
e73e7172	330	}\r
e73e7172	331	\r
ba8a80b3	332	void FpgaGatherVersion(char *dst, int len)\r
	333	{\r
	334	char *fpga_info; \r
	335	unsigned int fpga_info_len;\r
	336	dst[0] = 0;\r
9dbe0941	337	if(!bitparse_find_section('e', &fpga_info, &fpga_info_len)) {\r
ba8a80b3	338	strncat(dst, "FPGA image: legacy image without version information", len-1);\r
	339	} else {\r
	340	strncat(dst, "FPGA image built", len-1);\r
	341	/* USB packets only have 48 bytes data payload, so be terse */\r
	342	#if 0\r
9dbe0941	343	if(bitparse_find_section('a', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r
ba8a80b3	344	strncat(dst, " from ", len-1);\r
	345	strncat(dst, fpga_info, len-1);\r
	346	}\r
9dbe0941	347	if(bitparse_find_section('b', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r
ba8a80b3	348	strncat(dst, " for ", len-1);\r
	349	strncat(dst, fpga_info, len-1);\r
	350	}\r
	351	#endif\r
9dbe0941	352	if(bitparse_find_section('c', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r
ba8a80b3	353	strncat(dst, " on ", len-1);\r
	354	strncat(dst, fpga_info, len-1);\r
	355	}\r
9dbe0941	356	if(bitparse_find_section('d', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r
ba8a80b3	357	strncat(dst, " at ", len-1);\r
	358	strncat(dst, fpga_info, len-1);\r
	359	}\r
	360	}\r
	361	}\r
	362	\r
30f2a7d3	363	//-----------------------------------------------------------------------------\r
	364	// Send a 16 bit command/data pair to the FPGA.\r
	365	// The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0\r
	366	// where C is the 4 bit command and D is the 12 bit data\r
	367	//-----------------------------------------------------------------------------\r
	368	void FpgaSendCommand(WORD cmd, WORD v)\r
	369	{\r
	370	SetupSpi(SPI_FPGA_MODE);\r
	371	while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0); // wait for the transfer to complete\r
	372	SPI_TX_DATA = SPI_CONTROL_LAST_TRANSFER \| cmd \| v; // send the data\r
	373	}\r
6658905f	374	//-----------------------------------------------------------------------------\r
6658905f	375	// Write the FPGA setup word (that determines what mode the logic is in, read\r
30f2a7d3	376	// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to\r
30f2a7d3	377	// avoid changing this function's occurence everywhere in the source code.\r
6658905f	378	//-----------------------------------------------------------------------------\r
	379	void FpgaWriteConfWord(BYTE v)\r
	380	{\r
30f2a7d3	381	FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);\r
6658905f	382	}\r
	383	\r
	384	//-----------------------------------------------------------------------------\r
	385	// Set up the CMOS switches that mux the ADC: four switches, independently\r
	386	// closable, but should only close one at a time. Not an FPGA thing, but\r
	387	// the samples from the ADC always flow through the FPGA.\r
	388	//-----------------------------------------------------------------------------\r
	389	void SetAdcMuxFor(int whichGpio)\r
	390	{\r
	391	PIO_OUTPUT_ENABLE = (1 << GPIO_MUXSEL_HIPKD) \|\r
	392	(1 << GPIO_MUXSEL_LOPKD) \|\r
	393	(1 << GPIO_MUXSEL_LORAW) \|\r
	394	(1 << GPIO_MUXSEL_HIRAW);\r
	395	\r
	396	PIO_ENABLE = (1 << GPIO_MUXSEL_HIPKD) \|\r
	397	(1 << GPIO_MUXSEL_LOPKD) \|\r
	398	(1 << GPIO_MUXSEL_LORAW) \|\r
	399	(1 << GPIO_MUXSEL_HIRAW);\r
	400	\r
	401	LOW(GPIO_MUXSEL_HIPKD);\r
	402	LOW(GPIO_MUXSEL_HIRAW);\r
	403	LOW(GPIO_MUXSEL_LORAW);\r
	404	LOW(GPIO_MUXSEL_LOPKD);\r
	405	\r
	406	HIGH(whichGpio);\r
	407	}\r