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Merge branch 'master' of https://github.com/Proxmark/proxmark3
[proxmark3-svn] / armsrc / iclass.c
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cee5a30d 1//-----------------------------------------------------------------------------
2// Gerhard de Koning Gans - May 2008
3// Hagen Fritsch - June 2010
4// Gerhard de Koning Gans - May 2011
1e262141 5// Gerhard de Koning Gans - June 2012 - Added iClass card and reader emulation
cee5a30d 6//
7// This code is licensed to you under the terms of the GNU GPL, version 2 or,
8// at your option, any later version. See the LICENSE.txt file for the text of
9// the license.
10//-----------------------------------------------------------------------------
11// Routines to support iClass.
12//-----------------------------------------------------------------------------
13// Based on ISO14443a implementation. Still in experimental phase.
14// Contribution made during a security research at Radboud University Nijmegen
15//
16// Please feel free to contribute and extend iClass support!!
17//-----------------------------------------------------------------------------
18//
cee5a30d 19// FIX:
20// ====
21// We still have sometimes a demodulation error when snooping iClass communication.
22// The resulting trace of a read-block-03 command may look something like this:
23//
24// + 22279: : 0c 03 e8 01
25//
26// ...with an incorrect answer...
27//
28// + 85: 0: TAG ff! ff! ff! ff! ff! ff! ff! ff! bb 33 bb 00 01! 0e! 04! bb !crc
29//
30// We still left the error signalling bytes in the traces like 0xbb
31//
32// A correct trace should look like this:
33//
34// + 21112: : 0c 03 e8 01
35// + 85: 0: TAG ff ff ff ff ff ff ff ff ea f5
36//
37//-----------------------------------------------------------------------------
38
f38a1528 39#include "../include/proxmark3.h"
cee5a30d 40#include "apps.h"
41#include "util.h"
42#include "string.h"
7e67e42f 43#include "common.h"
f38a1528 44#include "cmd.h"
1e262141 45// Needed for CRC in emulation mode;
46// same construction as in ISO 14443;
47// different initial value (CRC_ICLASS)
f38a1528 48#include "../common/iso14443crc.h"
49#include "../common/iso15693tools.h"
10403a6a 50//#include "iso15693tools.h"
f38a1528 51
cee5a30d 52
1e262141 53static int timeout = 4096;
cee5a30d 54
cee5a30d 55
1e262141 56static int SendIClassAnswer(uint8_t *resp, int respLen, int delay);
cee5a30d 57
58//-----------------------------------------------------------------------------
59// The software UART that receives commands from the reader, and its state
60// variables.
61//-----------------------------------------------------------------------------
62static struct {
63 enum {
64 STATE_UNSYNCD,
65 STATE_START_OF_COMMUNICATION,
66 STATE_RECEIVING
67 } state;
68 uint16_t shiftReg;
69 int bitCnt;
70 int byteCnt;
71 int byteCntMax;
72 int posCnt;
73 int nOutOfCnt;
74 int OutOfCnt;
75 int syncBit;
1e262141 76 int samples;
cee5a30d 77 int highCnt;
78 int swapper;
79 int counter;
80 int bitBuffer;
81 int dropPosition;
a501c82b 82 uint8_t *output;
cee5a30d 83} Uart;
84
1e262141 85static RAMFUNC int OutOfNDecoding(int bit)
cee5a30d 86{
9f693930 87 //int error = 0;
cee5a30d 88 int bitright;
89
90 if(!Uart.bitBuffer) {
91 Uart.bitBuffer = bit ^ 0xFF0;
92 return FALSE;
93 }
94 else {
95 Uart.bitBuffer <<= 4;
96 Uart.bitBuffer ^= bit;
97 }
98
99 /*if(Uart.swapper) {
100 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
101 Uart.byteCnt++;
102 Uart.swapper = 0;
103 if(Uart.byteCnt > 15) { return TRUE; }
104 }
105 else {
106 Uart.swapper = 1;
107 }*/
108
109 if(Uart.state != STATE_UNSYNCD) {
110 Uart.posCnt++;
111
112 if((Uart.bitBuffer & Uart.syncBit) ^ Uart.syncBit) {
113 bit = 0x00;
114 }
115 else {
116 bit = 0x01;
117 }
118 if(((Uart.bitBuffer << 1) & Uart.syncBit) ^ Uart.syncBit) {
119 bitright = 0x00;
120 }
121 else {
122 bitright = 0x01;
123 }
124 if(bit != bitright) { bit = bitright; }
125
126
127 // So, now we only have to deal with *bit*, lets see...
128 if(Uart.posCnt == 1) {
129 // measurement first half bitperiod
130 if(!bit) {
131 // Drop in first half means that we are either seeing
132 // an SOF or an EOF.
133
134 if(Uart.nOutOfCnt == 1) {
135 // End of Communication
136 Uart.state = STATE_UNSYNCD;
137 Uart.highCnt = 0;
138 if(Uart.byteCnt == 0) {
139 // Its not straightforward to show single EOFs
140 // So just leave it and do not return TRUE
a501c82b 141 Uart.output[0] = 0xf0;
cee5a30d 142 Uart.byteCnt++;
cee5a30d 143 }
144 else {
145 return TRUE;
146 }
147 }
148 else if(Uart.state != STATE_START_OF_COMMUNICATION) {
149 // When not part of SOF or EOF, it is an error
150 Uart.state = STATE_UNSYNCD;
151 Uart.highCnt = 0;
9f693930 152 //error = 4;
cee5a30d 153 }
154 }
155 }
156 else {
157 // measurement second half bitperiod
158 // Count the bitslot we are in... (ISO 15693)
159 Uart.nOutOfCnt++;
160
161 if(!bit) {
162 if(Uart.dropPosition) {
163 if(Uart.state == STATE_START_OF_COMMUNICATION) {
9f693930 164 //error = 1;
cee5a30d 165 }
166 else {
9f693930 167 //error = 7;
cee5a30d 168 }
169 // It is an error if we already have seen a drop in current frame
170 Uart.state = STATE_UNSYNCD;
171 Uart.highCnt = 0;
172 }
173 else {
174 Uart.dropPosition = Uart.nOutOfCnt;
175 }
176 }
177
178 Uart.posCnt = 0;
179
180
181 if(Uart.nOutOfCnt == Uart.OutOfCnt && Uart.OutOfCnt == 4) {
182 Uart.nOutOfCnt = 0;
183
184 if(Uart.state == STATE_START_OF_COMMUNICATION) {
185 if(Uart.dropPosition == 4) {
186 Uart.state = STATE_RECEIVING;
187 Uart.OutOfCnt = 256;
188 }
189 else if(Uart.dropPosition == 3) {
190 Uart.state = STATE_RECEIVING;
191 Uart.OutOfCnt = 4;
192 //Uart.output[Uart.byteCnt] = 0xdd;
193 //Uart.byteCnt++;
194 }
195 else {
196 Uart.state = STATE_UNSYNCD;
197 Uart.highCnt = 0;
198 }
199 Uart.dropPosition = 0;
200 }
201 else {
202 // RECEIVING DATA
203 // 1 out of 4
204 if(!Uart.dropPosition) {
205 Uart.state = STATE_UNSYNCD;
206 Uart.highCnt = 0;
9f693930 207 //error = 9;
cee5a30d 208 }
209 else {
210 Uart.shiftReg >>= 2;
211
212 // Swap bit order
213 Uart.dropPosition--;
214 //if(Uart.dropPosition == 1) { Uart.dropPosition = 2; }
215 //else if(Uart.dropPosition == 2) { Uart.dropPosition = 1; }
216
217 Uart.shiftReg ^= ((Uart.dropPosition & 0x03) << 6);
218 Uart.bitCnt += 2;
219 Uart.dropPosition = 0;
220
221 if(Uart.bitCnt == 8) {
222 Uart.output[Uart.byteCnt] = (Uart.shiftReg & 0xff);
223 Uart.byteCnt++;
cee5a30d 224 Uart.bitCnt = 0;
225 Uart.shiftReg = 0;
226 }
227 }
228 }
229 }
230 else if(Uart.nOutOfCnt == Uart.OutOfCnt) {
231 // RECEIVING DATA
232 // 1 out of 256
233 if(!Uart.dropPosition) {
234 Uart.state = STATE_UNSYNCD;
235 Uart.highCnt = 0;
9f693930 236 //error = 3;
cee5a30d 237 }
238 else {
239 Uart.dropPosition--;
240 Uart.output[Uart.byteCnt] = (Uart.dropPosition & 0xff);
241 Uart.byteCnt++;
cee5a30d 242 Uart.bitCnt = 0;
243 Uart.shiftReg = 0;
244 Uart.nOutOfCnt = 0;
245 Uart.dropPosition = 0;
246 }
247 }
248
249 /*if(error) {
250 Uart.output[Uart.byteCnt] = 0xAA;
251 Uart.byteCnt++;
252 Uart.output[Uart.byteCnt] = error & 0xFF;
253 Uart.byteCnt++;
254 Uart.output[Uart.byteCnt] = 0xAA;
255 Uart.byteCnt++;
256 Uart.output[Uart.byteCnt] = (Uart.bitBuffer >> 8) & 0xFF;
257 Uart.byteCnt++;
258 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
259 Uart.byteCnt++;
260 Uart.output[Uart.byteCnt] = (Uart.syncBit >> 3) & 0xFF;
261 Uart.byteCnt++;
262 Uart.output[Uart.byteCnt] = 0xAA;
263 Uart.byteCnt++;
264 return TRUE;
265 }*/
266 }
267
268 }
269 else {
270 bit = Uart.bitBuffer & 0xf0;
271 bit >>= 4;
272 bit ^= 0x0F; // drops become 1s ;-)
273 if(bit) {
274 // should have been high or at least (4 * 128) / fc
275 // according to ISO this should be at least (9 * 128 + 20) / fc
276 if(Uart.highCnt == 8) {
277 // we went low, so this could be start of communication
278 // it turns out to be safer to choose a less significant
279 // syncbit... so we check whether the neighbour also represents the drop
280 Uart.posCnt = 1; // apparently we are busy with our first half bit period
281 Uart.syncBit = bit & 8;
282 Uart.samples = 3;
283 if(!Uart.syncBit) { Uart.syncBit = bit & 4; Uart.samples = 2; }
284 else if(bit & 4) { Uart.syncBit = bit & 4; Uart.samples = 2; bit <<= 2; }
285 if(!Uart.syncBit) { Uart.syncBit = bit & 2; Uart.samples = 1; }
286 else if(bit & 2) { Uart.syncBit = bit & 2; Uart.samples = 1; bit <<= 1; }
287 if(!Uart.syncBit) { Uart.syncBit = bit & 1; Uart.samples = 0;
288 if(Uart.syncBit && (Uart.bitBuffer & 8)) {
289 Uart.syncBit = 8;
290
291 // the first half bit period is expected in next sample
292 Uart.posCnt = 0;
293 Uart.samples = 3;
294 }
295 }
296 else if(bit & 1) { Uart.syncBit = bit & 1; Uart.samples = 0; }
297
298 Uart.syncBit <<= 4;
299 Uart.state = STATE_START_OF_COMMUNICATION;
300 Uart.bitCnt = 0;
301 Uart.byteCnt = 0;
cee5a30d 302 Uart.nOutOfCnt = 0;
303 Uart.OutOfCnt = 4; // Start at 1/4, could switch to 1/256
304 Uart.dropPosition = 0;
305 Uart.shiftReg = 0;
9f693930 306 //error = 0;
cee5a30d 307 }
308 else {
309 Uart.highCnt = 0;
310 }
311 }
312 else {
313 if(Uart.highCnt < 8) {
314 Uart.highCnt++;
315 }
316 }
317 }
318
319 return FALSE;
320}
321
322//=============================================================================
1e262141 323// Manchester
cee5a30d 324//=============================================================================
325
326static struct {
327 enum {
328 DEMOD_UNSYNCD,
329 DEMOD_START_OF_COMMUNICATION,
330 DEMOD_START_OF_COMMUNICATION2,
331 DEMOD_START_OF_COMMUNICATION3,
332 DEMOD_SOF_COMPLETE,
333 DEMOD_MANCHESTER_D,
334 DEMOD_MANCHESTER_E,
335 DEMOD_END_OF_COMMUNICATION,
336 DEMOD_END_OF_COMMUNICATION2,
337 DEMOD_MANCHESTER_F,
338 DEMOD_ERROR_WAIT
339 } state;
340 int bitCount;
341 int posCount;
342 int syncBit;
cee5a30d 343 uint16_t shiftReg;
344 int buffer;
345 int buffer2;
346 int buffer3;
347 int buff;
348 int samples;
349 int len;
350 enum {
351 SUB_NONE,
352 SUB_FIRST_HALF,
353 SUB_SECOND_HALF,
354 SUB_BOTH
355 } sub;
356 uint8_t *output;
357} Demod;
358
359static RAMFUNC int ManchesterDecoding(int v)
360{
361 int bit;
362 int modulation;
363 int error = 0;
364
365 bit = Demod.buffer;
366 Demod.buffer = Demod.buffer2;
367 Demod.buffer2 = Demod.buffer3;
368 Demod.buffer3 = v;
369
370 if(Demod.buff < 3) {
371 Demod.buff++;
372 return FALSE;
373 }
374
375 if(Demod.state==DEMOD_UNSYNCD) {
376 Demod.output[Demod.len] = 0xfa;
377 Demod.syncBit = 0;
378 //Demod.samples = 0;
379 Demod.posCount = 1; // This is the first half bit period, so after syncing handle the second part
cee5a30d 380
381 if(bit & 0x08) {
382 Demod.syncBit = 0x08;
383 }
384
385 if(bit & 0x04) {
386 if(Demod.syncBit) {
387 bit <<= 4;
388 }
389 Demod.syncBit = 0x04;
390 }
391
392 if(bit & 0x02) {
393 if(Demod.syncBit) {
394 bit <<= 2;
395 }
396 Demod.syncBit = 0x02;
397 }
398
399 if(bit & 0x01 && Demod.syncBit) {
400 Demod.syncBit = 0x01;
401 }
402
403 if(Demod.syncBit) {
404 Demod.len = 0;
405 Demod.state = DEMOD_START_OF_COMMUNICATION;
406 Demod.sub = SUB_FIRST_HALF;
407 Demod.bitCount = 0;
408 Demod.shiftReg = 0;
cee5a30d 409 Demod.samples = 0;
410 if(Demod.posCount) {
411 //if(trigger) LED_A_OFF(); // Not useful in this case...
412 switch(Demod.syncBit) {
413 case 0x08: Demod.samples = 3; break;
414 case 0x04: Demod.samples = 2; break;
415 case 0x02: Demod.samples = 1; break;
416 case 0x01: Demod.samples = 0; break;
417 }
418 // SOF must be long burst... otherwise stay unsynced!!!
419 if(!(Demod.buffer & Demod.syncBit) || !(Demod.buffer2 & Demod.syncBit)) {
420 Demod.state = DEMOD_UNSYNCD;
421 }
422 }
423 else {
424 // SOF must be long burst... otherwise stay unsynced!!!
425 if(!(Demod.buffer2 & Demod.syncBit) || !(Demod.buffer3 & Demod.syncBit)) {
426 Demod.state = DEMOD_UNSYNCD;
427 error = 0x88;
428 }
429
430 }
431 error = 0;
432
433 }
434 }
435 else {
436 modulation = bit & Demod.syncBit;
437 modulation |= ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit;
cee5a30d 438
439 Demod.samples += 4;
440
441 if(Demod.posCount==0) {
442 Demod.posCount = 1;
443 if(modulation) {
444 Demod.sub = SUB_FIRST_HALF;
445 }
446 else {
447 Demod.sub = SUB_NONE;
448 }
449 }
450 else {
451 Demod.posCount = 0;
452 /*(modulation && (Demod.sub == SUB_FIRST_HALF)) {
453 if(Demod.state!=DEMOD_ERROR_WAIT) {
454 Demod.state = DEMOD_ERROR_WAIT;
455 Demod.output[Demod.len] = 0xaa;
456 error = 0x01;
457 }
458 }*/
459 //else if(modulation) {
460 if(modulation) {
461 if(Demod.sub == SUB_FIRST_HALF) {
462 Demod.sub = SUB_BOTH;
463 }
464 else {
465 Demod.sub = SUB_SECOND_HALF;
466 }
467 }
468 else if(Demod.sub == SUB_NONE) {
469 if(Demod.state == DEMOD_SOF_COMPLETE) {
470 Demod.output[Demod.len] = 0x0f;
471 Demod.len++;
cee5a30d 472 Demod.state = DEMOD_UNSYNCD;
473// error = 0x0f;
474 return TRUE;
475 }
476 else {
477 Demod.state = DEMOD_ERROR_WAIT;
478 error = 0x33;
479 }
480 /*if(Demod.state!=DEMOD_ERROR_WAIT) {
481 Demod.state = DEMOD_ERROR_WAIT;
482 Demod.output[Demod.len] = 0xaa;
483 error = 0x01;
484 }*/
485 }
486
487 switch(Demod.state) {
488 case DEMOD_START_OF_COMMUNICATION:
489 if(Demod.sub == SUB_BOTH) {
490 //Demod.state = DEMOD_MANCHESTER_D;
491 Demod.state = DEMOD_START_OF_COMMUNICATION2;
492 Demod.posCount = 1;
493 Demod.sub = SUB_NONE;
494 }
495 else {
496 Demod.output[Demod.len] = 0xab;
497 Demod.state = DEMOD_ERROR_WAIT;
498 error = 0xd2;
499 }
500 break;
501 case DEMOD_START_OF_COMMUNICATION2:
502 if(Demod.sub == SUB_SECOND_HALF) {
503 Demod.state = DEMOD_START_OF_COMMUNICATION3;
504 }
505 else {
506 Demod.output[Demod.len] = 0xab;
507 Demod.state = DEMOD_ERROR_WAIT;
508 error = 0xd3;
509 }
510 break;
511 case DEMOD_START_OF_COMMUNICATION3:
512 if(Demod.sub == SUB_SECOND_HALF) {
513// Demod.state = DEMOD_MANCHESTER_D;
514 Demod.state = DEMOD_SOF_COMPLETE;
515 //Demod.output[Demod.len] = Demod.syncBit & 0xFF;
516 //Demod.len++;
517 }
518 else {
519 Demod.output[Demod.len] = 0xab;
520 Demod.state = DEMOD_ERROR_WAIT;
521 error = 0xd4;
522 }
523 break;
524 case DEMOD_SOF_COMPLETE:
525 case DEMOD_MANCHESTER_D:
526 case DEMOD_MANCHESTER_E:
527 // OPPOSITE FROM ISO14443 - 11110000 = 0 (1 in 14443)
528 // 00001111 = 1 (0 in 14443)
529 if(Demod.sub == SUB_SECOND_HALF) { // SUB_FIRST_HALF
530 Demod.bitCount++;
531 Demod.shiftReg = (Demod.shiftReg >> 1) ^ 0x100;
532 Demod.state = DEMOD_MANCHESTER_D;
533 }
534 else if(Demod.sub == SUB_FIRST_HALF) { // SUB_SECOND_HALF
535 Demod.bitCount++;
536 Demod.shiftReg >>= 1;
537 Demod.state = DEMOD_MANCHESTER_E;
538 }
539 else if(Demod.sub == SUB_BOTH) {
540 Demod.state = DEMOD_MANCHESTER_F;
541 }
542 else {
543 Demod.state = DEMOD_ERROR_WAIT;
544 error = 0x55;
545 }
546 break;
547
548 case DEMOD_MANCHESTER_F:
549 // Tag response does not need to be a complete byte!
550 if(Demod.len > 0 || Demod.bitCount > 0) {
551 if(Demod.bitCount > 1) { // was > 0, do not interpret last closing bit, is part of EOF
f5ed4d12 552 Demod.shiftReg >>= (9 - Demod.bitCount); // right align data
cee5a30d 553 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
554 Demod.len++;
cee5a30d 555 }
556
557 Demod.state = DEMOD_UNSYNCD;
558 return TRUE;
559 }
560 else {
561 Demod.output[Demod.len] = 0xad;
562 Demod.state = DEMOD_ERROR_WAIT;
563 error = 0x03;
564 }
565 break;
566
567 case DEMOD_ERROR_WAIT:
568 Demod.state = DEMOD_UNSYNCD;
569 break;
570
571 default:
572 Demod.output[Demod.len] = 0xdd;
573 Demod.state = DEMOD_UNSYNCD;
574 break;
575 }
576
577 /*if(Demod.bitCount>=9) {
578 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
579 Demod.len++;
580
581 Demod.parityBits <<= 1;
582 Demod.parityBits ^= ((Demod.shiftReg >> 8) & 0x01);
583
584 Demod.bitCount = 0;
585 Demod.shiftReg = 0;
586 }*/
587 if(Demod.bitCount>=8) {
588 Demod.shiftReg >>= 1;
589 Demod.output[Demod.len] = (Demod.shiftReg & 0xff);
590 Demod.len++;
cee5a30d 591 Demod.bitCount = 0;
592 Demod.shiftReg = 0;
593 }
594
595 if(error) {
596 Demod.output[Demod.len] = 0xBB;
597 Demod.len++;
598 Demod.output[Demod.len] = error & 0xFF;
599 Demod.len++;
600 Demod.output[Demod.len] = 0xBB;
601 Demod.len++;
602 Demod.output[Demod.len] = bit & 0xFF;
603 Demod.len++;
604 Demod.output[Demod.len] = Demod.buffer & 0xFF;
605 Demod.len++;
606 // Look harder ;-)
607 Demod.output[Demod.len] = Demod.buffer2 & 0xFF;
608 Demod.len++;
609 Demod.output[Demod.len] = Demod.syncBit & 0xFF;
610 Demod.len++;
611 Demod.output[Demod.len] = 0xBB;
612 Demod.len++;
613 return TRUE;
614 }
615
616 }
617
618 } // end (state != UNSYNCED)
619
620 return FALSE;
621}
622
623//=============================================================================
1e262141 624// Finally, a `sniffer' for iClass communication
cee5a30d 625// Both sides of communication!
626//=============================================================================
627
628//-----------------------------------------------------------------------------
629// Record the sequence of commands sent by the reader to the tag, with
630// triggering so that we start recording at the point that the tag is moved
631// near the reader.
632//-----------------------------------------------------------------------------
633void RAMFUNC SnoopIClass(void)
634{
17cba269 635
cee5a30d 636
637 // We won't start recording the frames that we acquire until we trigger;
638 // a good trigger condition to get started is probably when we see a
639 // response from the tag.
9f693930 640 //int triggered = FALSE; // FALSE to wait first for card
cee5a30d 641
642 // The command (reader -> tag) that we're receiving.
643 // The length of a received command will in most cases be no more than 18 bytes.
644 // So 32 should be enough!
f71f4deb 645 #define ICLASS_BUFFER_SIZE 32
646 uint8_t readerToTagCmd[ICLASS_BUFFER_SIZE];
cee5a30d 647 // The response (tag -> reader) that we're receiving.
f71f4deb 648 uint8_t tagToReaderResponse[ICLASS_BUFFER_SIZE];
6a1f2d82 649
7cc204bf 650 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
651
f71f4deb 652 // free all BigBuf memory
653 BigBuf_free();
654 // The DMA buffer, used to stream samples from the FPGA
655 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
656
3000dc4e
MHS		 657 set_tracing(TRUE);
658 clear_trace();
1e262141 659 iso14a_set_trigger(FALSE);
cee5a30d 660
cee5a30d 661 int lastRxCounter;
117d9ec2 662 uint8_t *upTo;
cee5a30d 663 int smpl;
664 int maxBehindBy = 0;
665
666 // Count of samples received so far, so that we can include timing
667 // information in the trace buffer.
668 int samples = 0;
669 rsamples = 0;
670
cee5a30d 671 // Set up the demodulator for tag -> reader responses.
17cba269 672 Demod.output = tagToReaderResponse;
cee5a30d 673 Demod.len = 0;
674 Demod.state = DEMOD_UNSYNCD;
675
676 // Setup for the DMA.
677 FpgaSetupSsc();
678 upTo = dmaBuf;
679 lastRxCounter = DMA_BUFFER_SIZE;
680 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
681
682 // And the reader -> tag commands
683 memset(&Uart, 0, sizeof(Uart));
17cba269 684 Uart.output = readerToTagCmd;
cee5a30d 685 Uart.byteCntMax = 32; // was 100 (greg)////////////////////////////////////////////////////////////////////////
686 Uart.state = STATE_UNSYNCD;
687
688 // And put the FPGA in the appropriate mode
689 // Signal field is off with the appropriate LED
690 LED_D_OFF();
691 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_SNIFFER);
692 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
693
81012e67 694 uint32_t time_0 = GetCountSspClk();
55eaed8f
MHS		 695 uint32_t time_start = 0;
696 uint32_t time_stop = 0;
81012e67 697
cee5a30d 698 int div = 0;
699 //int div2 = 0;
700 int decbyte = 0;
701 int decbyter = 0;
702
703 // And now we loop, receiving samples.
704 for(;;) {
705 LED_A_ON();
706 WDT_HIT();
707 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &
708 (DMA_BUFFER_SIZE-1);
709 if(behindBy > maxBehindBy) {
710 maxBehindBy = behindBy;
f71f4deb 711 if(behindBy > (9 * DMA_BUFFER_SIZE / 10)) {
cee5a30d 712 Dbprintf("blew circular buffer! behindBy=0x%x", behindBy);
713 goto done;
714 }
715 }
716 if(behindBy < 1) continue;
717
718 LED_A_OFF();
719 smpl = upTo[0];
720 upTo++;
721 lastRxCounter -= 1;
722 if(upTo - dmaBuf > DMA_BUFFER_SIZE) {
723 upTo -= DMA_BUFFER_SIZE;
724 lastRxCounter += DMA_BUFFER_SIZE;
725 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
726 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
727 }
728
729 //samples += 4;
730 samples += 1;
cee5a30d 731
cee5a30d 732 if(smpl & 0xF) {
733 decbyte ^= (1 << (3 - div));
734 }
cee5a30d 735
736 // FOR READER SIDE COMMUMICATION...
17cba269 737
cee5a30d 738 decbyter <<= 2;
739 decbyter ^= (smpl & 0x30);
740
741 div++;
742
743 if((div + 1) % 2 == 0) {
744 smpl = decbyter;
1e262141 745 if(OutOfNDecoding((smpl & 0xF0) >> 4)) {
cee5a30d 746 rsamples = samples - Uart.samples;
55eaed8f 747 time_stop = (GetCountSspClk()-time_0) << 4;
cee5a30d 748 LED_C_ON();
17cba269 749
81012e67 750 //if(!LogTrace(Uart.output,Uart.byteCnt, rsamples, Uart.parityBits,TRUE)) break;
17cba269 751 //if(!LogTrace(NULL, 0, Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, 0, TRUE)) break;
6a1f2d82 752 if(tracing) {
a501c82b 753 uint8_t parity[MAX_PARITY_SIZE];
754 GetParity(Uart.output, Uart.byteCnt, parity);
55eaed8f 755 LogTrace(Uart.output,Uart.byteCnt, time_start, time_stop, parity, TRUE);
81012e67
MHS		 756 }
757
17cba269
MHS		 758
759 /* And ready to receive another command. */
cee5a30d 760 Uart.state = STATE_UNSYNCD;
761 /* And also reset the demod code, which might have been */
762 /* false-triggered by the commands from the reader. */
763 Demod.state = DEMOD_UNSYNCD;
764 LED_B_OFF();
765 Uart.byteCnt = 0;
55eaed8f
MHS		 766 }else{
767 time_start = (GetCountSspClk()-time_0) << 4;
cee5a30d 768 }
769 decbyter = 0;
770 }
771
772 if(div > 3) {
773 smpl = decbyte;
774 if(ManchesterDecoding(smpl & 0x0F)) {
55eaed8f
MHS		 775 time_stop = (GetCountSspClk()-time_0) << 4;
776
cee5a30d 777 rsamples = samples - Demod.samples;
778 LED_B_ON();
779
6a1f2d82 780 if(tracing) {
a501c82b 781 uint8_t parity[MAX_PARITY_SIZE];
782 GetParity(Demod.output, Demod.len, parity);
55eaed8f 783 LogTrace(Demod.output, Demod.len, time_start, time_stop, parity, FALSE);
81012e67 784 }
17cba269 785
cee5a30d 786 // And ready to receive another response.
787 memset(&Demod, 0, sizeof(Demod));
17cba269 788 Demod.output = tagToReaderResponse;
cee5a30d 789 Demod.state = DEMOD_UNSYNCD;
790 LED_C_OFF();
55eaed8f
MHS		 791 }else{
792 time_start = (GetCountSspClk()-time_0) << 4;
cee5a30d 793 }
794
795 div = 0;
796 decbyte = 0x00;
797 }
798 //}
799
800 if(BUTTON_PRESS()) {
801 DbpString("cancelled_a");
802 goto done;
803 }
804 }
805
806 DbpString("COMMAND FINISHED");
807
808 Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
3000dc4e 809 Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
cee5a30d 810
811done:
812 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
813 Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
3000dc4e 814 Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
cee5a30d 815 LED_A_OFF();
816 LED_B_OFF();
1e262141 817 LED_C_OFF();
818 LED_D_OFF();
819}
820
912a3e94 821void rotateCSN(uint8_t* originalCSN, uint8_t* rotatedCSN) {
822 int i;
823 for(i = 0; i < 8; i++) {
824 rotatedCSN[i] = (originalCSN[i] >> 3) | (originalCSN[(i+1)%8] << 5);
1e262141 825 }
826}
827
828//-----------------------------------------------------------------------------
829// Wait for commands from reader
830// Stop when button is pressed
831// Or return TRUE when command is captured
832//-----------------------------------------------------------------------------
833static int GetIClassCommandFromReader(uint8_t *received, int *len, int maxLen)
834{
912a3e94 835 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1e262141 836 // only, since we are receiving, not transmitting).
837 // Signal field is off with the appropriate LED
838 LED_D_OFF();
839 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
840
841 // Now run a `software UART' on the stream of incoming samples.
842 Uart.output = received;
843 Uart.byteCntMax = maxLen;
844 Uart.state = STATE_UNSYNCD;
845
846 for(;;) {
847 WDT_HIT();
848
849 if(BUTTON_PRESS()) return FALSE;
850
851 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
852 AT91C_BASE_SSC->SSC_THR = 0x00;
853 }
854 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
855 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
95e63594 856
1e262141 857 if(OutOfNDecoding(b & 0x0f)) {
858 *len = Uart.byteCnt;
859 return TRUE;
860 }
861 }
862 }
863}
864
645c960f
MHS		 865static uint8_t encode4Bits(const uint8_t b)
866{
867 uint8_t c = b & 0xF;
868 // OTA, the least significant bits first
869 // The columns are
870 // 1 - Bit value to send
871 // 2 - Reversed (big-endian)
872 // 3 - Encoded
873 // 4 - Hex values
874
875 switch(c){
876 // 1 2 3 4
877 case 15: return 0x55; // 1111 -> 1111 -> 01010101 -> 0x55
878 case 14: return 0x95; // 1110 -> 0111 -> 10010101 -> 0x95
879 case 13: return 0x65; // 1101 -> 1011 -> 01100101 -> 0x65
880 case 12: return 0xa5; // 1100 -> 0011 -> 10100101 -> 0xa5
881 case 11: return 0x59; // 1011 -> 1101 -> 01011001 -> 0x59
882 case 10: return 0x99; // 1010 -> 0101 -> 10011001 -> 0x99
883 case 9: return 0x69; // 1001 -> 1001 -> 01101001 -> 0x69
884 case 8: return 0xa9; // 1000 -> 0001 -> 10101001 -> 0xa9
885 case 7: return 0x56; // 0111 -> 1110 -> 01010110 -> 0x56
886 case 6: return 0x96; // 0110 -> 0110 -> 10010110 -> 0x96
887 case 5: return 0x66; // 0101 -> 1010 -> 01100110 -> 0x66
888 case 4: return 0xa6; // 0100 -> 0010 -> 10100110 -> 0xa6
889 case 3: return 0x5a; // 0011 -> 1100 -> 01011010 -> 0x5a
890 case 2: return 0x9a; // 0010 -> 0100 -> 10011010 -> 0x9a
891 case 1: return 0x6a; // 0001 -> 1000 -> 01101010 -> 0x6a
892 default: return 0xaa; // 0000 -> 0000 -> 10101010 -> 0xaa
893
894 }
895}
1e262141 896
897//-----------------------------------------------------------------------------
898// Prepare tag messages
899//-----------------------------------------------------------------------------
900static void CodeIClassTagAnswer(const uint8_t *cmd, int len)
901{
645c960f
MHS		 902
903 /*
904 * SOF comprises 3 parts;
905 * * An unmodulated time of 56.64 us
906 * * 24 pulses of 423.75 KHz (fc/32)
907 * * A logic 1, which starts with an unmodulated time of 18.88us
908 * followed by 8 pulses of 423.75kHz (fc/32)
909 *
910 *
911 * EOF comprises 3 parts:
912 * - A logic 0 (which starts with 8 pulses of fc/32 followed by an unmodulated
913 * time of 18.88us.
914 * - 24 pulses of fc/32
915 * - An unmodulated time of 56.64 us
916 *
917 *
918 * A logic 0 starts with 8 pulses of fc/32
919 * followed by an unmodulated time of 256/fc (~18,88us).
920 *
921 * A logic 0 starts with unmodulated time of 256/fc (~18,88us) followed by
922 * 8 pulses of fc/32 (also 18.88us)
923 *
924 * The mode FPGA_HF_SIMULATOR_MODULATE_424K_8BIT which we use to simulate tag,
925 * works like this.
926 * - A 1-bit input to the FPGA becomes 8 pulses on 423.5kHz (fc/32) (18.88us).
927 * - A 0-bit inptu to the FPGA becomes an unmodulated time of 18.88us
928 *
6b038d19 929 * In this mode the SOF can be written as 00011101 = 0x1D
645c960f
MHS		 930 * The EOF can be written as 10111000 = 0xb8
931 * A logic 1 is 01
932 * A logic 0 is 10
933 *
934 * */
935
1e262141 936 int i;
937
938 ToSendReset();
939
940 // Send SOF
645c960f 941 ToSend[++ToSendMax] = 0x1D;
1e262141 942
943 for(i = 0; i < len; i++) {
1e262141 944 uint8_t b = cmd[i];
645c960f
MHS		 945 ToSend[++ToSendMax] = encode4Bits(b & 0xF); //Least significant half
946 ToSend[++ToSendMax] = encode4Bits((b >>4) & 0xF);//Most significant half
1e262141 947 }
1e262141 948
949 // Send EOF
645c960f 950 ToSend[++ToSendMax] = 0xB8;
81012e67 951 //lastProxToAirDuration = 8*ToSendMax - 3*8 - 3*8;//Not counting zeroes in the beginning or end
1e262141 952 // Convert from last byte pos to length
953 ToSendMax++;
954}
955
956// Only SOF
957static void CodeIClassTagSOF()
958{
81012e67
MHS		 959 //So far a dummy implementation, not used
960 //int lastProxToAirDuration =0;
1e262141 961
81012e67 962 ToSendReset();
1e262141 963 // Send SOF
645c960f 964 ToSend[++ToSendMax] = 0x1D;
81012e67
MHS		 965// lastProxToAirDuration = 8*ToSendMax - 3*8;//Not counting zeroes in the beginning
966
1e262141 967 // Convert from last byte pos to length
968 ToSendMax++;
969}
55eaed8f 970
9f6e9d15 971int doIClassSimulation(uint8_t csn[], int breakAfterMacReceived, uint8_t *reader_mac_buf);
ff7bb4ef
MHS		 972/**
973 * @brief SimulateIClass simulates an iClass card.
974 * @param arg0 type of simulation
975 * - 0 uses the first 8 bytes in usb data as CSN
976 * - 2 "dismantling iclass"-attack. This mode iterates through all CSN's specified
977 * in the usb data. This mode collects MAC from the reader, in order to do an offline
978 * attack on the keys. For more info, see "dismantling iclass" and proxclone.com.
979 * - Other : Uses the default CSN (031fec8af7ff12e0)
980 * @param arg1 - number of CSN's contained in datain (applicable for mode 2 only)
981 * @param arg2
982 * @param datain
983 */
984void SimulateIClass(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain)
1e262141 985{
ff7bb4ef
MHS		 986 uint32_t simType = arg0;
987 uint32_t numberOfCSNS = arg1;
7cc204bf 988 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1e262141 989
ff7bb4ef 990 // Enable and clear the trace
3000dc4e
MHS		 991 set_tracing(TRUE);
992 clear_trace();
81cd0474 993
ff7bb4ef 994 uint8_t csn_crc[] = { 0x03, 0x1f, 0xec, 0x8a, 0xf7, 0xff, 0x12, 0xe0, 0x00, 0x00 };
ff7bb4ef
MHS		 995 if(simType == 0) {
996 // Use the CSN from commandline
997 memcpy(csn_crc, datain, 8);
9f6e9d15 998 doIClassSimulation(csn_crc,0,NULL);
ff7bb4ef
MHS		 999 }else if(simType == 1)
1000 {
9f6e9d15 1001 doIClassSimulation(csn_crc,0,NULL);
ff7bb4ef
MHS		 1002 }
1003 else if(simType == 2)
1004 {
9f6e9d15 1005
7b941c8d 1006 uint8_t mac_responses[USB_CMD_DATA_SIZE] = { 0 };
a501c82b 1007 Dbprintf("Going into attack mode, %d CSNS sent", numberOfCSNS);
ff7bb4ef
MHS		 1008 // In this mode, a number of csns are within datain. We'll simulate each one, one at a time
1009 // in order to collect MAC's from the reader. This can later be used in an offlne-attack
1010 // in order to obtain the keys, as in the "dismantling iclass"-paper.
9f6e9d15
MHS		 1011 int i = 0;
1012 for( ; i < numberOfCSNS && i*8+8 < USB_CMD_DATA_SIZE; i++)
ff7bb4ef
MHS		 1013 {
1014 // The usb data is 512 bytes, fitting 65 8-byte CSNs in there.
1015
1016 memcpy(csn_crc, datain+(i*8), 8);
a501c82b 1017 if(doIClassSimulation(csn_crc,1,mac_responses+i*8))
f83cc126 1018 {
645c960f 1019 cmd_send(CMD_ACK,CMD_SIMULATE_TAG_ICLASS,i,0,mac_responses,i*8);
f83cc126
MHS		 1020 return; // Button pressed
1021 }
ff7bb4ef 1022 }
9f6e9d15
MHS		 1023 cmd_send(CMD_ACK,CMD_SIMULATE_TAG_ICLASS,i,0,mac_responses,i*8);
1024
81012e67
MHS		 1025 }
1026 else{
ff7bb4ef
MHS		 1027 // We may want a mode here where we hardcode the csns to use (from proxclone).
1028 // That will speed things up a little, but not required just yet.
1029 Dbprintf("The mode is not implemented, reserved for future use");
1030 }
9f6e9d15 1031 Dbprintf("Done...");
ff7bb4ef
MHS		 1032
1033}
1034/**
1035 * @brief Does the actual simulation
1036 * @param csn - csn to use
1037 * @param breakAfterMacReceived if true, returns after reader MAC has been received.
1038 */
9f6e9d15 1039int doIClassSimulation(uint8_t csn[], int breakAfterMacReceived, uint8_t *reader_mac_buf)
ff7bb4ef 1040{
55eaed8f 1041
1e262141 1042 // CSN followed by two CRC bytes
55eaed8f 1043 uint8_t response1[] = { 0x0F} ;
1e262141 1044 uint8_t response2[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
ff7bb4ef
MHS		 1045 uint8_t response3[] = { 0,0,0,0,0,0,0,0,0,0};
1046 memcpy(response3,csn,sizeof(response3));
f83cc126 1047 Dbprintf("Simulating CSN %02x%02x%02x%02x%02x%02x%02x%02x",csn[0],csn[1],csn[2],csn[3],csn[4],csn[5],csn[6],csn[7]);
1e262141 1048 // e-Purse
1049 uint8_t response4[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1e262141 1050
1e262141 1051 // Construct anticollision-CSN
912a3e94 1052 rotateCSN(response3,response2);
1e262141 1053
1054 // Compute CRC on both CSNs
1055 ComputeCrc14443(CRC_ICLASS, response2, 8, &response2[8], &response2[9]);
1056 ComputeCrc14443(CRC_ICLASS, response3, 8, &response3[8], &response3[9]);
1057
ff7bb4ef 1058 int exitLoop = 0;
1e262141 1059 // Reader 0a
1060 // Tag 0f
1061 // Reader 0c
1062 // Tag anticoll. CSN
1063 // Reader 81 anticoll. CSN
1064 // Tag CSN
1065
55eaed8f
MHS		 1066 uint8_t *modulated_response;
1067 int modulated_response_size;
1068 uint8_t* trace_data = NULL;
1069 int trace_data_size = 0;
1070 //uint8_t sof = 0x0f;
1e262141 1071
f71f4deb 1072 // free eventually allocated BigBuf memory
1073 BigBuf_free();
645c960f 1074 // Respond SOF -- takes 1 bytes
f71f4deb 1075 uint8_t *resp1 = BigBuf_malloc(2);
1e262141 1076 int resp1Len;
1077
1078 // Anticollision CSN (rotated CSN)
645c960f 1079 // 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
f71f4deb 1080 uint8_t *resp2 = BigBuf_malloc(28);
1e262141 1081 int resp2Len;
1082
1083 // CSN
645c960f 1084 // 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
f71f4deb 1085 uint8_t *resp3 = BigBuf_malloc(30);
912a3e94 1086 int resp3Len;
1e262141 1087
1088 // e-Purse
b3cc5f29
MHS		 1089 // 18: Takes 2 bytes for SOF/EOF and 8 * 2 = 16 bytes (2 bytes/bit)
1090 uint8_t *resp4 = BigBuf_malloc(20);
1e262141 1091 int resp4Len;
1092
f71f4deb 1093 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
a501c82b 1094 memset(receivedCmd, 0x44, MAX_FRAME_SIZE);
1e262141 1095 int len;
1096
1e262141 1097 // Prepare card messages
1098 ToSendMax = 0;
1099
1100 // First card answer: SOF
1101 CodeIClassTagSOF();
1102 memcpy(resp1, ToSend, ToSendMax); resp1Len = ToSendMax;
1103
1104 // Anticollision CSN
1105 CodeIClassTagAnswer(response2, sizeof(response2));
1106 memcpy(resp2, ToSend, ToSendMax); resp2Len = ToSendMax;
1107
1108 // CSN
1109 CodeIClassTagAnswer(response3, sizeof(response3));
912a3e94 1110 memcpy(resp3, ToSend, ToSendMax); resp3Len = ToSendMax;
1e262141 1111
1112 // e-Purse
1113 CodeIClassTagAnswer(response4, sizeof(response4));
1114 memcpy(resp4, ToSend, ToSendMax); resp4Len = ToSendMax;
1115
e3dc1e4c
MHS		 1116
1117 // Start from off (no field generated)
fa541aca
MHS		 1118 //FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1119 //SpinDelay(200);
1120 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1121 SpinDelay(100);
1122 StartCountSspClk();
1e262141 1123 // We need to listen to the high-frequency, peak-detected path.
1124 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1125 FpgaSetupSsc();
1126
1127 // To control where we are in the protocol
1e262141 1128 int cmdsRecvd = 0;
81012e67
MHS		 1129 uint32_t time_0 = GetCountSspClk();
1130 uint32_t t2r_time =0;
1131 uint32_t r2t_time =0;
912a3e94 1132
1e262141 1133 LED_A_ON();
f83cc126 1134 bool buttonPressed = false;
9f6e9d15 1135
ff7bb4ef 1136 while(!exitLoop) {
81012e67 1137
1e262141 1138 LED_B_OFF();
e3dc1e4c
MHS		 1139 //Signal tracer
1140 // Can be used to get a trigger for an oscilloscope..
1141 LED_C_OFF();
1142
1e262141 1143 if(!GetIClassCommandFromReader(receivedCmd, &len, 100)) {
f83cc126 1144 buttonPressed = true;
1e262141 1145 break;
81cd0474 1146 }
81012e67 1147 r2t_time = GetCountSspClk();
e3dc1e4c
MHS		 1148 //Signal tracer
1149 LED_C_ON();
1e262141 1150
81cd0474 1151 // Okay, look at the command now.
f83cc126 1152 if(receivedCmd[0] == 0x0a ) {
1e262141 1153 // Reader in anticollission phase
55eaed8f
MHS		 1154 modulated_response = resp1; modulated_response_size = resp1Len; //order = 1;
1155 trace_data = response1;
1156 trace_data_size = sizeof(response1);
1e262141 1157 } else if(receivedCmd[0] == 0x0c) {
1158 // Reader asks for anticollission CSN
55eaed8f
MHS		 1159 modulated_response = resp2; modulated_response_size = resp2Len; //order = 2;
1160 trace_data = response2;
1161 trace_data_size = sizeof(response2);
1e262141 1162 //DbpString("Reader requests anticollission CSN:");
1163 } else if(receivedCmd[0] == 0x81) {
1164 // Reader selects anticollission CSN.
1165 // Tag sends the corresponding real CSN
55eaed8f
MHS		 1166 modulated_response = resp3; modulated_response_size = resp3Len; //order = 3;
1167 trace_data = response3;
1168 trace_data_size = sizeof(response3);
1e262141 1169 //DbpString("Reader selects anticollission CSN:");
1170 } else if(receivedCmd[0] == 0x88) {
1171 // Read e-purse (88 02)
55eaed8f
MHS		 1172 modulated_response = resp4; modulated_response_size = resp4Len; //order = 4;
1173 trace_data = response4;
1174 trace_data_size = sizeof(response4);
1e262141 1175 LED_B_ON();
1176 } else if(receivedCmd[0] == 0x05) {
1177 // Reader random and reader MAC!!!
1e262141 1178 // Do not respond
f38a1528 1179 // We do not know what to answer, so lets keep quiet
55eaed8f
MHS		 1180 modulated_response = resp1; modulated_response_size = 0; //order = 5;
1181 trace_data = NULL;
1182 trace_data_size = 0;
ff7bb4ef 1183 if (breakAfterMacReceived){
ff7bb4ef 1184 // dbprintf:ing ...
f5ed4d12 1185 Dbprintf("CSN: %02x %02x %02x %02x %02x %02x %02x %02x"
1186 ,csn[0],csn[1],csn[2],csn[3],csn[4],csn[5],csn[6],csn[7]);
ff7bb4ef 1187 Dbprintf("RDR: (len=%02d): %02x %02x %02x %02x %02x %02x %02x %02x %02x",len,
a501c82b 1188 receivedCmd[0], receivedCmd[1], receivedCmd[2],
ff7bb4ef
MHS		 1189 receivedCmd[3], receivedCmd[4], receivedCmd[5],
1190 receivedCmd[6], receivedCmd[7], receivedCmd[8]);
9f6e9d15
MHS		 1191 if (reader_mac_buf != NULL)
1192 {
1193 memcpy(reader_mac_buf,receivedCmd+1,8);
1194 }
ff7bb4ef
MHS		 1195 exitLoop = true;
1196 }
1e262141 1197 } else if(receivedCmd[0] == 0x00 && len == 1) {
1198 // Reader ends the session
55eaed8f
MHS		 1199 modulated_response = resp1; modulated_response_size = 0; //order = 0;
1200 trace_data = NULL;
1201 trace_data_size = 0;
81cd0474 1202 } else {
17cba269 1203 //#db# Unknown command received from reader (len=5): 26 1 0 f6 a 44 44 44 44
1e262141 1204 // Never seen this command before
1205 Dbprintf("Unknown command received from reader (len=%d): %x %x %x %x %x %x %x %x %x",
1206 len,
1207 receivedCmd[0], receivedCmd[1], receivedCmd[2],
1208 receivedCmd[3], receivedCmd[4], receivedCmd[5],
1209 receivedCmd[6], receivedCmd[7], receivedCmd[8]);
1210 // Do not respond
55eaed8f
MHS		 1211 modulated_response = resp1; modulated_response_size = 0; //order = 0;
1212 trace_data = NULL;
1213 trace_data_size = 0;
1e262141 1214 }
1215
81012e67
MHS		 1216 if(cmdsRecvd > 100) {
1217 //DbpString("100 commands later...");
9f6e9d15 1218 //break;
1e262141 1219 }
1220 else {
1221 cmdsRecvd++;
1222 }
55eaed8f 1223 /**
6b038d19 1224 A legit tag has about 380us delay between reader EOT and tag SOF.
55eaed8f
MHS		 1225 **/
1226 if(modulated_response_size > 0) {
645c960f 1227 SendIClassAnswer(modulated_response, modulated_response_size, 1);
81012e67 1228 t2r_time = GetCountSspClk();
81cd0474 1229 }
f83cc126 1230
81cd0474 1231 if (tracing) {
a501c82b 1232 uint8_t parity[MAX_PARITY_SIZE];
1233 GetParity(receivedCmd, len, parity);
1234 LogTrace(receivedCmd,len, (r2t_time-time_0)<< 4, (r2t_time-time_0) << 4, parity, TRUE);
17cba269 1235
55eaed8f
MHS		 1236 if (trace_data != NULL) {
1237 GetParity(trace_data, trace_data_size, parity);
1238 LogTrace(trace_data, trace_data_size, (t2r_time-time_0) << 4, (t2r_time-time_0) << 4, parity, FALSE);
17cba269 1239 }
81012e67
MHS		 1240 if(!tracing) {
1241 DbpString("Trace full");
1242 //break;
1243 }
1244
81cd0474 1245 }
a501c82b 1246 memset(receivedCmd, 0x44, MAX_FRAME_SIZE);
81cd0474 1247 }
1e262141 1248
9f6e9d15 1249 //Dbprintf("%x", cmdsRecvd);
1e262141 1250 LED_A_OFF();
1251 LED_B_OFF();
7b941c8d
MHS		 1252 LED_C_OFF();
1253
f83cc126
MHS		 1254 if(buttonPressed)
1255 {
1256 DbpString("Button pressed");
1257 }
f83cc126 1258 return buttonPressed;
1e262141 1259}
1260
1261static int SendIClassAnswer(uint8_t *resp, int respLen, int delay)
1262{
e3dc1e4c 1263 int i = 0, d=0;//, u = 0, d = 0;
1e262141 1264 uint8_t b = 0;
e3dc1e4c 1265
645c960f
MHS		 1266 //FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K);
1267 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K_8BIT);
e3dc1e4c 1268
1e262141 1269 AT91C_BASE_SSC->SSC_THR = 0x00;
1270 FpgaSetupSsc();
e3dc1e4c
MHS		 1271 while(!BUTTON_PRESS()) {
1272 if((AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)){
1273 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1e262141 1274 }
e3dc1e4c
MHS		 1275 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)){
1276 b = 0x00;
1e262141 1277 if(d < delay) {
1e262141 1278 d++;
1279 }
e3dc1e4c
MHS		 1280 else {
1281 if( i < respLen){
1282 b = resp[i];
1283 //Hack
1284 //b = 0xAC;
1285 }
1286 i++;
1e262141 1287 }
1288 AT91C_BASE_SSC->SSC_THR = b;
1e262141 1289 }
e3dc1e4c 1290
645c960f
MHS		 1291// if (i > respLen +4) break;
1292 if (i > respLen +1) break;
1e262141 1293 }
1294
1295 return 0;
1296}
1297
1298/// THE READER CODE
1299
1300//-----------------------------------------------------------------------------
1301// Transmit the command (to the tag) that was placed in ToSend[].
1302//-----------------------------------------------------------------------------
1303static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait)
1304{
1305 int c;
1e262141 1306 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1307 AT91C_BASE_SSC->SSC_THR = 0x00;
1308 FpgaSetupSsc();
1309
1310 if (wait)
f5ed4d12 1311 {
1312 if(*wait < 10) *wait = 10;
2ed270a8 1313
1e262141 1314 for(c = 0; c < *wait;) {
1315 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1316 AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing!
1317 c++;
1318 }
1319 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1320 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1321 (void)r;
1322 }
1323 WDT_HIT();
1324 }
1325
f5ed4d12 1326 }
1327
1328
1e262141 1329 uint8_t sendbyte;
1330 bool firstpart = TRUE;
1331 c = 0;
1332 for(;;) {
1333 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1334
1335 // DOUBLE THE SAMPLES!
1336 if(firstpart) {
1337 sendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4);
1338 }
1339 else {
1340 sendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4);
1341 c++;
1342 }
1343 if(sendbyte == 0xff) {
1344 sendbyte = 0xfe;
1345 }
1346 AT91C_BASE_SSC->SSC_THR = sendbyte;
1347 firstpart = !firstpart;
1348
1349 if(c >= len) {
1350 break;
1351 }
1352 }
1353 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1354 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1355 (void)r;
1356 }
1357 WDT_HIT();
1358 }
1359 if (samples) *samples = (c + *wait) << 3;
1360}
1361
1362
1363//-----------------------------------------------------------------------------
1364// Prepare iClass reader command to send to FPGA
1365//-----------------------------------------------------------------------------
1366void CodeIClassCommand(const uint8_t * cmd, int len)
1367{
1368 int i, j, k;
1369 uint8_t b;
1370
1371 ToSendReset();
1372
1373 // Start of Communication: 1 out of 4
1374 ToSend[++ToSendMax] = 0xf0;
1375 ToSend[++ToSendMax] = 0x00;
1376 ToSend[++ToSendMax] = 0x0f;
1377 ToSend[++ToSendMax] = 0x00;
1378
1379 // Modulate the bytes
1380 for (i = 0; i < len; i++) {
1381 b = cmd[i];
1382 for(j = 0; j < 4; j++) {
1383 for(k = 0; k < 4; k++) {
e3dc1e4c
MHS		 1384 if(k == (b & 3)) {
1385 ToSend[++ToSendMax] = 0x0f;
1386 }
1387 else {
1388 ToSend[++ToSendMax] = 0x00;
1389 }
1e262141 1390 }
1391 b >>= 2;
1392 }
1393 }
1394
1395 // End of Communication
1396 ToSend[++ToSendMax] = 0x00;
1397 ToSend[++ToSendMax] = 0x00;
1398 ToSend[++ToSendMax] = 0xf0;
1399 ToSend[++ToSendMax] = 0x00;
1400
1401 // Convert from last character reference to length
1402 ToSendMax++;
1403}
1404
1405void ReaderTransmitIClass(uint8_t* frame, int len)
1406{
1407 int wait = 0;
1408 int samples = 0;
1e262141 1409
1410 // This is tied to other size changes
1e262141 1411 CodeIClassCommand(frame,len);
1412
1413 // Select the card
1414 TransmitIClassCommand(ToSend, ToSendMax, &samples, &wait);
1415 if(trigger)
1416 LED_A_ON();
1417
1418 // Store reader command in buffer
6a1f2d82 1419 if (tracing) {
a501c82b 1420 uint8_t par[MAX_PARITY_SIZE];
1421 GetParity(frame, len, par);
1422 LogTrace(frame, len, rsamples, rsamples, par, TRUE);
1423 }
1e262141 1424}
1425
1426//-----------------------------------------------------------------------------
1427// Wait a certain time for tag response
1428// If a response is captured return TRUE
1429// If it takes too long return FALSE
1430//-----------------------------------------------------------------------------
1431static int GetIClassAnswer(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed) //uint8_t *buffer
1432{
1433 // buffer needs to be 512 bytes
1434 int c;
1435
1436 // Set FPGA mode to "reader listen mode", no modulation (listen
1437 // only, since we are receiving, not transmitting).
1438 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1439
1440 // Now get the answer from the card
1441 Demod.output = receivedResponse;
1442 Demod.len = 0;
1443 Demod.state = DEMOD_UNSYNCD;
1444
1445 uint8_t b;
1446 if (elapsed) *elapsed = 0;
1447
1448 bool skip = FALSE;
1449
1450 c = 0;
1451 for(;;) {
1452 WDT_HIT();
1453
95e63594 1454 if(BUTTON_PRESS()) return FALSE;
1e262141 1455
1456 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1457 AT91C_BASE_SSC->SSC_THR = 0x00; // To make use of exact timing of next command from reader!!
1458 if (elapsed) (*elapsed)++;
1459 }
1460 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1461 if(c < timeout) { c++; } else { return FALSE; }
1462 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1463 skip = !skip;
1464 if(skip) continue;
95e63594 1465
1e262141 1466 if(ManchesterDecoding(b & 0x0f)) {
1467 *samples = c << 3;
1468 return TRUE;
1469 }
1470 }
1471 }
1472}
1473
1474int ReaderReceiveIClass(uint8_t* receivedAnswer)
1475{
1476 int samples = 0;
1477 if (!GetIClassAnswer(receivedAnswer,160,&samples,0)) return FALSE;
7bc95e2e 1478 rsamples += samples;
6a1f2d82 1479 if (tracing) {
1480 uint8_t parity[MAX_PARITY_SIZE];
1481 GetParity(receivedAnswer, Demod.len, parity);
1482 LogTrace(receivedAnswer,Demod.len,rsamples,rsamples,parity,FALSE);
a501c82b 1483 }
1e262141 1484 if(samples == 0) return FALSE;
1485 return Demod.len;
1486}
1487
f38a1528 1488void setupIclassReader()
1489{
1490 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1491 // Reset trace buffer
3000dc4e
MHS		 1492 set_tracing(TRUE);
1493 clear_trace();
f38a1528 1494
1495 // Setup SSC
1496 FpgaSetupSsc();
1497 // Start from off (no field generated)
1498 // Signal field is off with the appropriate LED
1499 LED_D_OFF();
1500 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1501 SpinDelay(200);
1502
1503 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1504
1505 // Now give it time to spin up.
1506 // Signal field is on with the appropriate LED
1507 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1508 SpinDelay(200);
1509 LED_A_ON();
1510
1511}
1512
d3a22c7d 1513size_t sendCmdGetResponseWithRetries(uint8_t* command, size_t cmdsize, uint8_t* resp, uint8_t expected_size, uint8_t retries)
1514{
1515 while(retries-- > 0)
1516 {
1517 ReaderTransmitIClass(command, cmdsize);
1518 if(expected_size == ReaderReceiveIClass(resp)){
1519 return 0;
1520 }
1521 }
1522 return 1;//Error
1523}
1524
1525/**
1526 * @brief Talks to an iclass tag, sends the commands to get CSN and CC.
1527 * @param card_data where the CSN and CC are stored for return
1528 * @return 0 = fail
1529 * 1 = Got CSN
1530 * 2 = Got CSN and CC
1531 */
1532uint8_t handshakeIclassTag(uint8_t *card_data)
1533{
1534 static uint8_t act_all[] = { 0x0a };
1535 static uint8_t identify[] = { 0x0c };
1536 static uint8_t select[] = { 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1537 static uint8_t readcheck_cc[]= { 0x88, 0x02 };
f71f4deb 1538 uint8_t resp[ICLASS_BUFFER_SIZE];
d3a22c7d 1539
1540 uint8_t read_status = 0;
1541
1542 // Send act_all
1543 ReaderTransmitIClass(act_all, 1);
1544 // Card present?
1545 if(!ReaderReceiveIClass(resp)) return read_status;//Fail
1546 //Send Identify
1547 ReaderTransmitIClass(identify, 1);
1548 //We expect a 10-byte response here, 8 byte anticollision-CSN and 2 byte CRC
1549 uint8_t len = ReaderReceiveIClass(resp);
1550 if(len != 10) return read_status;//Fail
1551
1552 //Copy the Anti-collision CSN to our select-packet
1553 memcpy(&select[1],resp,8);
1554 //Select the card
1555 ReaderTransmitIClass(select, sizeof(select));
1556 //We expect a 10-byte response here, 8 byte CSN and 2 byte CRC
1557 len = ReaderReceiveIClass(resp);
1558 if(len != 10) return read_status;//Fail
1559
1560 //Success - level 1, we got CSN
1561 //Save CSN in response data
1562 memcpy(card_data,resp,8);
1563
1564 //Flag that we got to at least stage 1, read CSN
1565 read_status = 1;
1566
1567 // Card selected, now read e-purse (cc)
1568 ReaderTransmitIClass(readcheck_cc, sizeof(readcheck_cc));
1569 if(ReaderReceiveIClass(resp) == 8) {
1570 //Save CC (e-purse) in response data
1571 memcpy(card_data+8,resp,8);
1572
1573 //Got both
1574 read_status = 2;
1575 }
1576
1577 return read_status;
1578}
1579
1e262141 1580// Reader iClass Anticollission
1581void ReaderIClass(uint8_t arg0) {
f38a1528 1582
1583 uint8_t card_data[24]={0};
1584 uint8_t last_csn[8]={0};
6a1f2d82 1585
f38a1528 1586 int read_status= 0;
1587 bool abort_after_read = arg0 & FLAG_ICLASS_READER_ONLY_ONCE;
d3a22c7d 1588 bool get_cc = arg0 & FLAG_ICLASS_READER_GET_CC;
3000dc4e 1589 set_tracing(TRUE);
f38a1528 1590 setupIclassReader();
1591
1592 size_t datasize = 0;
1593 while(!BUTTON_PRESS())
1594 {
d3a22c7d 1595
3000dc4e 1596 if(!tracing) {
d3a22c7d 1597 DbpString("Trace full");
1598 break;
1599 }
c8dd9b09 1600 WDT_HIT();
f38a1528 1601
d3a22c7d 1602 read_status = handshakeIclassTag(card_data);
1603
1604 if(read_status == 0) continue;
1605 if(read_status == 1) datasize = 8;
1606 if(read_status == 2) datasize = 16;
f38a1528 1607
1608 LED_B_ON();
1609 //Send back to client, but don't bother if we already sent this
1610 if(memcmp(last_csn, card_data, 8) != 0)
d3a22c7d 1611 {
f38a1528 1612
d3a22c7d 1613 if(!get_cc || (get_cc && read_status == 2))
1614 {
1615 cmd_send(CMD_ACK,read_status,0,0,card_data,datasize);
1616 if(abort_after_read) {
1617 LED_A_OFF();
1618 return;
1619 }
f38a1528 1620 //Save that we already sent this....
f38a1528 1621 memcpy(last_csn, card_data, 8);
d3a22c7d 1622 }
1623 //If 'get_cc' was specified and we didn't get a CC, we'll just keep trying...
1624 }
c8dd9b09 1625 LED_B_OFF();
f38a1528 1626 }
d3a22c7d 1627 cmd_send(CMD_ACK,0,0,0,card_data, 0);
aa41c605 1628 LED_A_OFF();
f38a1528 1629}
1630
1631void ReaderIClass_Replay(uint8_t arg0, uint8_t *MAC) {
d3a22c7d 1632
14edfd09 1633 uint8_t card_data[USB_CMD_DATA_SIZE]={0};
d3a22c7d 1634 uint16_t block_crc_LUT[255] = {0};
1635
1636 {//Generate a lookup table for block crc
1637 for(int block = 0; block < 255; block++){
1638 char bl = block;
1639 block_crc_LUT[block] = iclass_crc16(&bl ,1);
1640 }
1641 }
1642 //Dbprintf("Lookup table: %02x %02x %02x" ,block_crc_LUT[0],block_crc_LUT[1],block_crc_LUT[2]);
1643
f38a1528 1644 uint8_t check[] = { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1645 uint8_t read[] = { 0x0c, 0x00, 0x00, 0x00 };
1646
fecd8202 1647 uint16_t crc = 0;
f38a1528 1648 uint8_t cardsize=0;
f38a1528 1649 uint8_t mem=0;
1650
1651 static struct memory_t{
1652 int k16;
1653 int book;
1654 int k2;
1655 int lockauth;
1656 int keyaccess;
1657 } memory;
1658
f71f4deb 1659 uint8_t resp[ICLASS_BUFFER_SIZE];
6a1f2d82 1660
f38a1528 1661 setupIclassReader();
3000dc4e 1662 set_tracing(TRUE);
f38a1528 1663
d3a22c7d 1664 while(!BUTTON_PRESS()) {
1665
1666 WDT_HIT();
39d3ce5d 1667
3000dc4e 1668 if(!tracing) {
f38a1528 1669 DbpString("Trace full");
1670 break;
1671 }
1672
d3a22c7d 1673 uint8_t read_status = handshakeIclassTag(card_data);
1674 if(read_status < 2) continue;
1675
f38a1528 1676 //for now replay captured auth (as cc not updated)
1677 memcpy(check+5,MAC,4);
d3a22c7d 1678
1679 if(sendCmdGetResponseWithRetries(check, sizeof(check),resp, 4, 5))
1680 {
f38a1528 1681 Dbprintf("Error: Authentication Fail!");
d3a22c7d 1682 continue;
f38a1528 1683 }
d3a22c7d 1684
1685 //first get configuration block (block 1)
1686 crc = block_crc_LUT[1];
f38a1528 1687 read[1]=1;
f38a1528 1688 read[2] = crc >> 8;
1689 read[3] = crc & 0xff;
d3a22c7d 1690
1691 if(sendCmdGetResponseWithRetries(read, sizeof(read),resp, 10, 10))
1692 {
1693 Dbprintf("Dump config (block 1) failed");
1694 continue;
1695 }
1696
f38a1528 1697 mem=resp[5];
1698 memory.k16= (mem & 0x80);
1699 memory.book= (mem & 0x20);
1700 memory.k2= (mem & 0x8);
1701 memory.lockauth= (mem & 0x2);
1702 memory.keyaccess= (mem & 0x1);
1703
d3a22c7d 1704 cardsize = memory.k16 ? 255 : 32;
1705 WDT_HIT();
14edfd09 1706 //Set card_data to all zeroes, we'll fill it with data
1707 memset(card_data,0x0,USB_CMD_DATA_SIZE);
1708 uint8_t failedRead =0;
1709 uint8_t stored_data_length =0;
f38a1528 1710 //then loop around remaining blocks
d3a22c7d 1711 for(int block=0; block < cardsize; block++){
1712
1713 read[1]= block;
1714 crc = block_crc_LUT[block];
f38a1528 1715 read[2] = crc >> 8;
1716 read[3] = crc & 0xff;
d3a22c7d 1717
1718 if(!sendCmdGetResponseWithRetries(read, sizeof(read), resp, 10, 10))
1719 {
f38a1528 1720 Dbprintf(" %02x: %02x %02x %02x %02x %02x %02x %02x %02x",
d3a22c7d 1721 block, resp[0], resp[1], resp[2],
f38a1528 1722 resp[3], resp[4], resp[5],
1723 resp[6], resp[7]);
d3a22c7d 1724
14edfd09 1725 //Fill up the buffer
1726 memcpy(card_data+stored_data_length,resp,8);
1727 stored_data_length += 8;
1728
1729 if(stored_data_length +8 > USB_CMD_DATA_SIZE)
1730 {//Time to send this off and start afresh
1731 cmd_send(CMD_ACK,
1732 stored_data_length,//data length
1733 failedRead,//Failed blocks?
1734 0,//Not used ATM
1735 card_data, stored_data_length);
1736 //reset
1737 stored_data_length = 0;
1738 failedRead = 0;
1739 }
1740
d3a22c7d 1741 }else{
14edfd09 1742 failedRead = 1;
1743 stored_data_length +=8;//Otherwise, data becomes misaligned
d3a22c7d 1744 Dbprintf("Failed to dump block %d", block);
f38a1528 1745 }
1746 }
14edfd09 1747 //Send off any remaining data
1748 if(stored_data_length > 0)
1749 {
1750 cmd_send(CMD_ACK,
1751 stored_data_length,//data length
1752 failedRead,//Failed blocks?
1753 0,//Not used ATM
1754 card_data, stored_data_length);
1755 }
d3a22c7d 1756 //If we got here, let's break
1757 break;
f38a1528 1758 }
14edfd09 1759 //Signal end of transmission
1760 cmd_send(CMD_ACK,
1761 0,//data length
1762 0,//Failed blocks?
1763 0,//Not used ATM
1764 card_data, 0);
1765
f38a1528 1766 LED_A_OFF();
1767}
1768
1769//2. Create Read method (cut-down from above) based off responses from 1.
1770// Since we have the MAC could continue to use replay function.
1771//3. Create Write method
1772/*
1773void IClass_iso14443A_write(uint8_t arg0, uint8_t blockNo, uint8_t *data, uint8_t *MAC) {
1774 uint8_t act_all[] = { 0x0a };
1775 uint8_t identify[] = { 0x0c };
1776 uint8_t select[] = { 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1777 uint8_t readcheck_cc[]= { 0x88, 0x02 };
1778 uint8_t check[] = { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1779 uint8_t read[] = { 0x0c, 0x00, 0x00, 0x00 };
1780 uint8_t write[] = { 0x87, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1781
1782 uint16_t crc = 0;
1783
14edfd09 1784 uint8_t* resp = (((uint8_t *)BigBuf) + 3560);
7cc204bf 1785
1e262141 1786 // Reset trace buffer
ff7bb4ef 1787 memset(trace, 0x44, RECV_CMD_OFFSET);
1e262141 1788 traceLen = 0;
1789
1790 // Setup SSC
1791 FpgaSetupSsc();
1792 // Start from off (no field generated)
1793 // Signal field is off with the appropriate LED
cee5a30d 1794 LED_D_OFF();
1e262141 1795 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1796 SpinDelay(200);
1797
1798 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1799
1800 // Now give it time to spin up.
1801 // Signal field is on with the appropriate LED
1802 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1803 SpinDelay(200);
1804
1805 LED_A_ON();
1806
f38a1528 1807 for(int i=0;i<1;i++) {
4ab4336a 1808
1809 if(traceLen > TRACE_SIZE) {
1810 DbpString("Trace full");
1811 break;
1812 }
1813
1814 if (BUTTON_PRESS()) break;
1e262141 1815
1816 // Send act_all
1817 ReaderTransmitIClass(act_all, 1);
1818 // Card present?
1819 if(ReaderReceiveIClass(resp)) {
1820 ReaderTransmitIClass(identify, 1);
4ab4336a 1821 if(ReaderReceiveIClass(resp) == 10) {
1822 // Select card
1823 memcpy(&select[1],resp,8);
1824 ReaderTransmitIClass(select, sizeof(select));
1825
1826 if(ReaderReceiveIClass(resp) == 10) {
1827 Dbprintf(" Selected CSN: %02x %02x %02x %02x %02x %02x %02x %02x",
1828 resp[0], resp[1], resp[2],
1829 resp[3], resp[4], resp[5],
1830 resp[6], resp[7]);
1831 }
f38a1528 1832 // Card selected
1833 Dbprintf("Readcheck on Sector 2");
1834 ReaderTransmitIClass(readcheck_cc, sizeof(readcheck_cc));
1835 if(ReaderReceiveIClass(resp) == 8) {
1836 Dbprintf(" CC: %02x %02x %02x %02x %02x %02x %02x %02x",
1837 resp[0], resp[1], resp[2],
1838 resp[3], resp[4], resp[5],
1839 resp[6], resp[7]);
1840 }else return;
1841 Dbprintf("Authenticate");
1842 //for now replay captured auth (as cc not updated)
1843 memcpy(check+5,MAC,4);
1844 Dbprintf(" AA: %02x %02x %02x %02x",
1845 check[5], check[6], check[7],check[8]);
1846 ReaderTransmitIClass(check, sizeof(check));
1847 if(ReaderReceiveIClass(resp) == 4) {
1848 Dbprintf(" AR: %02x %02x %02x %02x",
1849 resp[0], resp[1], resp[2],resp[3]);
1850 }else {
1851 Dbprintf("Error: Authentication Fail!");
1852 return;
1853 }
1854 Dbprintf("Write Block");
1855
1856 //read configuration for max block number
1857 read_success=false;
1858 read[1]=1;
1859 uint8_t *blockno=&read[1];
1860 crc = iclass_crc16((char *)blockno,1);
1861 read[2] = crc >> 8;
1862 read[3] = crc & 0xff;
1863 while(!read_success){
1864 ReaderTransmitIClass(read, sizeof(read));
1865 if(ReaderReceiveIClass(resp) == 10) {
1866 read_success=true;
1867 mem=resp[5];
1868 memory.k16= (mem & 0x80);
1869 memory.book= (mem & 0x20);
1870 memory.k2= (mem & 0x8);
1871 memory.lockauth= (mem & 0x2);
1872 memory.keyaccess= (mem & 0x1);
1873
1874 }
1875 }
1876 if (memory.k16){
1877 cardsize=255;
1878 }else cardsize=32;
1879 //check card_size
1880
1881 memcpy(write+1,blockNo,1);
1882 memcpy(write+2,data,8);
1883 memcpy(write+10,mac,4);
1884 while(!send_success){
1885 ReaderTransmitIClass(write, sizeof(write));
fecd8202 1886 if(ReaderReceiveIClass(resp) == 10) {
f38a1528 1887 write_success=true;
1888 }
1889 }//
1e262141 1890 }
1891 WDT_HIT();
1892 }
1893
1894 LED_A_OFF();
f38a1528 1895}*/
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