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cleaned up memmory
[proxmark3-svn] / armsrc / lfops.c
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15c4dc5a 1//-----------------------------------------------------------------------------
bd20f8f4 2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
15c4dc5a 6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10
e30c654b 11#include "proxmark3.h"
15c4dc5a 12#include "apps.h"
f7e3ed82 13#include "util.h"
15c4dc5a 14#include "hitag2.h"
15#include "crc16.h"
9ab7a6c7 16#include "string.h"
15c4dc5a 17
f7e3ed82 18void AcquireRawAdcSamples125k(int at134khz)
15c4dc5a 19{
20 if (at134khz)
21 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
22 else
23 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
24
25 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
26
27 // Connect the A/D to the peak-detected low-frequency path.
28 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
29
30 // Give it a bit of time for the resonant antenna to settle.
31 SpinDelay(50);
32
33 // Now set up the SSC to get the ADC samples that are now streaming at us.
34 FpgaSetupSsc();
35
36 // Now call the acquisition routine
37 DoAcquisition125k();
38}
39
40// split into two routines so we can avoid timing issues after sending commands //
41void DoAcquisition125k(void)
42{
f7e3ed82 43 uint8_t *dest = (uint8_t *)BigBuf;
15c4dc5a 44 int n = sizeof(BigBuf);
45 int i;
e30c654b 46
15c4dc5a 47 memset(dest, 0, n);
48 i = 0;
49 for(;;) {
50 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
51 AT91C_BASE_SSC->SSC_THR = 0x43;
52 LED_D_ON();
53 }
54 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
f7e3ed82 55 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 56 i++;
57 LED_D_OFF();
58 if (i >= n) break;
59 }
60 }
61 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
62 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
63}
64
f7e3ed82 65void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
15c4dc5a 66{
f7e3ed82 67 int at134khz;
15c4dc5a 68
69 /* Make sure the tag is reset */
70 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
71 SpinDelay(2500);
e30c654b 72
15c4dc5a 73 // see if 'h' was specified
74 if (command[strlen((char *) command) - 1] == 'h')
75 at134khz = TRUE;
76 else
77 at134khz = FALSE;
78
79 if (at134khz)
80 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
81 else
82 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
83
84 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
85
86 // Give it a bit of time for the resonant antenna to settle.
87 SpinDelay(50);
88 // And a little more time for the tag to fully power up
89 SpinDelay(2000);
90
91 // Now set up the SSC to get the ADC samples that are now streaming at us.
92 FpgaSetupSsc();
93
94 // now modulate the reader field
95 while(*command != '\0' && *command != ' ') {
96 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
97 LED_D_OFF();
98 SpinDelayUs(delay_off);
99 if (at134khz)
100 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
101 else
102 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
103
104 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
105 LED_D_ON();
106 if(*(command++) == '0')
107 SpinDelayUs(period_0);
108 else
109 SpinDelayUs(period_1);
110 }
111 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
112 LED_D_OFF();
113 SpinDelayUs(delay_off);
114 if (at134khz)
115 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
116 else
117 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
118
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
120
121 // now do the read
122 DoAcquisition125k();
123}
124
125/* blank r/w tag data stream
126...0000000000000000 01111111
1271010101010101010101010101010101010101010101010101010101010101010
1280011010010100001
12901111111
130101010101010101[0]000...
131
132[5555fe852c5555555555555555fe0000]
133*/
134void ReadTItag(void)
135{
136 // some hardcoded initial params
137 // when we read a TI tag we sample the zerocross line at 2Mhz
138 // TI tags modulate a 1 as 16 cycles of 123.2Khz
139 // TI tags modulate a 0 as 16 cycles of 134.2Khz
140 #define FSAMPLE 2000000
141 #define FREQLO 123200
142 #define FREQHI 134200
143
144 signed char *dest = (signed char *)BigBuf;
145 int n = sizeof(BigBuf);
146// int *dest = GraphBuffer;
147// int n = GraphTraceLen;
148
149 // 128 bit shift register [shift3:shift2:shift1:shift0]
f7e3ed82 150 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
15c4dc5a 151
152 int i, cycles=0, samples=0;
153 // how many sample points fit in 16 cycles of each frequency
f7e3ed82 154 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
15c4dc5a 155 // when to tell if we're close enough to one freq or another
f7e3ed82 156 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
15c4dc5a 157
158 // TI tags charge at 134.2Khz
159 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
160
161 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
162 // connects to SSP_DIN and the SSP_DOUT logic level controls
163 // whether we're modulating the antenna (high)
164 // or listening to the antenna (low)
165 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
166
167 // get TI tag data into the buffer
168 AcquireTiType();
169
170 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
171
172 for (i=0; i<n-1; i++) {
173 // count cycles by looking for lo to hi zero crossings
174 if ( (dest[i]<0) && (dest[i+1]>0) ) {
175 cycles++;
176 // after 16 cycles, measure the frequency
177 if (cycles>15) {
178 cycles=0;
179 samples=i-samples; // number of samples in these 16 cycles
180
181 // TI bits are coming to us lsb first so shift them
182 // right through our 128 bit right shift register
183 shift0 = (shift0>>1) | (shift1 << 31);
184 shift1 = (shift1>>1) | (shift2 << 31);
185 shift2 = (shift2>>1) | (shift3 << 31);
186 shift3 >>= 1;
187
188 // check if the cycles fall close to the number
189 // expected for either the low or high frequency
190 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
191 // low frequency represents a 1
192 shift3 |= (1<<31);
193 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
194 // high frequency represents a 0
195 } else {
196 // probably detected a gay waveform or noise
197 // use this as gaydar or discard shift register and start again
198 shift3 = shift2 = shift1 = shift0 = 0;
199 }
200 samples = i;
201
202 // for each bit we receive, test if we've detected a valid tag
203
204 // if we see 17 zeroes followed by 6 ones, we might have a tag
205 // remember the bits are backwards
206 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
207 // if start and end bytes match, we have a tag so break out of the loop
208 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
209 cycles = 0xF0B; //use this as a flag (ugly but whatever)
210 break;
211 }
212 }
213 }
214 }
215 }
216
217 // if flag is set we have a tag
218 if (cycles!=0xF0B) {
219 DbpString("Info: No valid tag detected.");
220 } else {
221 // put 64 bit data into shift1 and shift0
222 shift0 = (shift0>>24) | (shift1 << 8);
223 shift1 = (shift1>>24) | (shift2 << 8);
224
225 // align 16 bit crc into lower half of shift2
226 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
227
228 // if r/w tag, check ident match
229 if ( shift3&(1<<15) ) {
230 DbpString("Info: TI tag is rewriteable");
231 // only 15 bits compare, last bit of ident is not valid
232 if ( ((shift3>>16)^shift0)&0x7fff ) {
233 DbpString("Error: Ident mismatch!");
234 } else {
235 DbpString("Info: TI tag ident is valid");
236 }
237 } else {
238 DbpString("Info: TI tag is readonly");
239 }
240
241 // WARNING the order of the bytes in which we calc crc below needs checking
242 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
243 // bytes in reverse or something
244 // calculate CRC
f7e3ed82 245 uint32_t crc=0;
15c4dc5a 246
247 crc = update_crc16(crc, (shift0)&0xff);
248 crc = update_crc16(crc, (shift0>>8)&0xff);
249 crc = update_crc16(crc, (shift0>>16)&0xff);
250 crc = update_crc16(crc, (shift0>>24)&0xff);
251 crc = update_crc16(crc, (shift1)&0xff);
252 crc = update_crc16(crc, (shift1>>8)&0xff);
253 crc = update_crc16(crc, (shift1>>16)&0xff);
254 crc = update_crc16(crc, (shift1>>24)&0xff);
255
256 Dbprintf("Info: Tag data: %x%08x, crc=%x",
257 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
258 if (crc != (shift2&0xffff)) {
259 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
260 } else {
261 DbpString("Info: CRC is good");
262 }
263 }
264}
265
f7e3ed82 266void WriteTIbyte(uint8_t b)
15c4dc5a 267{
268 int i = 0;
269
270 // modulate 8 bits out to the antenna
271 for (i=0; i<8; i++)
272 {
273 if (b&(1<<i)) {
274 // stop modulating antenna
275 LOW(GPIO_SSC_DOUT);
276 SpinDelayUs(1000);
277 // modulate antenna
278 HIGH(GPIO_SSC_DOUT);
279 SpinDelayUs(1000);
280 } else {
281 // stop modulating antenna
282 LOW(GPIO_SSC_DOUT);
283 SpinDelayUs(300);
284 // modulate antenna
285 HIGH(GPIO_SSC_DOUT);
286 SpinDelayUs(1700);
287 }
288 }
289}
290
291void AcquireTiType(void)
292{
293 int i, j, n;
294 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
f7e3ed82 295 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
15c4dc5a 296 #define TIBUFLEN 1250
297
298 // clear buffer
299 memset(BigBuf,0,sizeof(BigBuf));
300
301 // Set up the synchronous serial port
302 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
303 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
304
305 // steal this pin from the SSP and use it to control the modulation
306 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
307 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
308
309 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
310 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
311
312 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
313 // 48/2 = 24 MHz clock must be divided by 12
314 AT91C_BASE_SSC->SSC_CMR = 12;
315
316 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
317 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
318 AT91C_BASE_SSC->SSC_TCMR = 0;
319 AT91C_BASE_SSC->SSC_TFMR = 0;
320
321 LED_D_ON();
322
323 // modulate antenna
324 HIGH(GPIO_SSC_DOUT);
325
326 // Charge TI tag for 50ms.
327 SpinDelay(50);
328
329 // stop modulating antenna and listen
330 LOW(GPIO_SSC_DOUT);
331
332 LED_D_OFF();
333
334 i = 0;
335 for(;;) {
336 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
337 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
338 i++; if(i >= TIBUFLEN) break;
339 }
340 WDT_HIT();
341 }
342
343 // return stolen pin to SSP
344 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
345 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
346
347 char *dest = (char *)BigBuf;
348 n = TIBUFLEN*32;
349 // unpack buffer
350 for (i=TIBUFLEN-1; i>=0; i--) {
351 for (j=0; j<32; j++) {
352 if(BigBuf[i] & (1 << j)) {
353 dest[--n] = 1;
354 } else {
355 dest[--n] = -1;
356 }
357 }
358 }
359}
360
361// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
362// if crc provided, it will be written with the data verbatim (even if bogus)
363// if not provided a valid crc will be computed from the data and written.
f7e3ed82 364void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
15c4dc5a 365{
366 if(crc == 0) {
367 crc = update_crc16(crc, (idlo)&0xff);
368 crc = update_crc16(crc, (idlo>>8)&0xff);
369 crc = update_crc16(crc, (idlo>>16)&0xff);
370 crc = update_crc16(crc, (idlo>>24)&0xff);
371 crc = update_crc16(crc, (idhi)&0xff);
372 crc = update_crc16(crc, (idhi>>8)&0xff);
373 crc = update_crc16(crc, (idhi>>16)&0xff);
374 crc = update_crc16(crc, (idhi>>24)&0xff);
375 }
376 Dbprintf("Writing to tag: %x%08x, crc=%x",
377 (unsigned int) idhi, (unsigned int) idlo, crc);
378
379 // TI tags charge at 134.2Khz
380 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
381 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
382 // connects to SSP_DIN and the SSP_DOUT logic level controls
383 // whether we're modulating the antenna (high)
384 // or listening to the antenna (low)
385 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
386 LED_A_ON();
387
388 // steal this pin from the SSP and use it to control the modulation
389 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
390 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
391
392 // writing algorithm:
393 // a high bit consists of a field off for 1ms and field on for 1ms
394 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
395 // initiate a charge time of 50ms (field on) then immediately start writing bits
396 // start by writing 0xBB (keyword) and 0xEB (password)
397 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
398 // finally end with 0x0300 (write frame)
399 // all data is sent lsb firts
400 // finish with 15ms programming time
401
402 // modulate antenna
403 HIGH(GPIO_SSC_DOUT);
404 SpinDelay(50); // charge time
405
406 WriteTIbyte(0xbb); // keyword
407 WriteTIbyte(0xeb); // password
408 WriteTIbyte( (idlo )&0xff );
409 WriteTIbyte( (idlo>>8 )&0xff );
410 WriteTIbyte( (idlo>>16)&0xff );
411 WriteTIbyte( (idlo>>24)&0xff );
412 WriteTIbyte( (idhi )&0xff );
413 WriteTIbyte( (idhi>>8 )&0xff );
414 WriteTIbyte( (idhi>>16)&0xff );
415 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
416 WriteTIbyte( (crc )&0xff ); // crc lo
417 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
418 WriteTIbyte(0x00); // write frame lo
419 WriteTIbyte(0x03); // write frame hi
420 HIGH(GPIO_SSC_DOUT);
421 SpinDelay(50); // programming time
422
423 LED_A_OFF();
424
425 // get TI tag data into the buffer
426 AcquireTiType();
427
428 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
429 DbpString("Now use tiread to check");
430}
431
432void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
433{
434 int i;
f7e3ed82 435 uint8_t *tab = (uint8_t *)BigBuf;
d19929cb 436
437 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
438
15c4dc5a 439 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
d19929cb 440
15c4dc5a 441 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
442 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
d19929cb 443
15c4dc5a 444#define SHORT_COIL() LOW(GPIO_SSC_DOUT)
445#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
d19929cb 446
15c4dc5a 447 i = 0;
448 for(;;) {
449 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
450 if(BUTTON_PRESS()) {
451 DbpString("Stopped");
452 return;
453 }
454 WDT_HIT();
455 }
d19929cb 456
15c4dc5a 457 if (ledcontrol)
458 LED_D_ON();
d19929cb 459
15c4dc5a 460 if(tab[i])
461 OPEN_COIL();
462 else
463 SHORT_COIL();
d19929cb 464
15c4dc5a 465 if (ledcontrol)
466 LED_D_OFF();
d19929cb 467
15c4dc5a 468 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
469 if(BUTTON_PRESS()) {
470 DbpString("Stopped");
471 return;
472 }
473 WDT_HIT();
474 }
d19929cb 475
15c4dc5a 476 i++;
477 if(i == period) {
478 i = 0;
e30c654b 479 if (gap) {
15c4dc5a 480 SHORT_COIL();
481 SpinDelayUs(gap);
482 }
483 }
484 }
485}
486
15c4dc5a 487#define DEBUG_FRAME_CONTENTS 1
488void SimulateTagLowFrequencyBidir(int divisor, int t0)
489{
15c4dc5a 490}
491
492// compose fc/8 fc/10 waveform
493static void fc(int c, int *n) {
f7e3ed82 494 uint8_t *dest = (uint8_t *)BigBuf;
15c4dc5a 495 int idx;
496
497 // for when we want an fc8 pattern every 4 logical bits
498 if(c==0) {
499 dest[((*n)++)]=1;
500 dest[((*n)++)]=1;
501 dest[((*n)++)]=0;
502 dest[((*n)++)]=0;
503 dest[((*n)++)]=0;
504 dest[((*n)++)]=0;
505 dest[((*n)++)]=0;
506 dest[((*n)++)]=0;
507 }
508 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
509 if(c==8) {
510 for (idx=0; idx<6; idx++) {
511 dest[((*n)++)]=1;
512 dest[((*n)++)]=1;
513 dest[((*n)++)]=0;
514 dest[((*n)++)]=0;
515 dest[((*n)++)]=0;
516 dest[((*n)++)]=0;
517 dest[((*n)++)]=0;
518 dest[((*n)++)]=0;
519 }
520 }
521
522 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
523 if(c==10) {
524 for (idx=0; idx<5; idx++) {
525 dest[((*n)++)]=1;
526 dest[((*n)++)]=1;
527 dest[((*n)++)]=1;
528 dest[((*n)++)]=0;
529 dest[((*n)++)]=0;
530 dest[((*n)++)]=0;
531 dest[((*n)++)]=0;
532 dest[((*n)++)]=0;
533 dest[((*n)++)]=0;
534 dest[((*n)++)]=0;
535 }
536 }
537}
538
539// prepare a waveform pattern in the buffer based on the ID given then
540// simulate a HID tag until the button is pressed
541void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
542{
543 int n=0, i=0;
544 /*
545 HID tag bitstream format
546 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
547 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
548 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
549 A fc8 is inserted before every 4 bits
550 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
551 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
552 */
553
554 if (hi>0xFFF) {
555 DbpString("Tags can only have 44 bits.");
556 return;
557 }
558 fc(0,&n);
559 // special start of frame marker containing invalid bit sequences
560 fc(8, &n); fc(8, &n); // invalid
561 fc(8, &n); fc(10, &n); // logical 0
562 fc(10, &n); fc(10, &n); // invalid
563 fc(8, &n); fc(10, &n); // logical 0
564
565 WDT_HIT();
566 // manchester encode bits 43 to 32
567 for (i=11; i>=0; i--) {
568 if ((i%4)==3) fc(0,&n);
569 if ((hi>>i)&1) {
570 fc(10, &n); fc(8, &n); // low-high transition
571 } else {
572 fc(8, &n); fc(10, &n); // high-low transition
573 }
574 }
575
576 WDT_HIT();
577 // manchester encode bits 31 to 0
578 for (i=31; i>=0; i--) {
579 if ((i%4)==3) fc(0,&n);
580 if ((lo>>i)&1) {
581 fc(10, &n); fc(8, &n); // low-high transition
582 } else {
583 fc(8, &n); fc(10, &n); // high-low transition
584 }
585 }
586
587 if (ledcontrol)
588 LED_A_ON();
589 SimulateTagLowFrequency(n, 0, ledcontrol);
590
591 if (ledcontrol)
592 LED_A_OFF();
593}
594
595
596// loop to capture raw HID waveform then FSK demodulate the TAG ID from it
597void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
598{
f7e3ed82 599 uint8_t *dest = (uint8_t *)BigBuf;
15c4dc5a 600 int m=0, n=0, i=0, idx=0, found=0, lastval=0;
f7e3ed82 601 uint32_t hi=0, lo=0;
15c4dc5a 602
603 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
604 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
605
606 // Connect the A/D to the peak-detected low-frequency path.
607 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
608
609 // Give it a bit of time for the resonant antenna to settle.
610 SpinDelay(50);
611
612 // Now set up the SSC to get the ADC samples that are now streaming at us.
613 FpgaSetupSsc();
614
615 for(;;) {
616 WDT_HIT();
617 if (ledcontrol)
618 LED_A_ON();
619 if(BUTTON_PRESS()) {
620 DbpString("Stopped");
621 if (ledcontrol)
622 LED_A_OFF();
623 return;
624 }
625
626 i = 0;
627 m = sizeof(BigBuf);
628 memset(dest,128,m);
629 for(;;) {
630 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
631 AT91C_BASE_SSC->SSC_THR = 0x43;
632 if (ledcontrol)
633 LED_D_ON();
634 }
635 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
f7e3ed82 636 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 637 // we don't care about actual value, only if it's more or less than a
638 // threshold essentially we capture zero crossings for later analysis
639 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
640 i++;
641 if (ledcontrol)
642 LED_D_OFF();
643 if(i >= m) {
644 break;
645 }
646 }
647 }
648
649 // FSK demodulator
650
651 // sync to first lo-hi transition
652 for( idx=1; idx<m; idx++) {
653 if (dest[idx-1]<dest[idx])
654 lastval=idx;
655 break;
656 }
657 WDT_HIT();
658
659 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
660 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
661 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
662 for( i=0; idx<m; idx++) {
663 if (dest[idx-1]<dest[idx]) {
664 dest[i]=idx-lastval;
665 if (dest[i] <= 8) {
666 dest[i]=1;
667 } else {
668 dest[i]=0;
669 }
670
671 lastval=idx;
672 i++;
673 }
674 }
675 m=i;
676 WDT_HIT();
677
678 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
679 lastval=dest[0];
680 idx=0;
681 i=0;
682 n=0;
683 for( idx=0; idx<m; idx++) {
684 if (dest[idx]==lastval) {
685 n++;
686 } else {
687 // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,
688 // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets
689 // swallowed up by rounding
690 // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding
691 // special start of frame markers use invalid manchester states (no transitions) by using sequences
692 // like 111000
693 if (dest[idx-1]) {
694 n=(n+1)/6; // fc/8 in sets of 6
695 } else {
696 n=(n+1)/5; // fc/10 in sets of 5
697 }
698 switch (n) { // stuff appropriate bits in buffer
699 case 0:
700 case 1: // one bit
701 dest[i++]=dest[idx-1];
702 break;
703 case 2: // two bits
704 dest[i++]=dest[idx-1];
705 dest[i++]=dest[idx-1];
706 break;
707 case 3: // 3 bit start of frame markers
708 dest[i++]=dest[idx-1];
709 dest[i++]=dest[idx-1];
710 dest[i++]=dest[idx-1];
711 break;
712 // When a logic 0 is immediately followed by the start of the next transmisson
713 // (special pattern) a pattern of 4 bit duration lengths is created.
714 case 4:
715 dest[i++]=dest[idx-1];
716 dest[i++]=dest[idx-1];
717 dest[i++]=dest[idx-1];
718 dest[i++]=dest[idx-1];
719 break;
720 default: // this shouldn't happen, don't stuff any bits
721 break;
722 }
723 n=0;
724 lastval=dest[idx];
725 }
726 }
727 m=i;
728 WDT_HIT();
729
730 // final loop, go over previously decoded manchester data and decode into usable tag ID
731 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
732 for( idx=0; idx<m-6; idx++) {
733 // search for a start of frame marker
734 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
735 {
736 found=1;
737 idx+=6;
738 if (found && (hi|lo)) {
739 Dbprintf("TAG ID: %x%08x (%d)",
740 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
741 /* if we're only looking for one tag */
742 if (findone)
743 {
744 *high = hi;
745 *low = lo;
746 return;
747 }
748 hi=0;
749 lo=0;
750 found=0;
751 }
752 }
753 if (found) {
754 if (dest[idx] && (!dest[idx+1]) ) {
755 hi=(hi<<1)|(lo>>31);
756 lo=(lo<<1)|0;
757 } else if ( (!dest[idx]) && dest[idx+1]) {
758 hi=(hi<<1)|(lo>>31);
759 lo=(lo<<1)|1;
760 } else {
761 found=0;
762 hi=0;
763 lo=0;
764 }
765 idx++;
766 }
767 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
768 {
769 found=1;
770 idx+=6;
771 if (found && (hi|lo)) {
772 Dbprintf("TAG ID: %x%08x (%d)",
773 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
774 /* if we're only looking for one tag */
775 if (findone)
776 {
777 *high = hi;
778 *low = lo;
779 return;
780 }
781 hi=0;
782 lo=0;
783 found=0;
784 }
785 }
786 }
787 WDT_HIT();
788 }
789}
ec09b62d 790
2d4eae76 791/*------------------------------
792 * T5555/T5557/T5567 routines
793 *------------------------------
794 */
795
796/* T55x7 configuration register definitions */
797#define T55x7_POR_DELAY 0x00000001
798#define T55x7_ST_TERMINATOR 0x00000008
799#define T55x7_PWD 0x00000010
800#define T55x7_MAXBLOCK_SHIFT 5
801#define T55x7_AOR 0x00000200
802#define T55x7_PSKCF_RF_2 0
803#define T55x7_PSKCF_RF_4 0x00000400
804#define T55x7_PSKCF_RF_8 0x00000800
805#define T55x7_MODULATION_DIRECT 0
806#define T55x7_MODULATION_PSK1 0x00001000
807#define T55x7_MODULATION_PSK2 0x00002000
808#define T55x7_MODULATION_PSK3 0x00003000
809#define T55x7_MODULATION_FSK1 0x00004000
810#define T55x7_MODULATION_FSK2 0x00005000
811#define T55x7_MODULATION_FSK1a 0x00006000
812#define T55x7_MODULATION_FSK2a 0x00007000
813#define T55x7_MODULATION_MANCHESTER 0x00008000
814#define T55x7_MODULATION_BIPHASE 0x00010000
815#define T55x7_BITRATE_RF_8 0
816#define T55x7_BITRATE_RF_16 0x00040000
817#define T55x7_BITRATE_RF_32 0x00080000
818#define T55x7_BITRATE_RF_40 0x000C0000
819#define T55x7_BITRATE_RF_50 0x00100000
820#define T55x7_BITRATE_RF_64 0x00140000
821#define T55x7_BITRATE_RF_100 0x00180000
822#define T55x7_BITRATE_RF_128 0x001C0000
823
824/* T5555 (Q5) configuration register definitions */
825#define T5555_ST_TERMINATOR 0x00000001
826#define T5555_MAXBLOCK_SHIFT 0x00000001
827#define T5555_MODULATION_MANCHESTER 0
828#define T5555_MODULATION_PSK1 0x00000010
829#define T5555_MODULATION_PSK2 0x00000020
830#define T5555_MODULATION_PSK3 0x00000030
831#define T5555_MODULATION_FSK1 0x00000040
832#define T5555_MODULATION_FSK2 0x00000050
833#define T5555_MODULATION_BIPHASE 0x00000060
834#define T5555_MODULATION_DIRECT 0x00000070
835#define T5555_INVERT_OUTPUT 0x00000080
836#define T5555_PSK_RF_2 0
837#define T5555_PSK_RF_4 0x00000100
838#define T5555_PSK_RF_8 0x00000200
839#define T5555_USE_PWD 0x00000400
840#define T5555_USE_AOR 0x00000800
841#define T5555_BITRATE_SHIFT 12
842#define T5555_FAST_WRITE 0x00004000
843#define T5555_PAGE_SELECT 0x00008000
844
845/*
846 * Relevant times in microsecond
847 * To compensate antenna falling times shorten the write times
848 * and enlarge the gap ones.
849 */
850#define START_GAP 250
851#define WRITE_GAP 160
852#define WRITE_0 144 // 192
853#define WRITE_1 400 // 432 for T55x7; 448 for E5550
854
855// Write one bit to card
856void T55xxWriteBit(int bit)
ec09b62d 857{
858 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
859 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
2d4eae76 860 if (bit == 0)
861 SpinDelayUs(WRITE_0);
862 else
863 SpinDelayUs(WRITE_1);
ec09b62d 864 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2d4eae76 865 SpinDelayUs(WRITE_GAP);
ec09b62d 866}
867
2d4eae76 868// Write one card block in page 0, no lock
869void T55xxWriteBlock(int Data, int Block)
ec09b62d 870{
2d4eae76 871 unsigned int i;
ec09b62d 872
873 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
874 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
875
876 // Give it a bit of time for the resonant antenna to settle.
877 // And for the tag to fully power up
878 SpinDelay(150);
879
2d4eae76 880 // Now start writting
ec09b62d 881 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2d4eae76 882 SpinDelayUs(START_GAP);
883
884 // Opcode
885 T55xxWriteBit(1);
886 T55xxWriteBit(0); //Page 0
887 // Lock bit
888 T55xxWriteBit(0);
889
890 // Data
891 for (i = 0x80000000; i != 0; i >>= 1)
892 T55xxWriteBit(Data & i);
893
894 // Page
895 for (i = 0x04; i != 0; i >>= 1)
896 T55xxWriteBit(Block & i);
897
898 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
899 // so wait a little more)
900 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
ec09b62d 901 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
902 SpinDelay(20);
2d4eae76 903 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
ec09b62d 904}
905
2d4eae76 906// Copy HID id to card and setup block 0 config
2414f978 907void CopyHIDtoT55x7(int hi, int lo)
ec09b62d 908{
909 int data1, data2, data3;
910
2d4eae76 911 // Ensure no more than 44 bits supplied
ec09b62d 912 if (hi>0xFFF) {
913 DbpString("Tags can only have 44 bits.");
914 return;
915 }
2d4eae76 916
917 // Build the 3 data blocks for supplied 44bit ID
918 data1 = 0x1D000000; // load preamble
919
920 for (int i=0;i<12;i++) {
921 if (hi & (1<<(11-i)))
922 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
923 else
924 data1 |= (1<<((11-i)*2)); // 0 -> 01
ec09b62d 925 }
2d4eae76 926
927 data2 = 0;
928 for (int i=0;i<16;i++) {
929 if (lo & (1<<(31-i)))
930 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
931 else
932 data2 |= (1<<((15-i)*2)); // 0 -> 01
ec09b62d 933 }
2d4eae76 934
935 data3 = 0;
936 for (int i=0;i<16;i++) {
937 if (lo & (1<<(15-i)))
938 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
939 else
940 data3 |= (1<<((15-i)*2)); // 0 -> 01
ec09b62d 941 }
942
2d4eae76 943 // Program the 3 data blocks for supplied 44bit ID
ec09b62d 944 // and the block 0 for HID format
2d4eae76 945 T55xxWriteBlock(data1,1);
946 T55xxWriteBlock(data2,2);
947 T55xxWriteBlock(data3,3);
948
949 // Config for HID (RF/50, FSK2a, Maxblock=3)
2414f978 950 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
951 T55x7_MODULATION_FSK2a |
2d4eae76 952 3 << T55x7_MAXBLOCK_SHIFT,
953 0);
ec09b62d 954
955 DbpString("DONE!");
2d4eae76 956}
ec09b62d 957
2d4eae76 958// Define 9bit header for EM410x tags
959#define EM410X_HEADER 0x1FF
960#define EM410X_ID_LENGTH 40
ec09b62d 961
2d4eae76 962void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
963{
964 int i, id_bit;
965 uint64_t id = EM410X_HEADER;
966 uint64_t rev_id = 0; // reversed ID
967 int c_parity[4]; // column parity
968 int r_parity = 0; // row parity
969
970 // Reverse ID bits given as parameter (for simpler operations)
971 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
972 if (i < 32) {
973 rev_id = (rev_id << 1) | (id_lo & 1);
974 id_lo >>= 1;
975 } else {
976 rev_id = (rev_id << 1) | (id_hi & 1);
977 id_hi >>= 1;
978 }
979 }
980
981 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
982 id_bit = rev_id & 1;
983
984 if (i % 4 == 0) {
985 // Don't write row parity bit at start of parsing
986 if (i)
987 id = (id << 1) | r_parity;
988 // Start counting parity for new row
989 r_parity = id_bit;
990 } else {
991 // Count row parity
992 r_parity ^= id_bit;
993 }
994
995 // First elements in column?
996 if (i < 4)
997 // Fill out first elements
998 c_parity[i] = id_bit;
999 else
1000 // Count column parity
1001 c_parity[i % 4] ^= id_bit;
1002
1003 // Insert ID bit
1004 id = (id << 1) | id_bit;
1005 rev_id >>= 1;
1006 }
1007
1008 // Insert parity bit of last row
1009 id = (id << 1) | r_parity;
1010
1011 // Fill out column parity at the end of tag
1012 for (i = 0; i < 4; ++i)
1013 id = (id << 1) | c_parity[i];
1014
1015 // Add stop bit
1016 id <<= 1;
1017
1018 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1019 LED_D_ON();
1020
1021 // Write EM410x ID
1022 T55xxWriteBlock((uint32_t)(id >> 32), 1);
1023 T55xxWriteBlock((uint32_t)id, 2);
1024
1025 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1026 if (card)
1027 // Writing configuration for T55x7 tag
1028 T55xxWriteBlock(T55x7_BITRATE_RF_64 |
1029 T55x7_MODULATION_MANCHESTER |
1030 2 << T55x7_MAXBLOCK_SHIFT,
1031 0);
1032 else
1033 // Writing configuration for T5555(Q5) tag
1034 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1035 T5555_MODULATION_MANCHESTER |
1036 2 << T5555_MAXBLOCK_SHIFT,
1037 0);
1038
1039 LED_D_OFF();
1040 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1041 (uint32_t)(id >> 32), (uint32_t)id);
1042}
2414f978 1043
1044// Clone Indala 64-bit tag by UID to T55x7
1045void CopyIndala64toT55x7(int hi, int lo)
1046{
1047
1048 //Program the 2 data blocks for supplied 64bit UID
1049 // and the block 0 for Indala64 format
1050 T55xxWriteBlock(hi,1);
1051 T55xxWriteBlock(lo,2);
1052 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1053 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1054 T55x7_MODULATION_PSK1 |
1055 2 << T55x7_MAXBLOCK_SHIFT,
1056 0);
1057 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1058// T5567WriteBlock(0x603E1042,0);
1059
1060 DbpString("DONE!");
1061
1062}
1063
1064void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1065{
1066
1067 //Program the 7 data blocks for supplied 224bit UID
1068 // and the block 0 for Indala224 format
1069 T55xxWriteBlock(uid1,1);
1070 T55xxWriteBlock(uid2,2);
1071 T55xxWriteBlock(uid3,3);
1072 T55xxWriteBlock(uid4,4);
1073 T55xxWriteBlock(uid5,5);
1074 T55xxWriteBlock(uid6,6);
1075 T55xxWriteBlock(uid7,7);
1076 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1077 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1078 T55x7_MODULATION_PSK1 |
1079 7 << T55x7_MAXBLOCK_SHIFT,
1080 0);
1081 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1082// T5567WriteBlock(0x603E10E2,0);
1083
1084 DbpString("DONE!");
1085
1086}
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