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Commit | Line | Data |
---|---|---|
715d74c5 | 1 | telnet_port 4444\r |
2 | gdb_port 3333\r | |
3 | \r | |
4 | interface parport\r | |
5 | parport_port 0x378\r | |
6 | parport_cable wiggler\r | |
7 | jtag_speed 0\r | |
8 | jtag_nsrst_delay 200\r | |
9 | jtag_ntrst_delay 200\r | |
10 | \r | |
11 | reset_config srst_only srst_pulls_trst\r | |
12 | \r | |
13 | jtag newtap sam7x256 cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x3f0f0f0f\r | |
14 | #jtag newtap xilinx tap -irlen 6 -ircapture 0x1 -irmask 0xf -expected-id 0x1c1a093\r | |
15 | \r | |
16 | target create sam7x256.cpu arm7tdmi -endian little -chain-position sam7x256.cpu -variant arm7tdmi\r | |
17 | sam7x256.cpu configure -event reset-init {\r | |
18 | # disable watchdog\r | |
19 | mww 0xfffffd44 0x00008000\r | |
20 | # enable user reset\r | |
21 | mww 0xfffffd08 0xa5000001\r | |
22 | # CKGR_MOR : enable the main oscillator\r | |
23 | mww 0xfffffc20 0x00000601\r | |
24 | sleep 10\r | |
25 | # CKGR_PLLR: 16 MHz * (5+1) /1 = 96Mhz\r | |
26 | mww 0xfffffc2c 0x00051c01\r | |
27 | sleep 10\r | |
28 | # PMC_MCKR : MCK = PLL / 2 = 48 MHz\r | |
29 | mww 0xfffffc30 0x00000007\r | |
30 | sleep 10\r | |
31 | # MC_FMR: flash mode (FWS=1,FMCN=60)\r | |
32 | mww 0xffffff60 0x003c0100\r | |
33 | sleep 100\r | |
34 | }\r | |
35 | \r | |
36 | gdb_memory_map enable\r | |
37 | \r | |
38 | sam7x256.cpu configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x10000 -work-area-backup 0\r | |
39 | flash bank at91sam7 0 0 0 0 0\r |