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15c4dc5a 1//-----------------------------------------------------------------------------
bd20f8f4 2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
15c4dc5a 6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10
e30c654b 11#include "proxmark3.h"
15c4dc5a 12#include "apps.h"
f7e3ed82 13#include "util.h"
15c4dc5a 14#include "hitag2.h"
15#include "crc16.h"
9ab7a6c7 16#include "string.h"
7db5f1ca 17#include "lfdemod.h"
15c4dc5a 18
b2256785
MHS		 19
20/**
21* Does the sample acquisition. If threshold is specified, the actual sampling
22* is not commenced until the threshold has been reached.
23* @param trigger_threshold - the threshold
24* @param silent - is true, now outputs are made. If false, dbprints the status
25*/
f97d4e23 26void DoAcquisition125k_internal(int trigger_threshold,bool silent)
69d88ec4 27{
c07b79fc 28 uint8_t *dest = (uint8_t *)BigBuf;
29 int n = sizeof(BigBuf);
30 int i;
31
32 memset(dest, 0, n);
33 i = 0;
34 for(;;) {
35 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
36 AT91C_BASE_SSC->SSC_THR = 0x43;
37 LED_D_ON();
38 }
39 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
40 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
41 LED_D_OFF();
42 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
43 continue;
44 else
45 trigger_threshold = -1;
46 if (++i >= n) break;
47 }
48 }
49 if(!silent)
50 {
51 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
52 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
53
54 }
69d88ec4 55}
b2256785
MHS		 56/**
57* Perform sample aquisition.
58*/
f97d4e23 59void DoAcquisition125k(int trigger_threshold)
69d88ec4 60{
c07b79fc 61 DoAcquisition125k_internal(trigger_threshold, false);
69d88ec4
MHS		 62}
63
b2256785
MHS		 64/**
65* Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
66* if not already loaded, sets divisor and starts up the antenna.
67* @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
68* 0 or 95 ==> 125 KHz
69*
70**/
b014c96d 71void LFSetupFPGAForADC(int divisor, bool lf_field)
15c4dc5a 72{
c07b79fc 73 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
74 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
75 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
76 else if (divisor == 0)
77 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
78 else
79 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
80
81 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
82
83 // Connect the A/D to the peak-detected low-frequency path.
84 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
85 // Give it a bit of time for the resonant antenna to settle.
86 SpinDelay(50);
87 // Now set up the SSC to get the ADC samples that are now streaming at us.
88 FpgaSetupSsc();
15c4dc5a 89}
b2256785
MHS		 90/**
91* Initializes the FPGA, and acquires the samples.
92**/
69d88ec4 93void AcquireRawAdcSamples125k(int divisor)
15c4dc5a 94{
c07b79fc 95 LFSetupFPGAForADC(divisor, true);
96 // Now call the acquisition routine
97 DoAcquisition125k_internal(-1,false);
b014c96d 98}
b2256785
MHS		 99/**
100* Initializes the FPGA for snoop-mode, and acquires the samples.
101**/
102
b014c96d 103void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
104{
c07b79fc 105 LFSetupFPGAForADC(divisor, false);
106 DoAcquisition125k(trigger_threshold);
15c4dc5a 107}
108
f7e3ed82 109void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
15c4dc5a 110{
15c4dc5a 111
c07b79fc 112 /* Make sure the tag is reset */
113 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
115 SpinDelay(2500);
e30c654b 116
b2256785 117
c07b79fc 118 int divisor_used = 95; // 125 KHz
119 // see if 'h' was specified
b2256785 120
c07b79fc 121 if (command[strlen((char *) command) - 1] == 'h')
122 divisor_used = 88; // 134.8 KHz
15c4dc5a 123
15c4dc5a 124
c07b79fc 125 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
126 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
127 // Give it a bit of time for the resonant antenna to settle.
128 SpinDelay(50);
b2256785 129
c07b79fc 130 // And a little more time for the tag to fully power up
131 SpinDelay(2000);
15c4dc5a 132
c07b79fc 133 // Now set up the SSC to get the ADC samples that are now streaming at us.
134 FpgaSetupSsc();
15c4dc5a 135
c07b79fc 136 // now modulate the reader field
137 while(*command != '\0' && *command != ' ') {
138 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
139 LED_D_OFF();
140 SpinDelayUs(delay_off);
141 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
15c4dc5a 142
c07b79fc 143 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
144 LED_D_ON();
145 if(*(command++) == '0')
146 SpinDelayUs(period_0);
147 else
148 SpinDelayUs(period_1);
149 }
150 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
151 LED_D_OFF();
152 SpinDelayUs(delay_off);
153 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
15c4dc5a 154
c07b79fc 155 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
15c4dc5a 156
c07b79fc 157 // now do the read
158 DoAcquisition125k(-1);
15c4dc5a 159}
160
161/* blank r/w tag data stream
162...0000000000000000 01111111
1631010101010101010101010101010101010101010101010101010101010101010
1640011010010100001
16501111111
166101010101010101[0]000...
167
168[5555fe852c5555555555555555fe0000]
169*/
170void ReadTItag(void)
171{
c07b79fc 172 // some hardcoded initial params
173 // when we read a TI tag we sample the zerocross line at 2Mhz
174 // TI tags modulate a 1 as 16 cycles of 123.2Khz
175 // TI tags modulate a 0 as 16 cycles of 134.2Khz
176#define FSAMPLE 2000000
177#define FREQLO 123200
178#define FREQHI 134200
179
180 signed char *dest = (signed char *)BigBuf;
181 int n = sizeof(BigBuf);
182 // int *dest = GraphBuffer;
183 // int n = GraphTraceLen;
184
185 // 128 bit shift register [shift3:shift2:shift1:shift0]
186 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
187
188 int i, cycles=0, samples=0;
189 // how many sample points fit in 16 cycles of each frequency
190 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
191 // when to tell if we're close enough to one freq or another
192 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
193
194 // TI tags charge at 134.2Khz
195 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
196 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
197
198 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
199 // connects to SSP_DIN and the SSP_DOUT logic level controls
200 // whether we're modulating the antenna (high)
201 // or listening to the antenna (low)
202 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
203
204 // get TI tag data into the buffer
205 AcquireTiType();
206
207 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
208
209 for (i=0; i<n-1; i++) {
210 // count cycles by looking for lo to hi zero crossings
211 if ( (dest[i]<0) && (dest[i+1]>0) ) {
212 cycles++;
213 // after 16 cycles, measure the frequency
214 if (cycles>15) {
215 cycles=0;
216 samples=i-samples; // number of samples in these 16 cycles
217
218 // TI bits are coming to us lsb first so shift them
219 // right through our 128 bit right shift register
220 shift0 = (shift0>>1) | (shift1 << 31);
221 shift1 = (shift1>>1) | (shift2 << 31);
222 shift2 = (shift2>>1) | (shift3 << 31);
223 shift3 >>= 1;
224
225 // check if the cycles fall close to the number
226 // expected for either the low or high frequency
227 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
228 // low frequency represents a 1
229 shift3 |= (1<<31);
230 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
231 // high frequency represents a 0
232 } else {
233 // probably detected a gay waveform or noise
234 // use this as gaydar or discard shift register and start again
235 shift3 = shift2 = shift1 = shift0 = 0;
236 }
237 samples = i;
238
239 // for each bit we receive, test if we've detected a valid tag
240
241 // if we see 17 zeroes followed by 6 ones, we might have a tag
242 // remember the bits are backwards
243 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
244 // if start and end bytes match, we have a tag so break out of the loop
245 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
246 cycles = 0xF0B; //use this as a flag (ugly but whatever)
247 break;
248 }
249 }
250 }
251 }
252 }
253
254 // if flag is set we have a tag
255 if (cycles!=0xF0B) {
256 DbpString("Info: No valid tag detected.");
257 } else {
258 // put 64 bit data into shift1 and shift0
259 shift0 = (shift0>>24) | (shift1 << 8);
260 shift1 = (shift1>>24) | (shift2 << 8);
261
262 // align 16 bit crc into lower half of shift2
263 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
264
265 // if r/w tag, check ident match
266 if ( shift3&(1<<15) ) {
267 DbpString("Info: TI tag is rewriteable");
268 // only 15 bits compare, last bit of ident is not valid
269 if ( ((shift3>>16)^shift0)&0x7fff ) {
270 DbpString("Error: Ident mismatch!");
271 } else {
272 DbpString("Info: TI tag ident is valid");
273 }
274 } else {
275 DbpString("Info: TI tag is readonly");
276 }
277
278 // WARNING the order of the bytes in which we calc crc below needs checking
279 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
280 // bytes in reverse or something
281 // calculate CRC
282 uint32_t crc=0;
283
284 crc = update_crc16(crc, (shift0)&0xff);
285 crc = update_crc16(crc, (shift0>>8)&0xff);
286 crc = update_crc16(crc, (shift0>>16)&0xff);
287 crc = update_crc16(crc, (shift0>>24)&0xff);
288 crc = update_crc16(crc, (shift1)&0xff);
289 crc = update_crc16(crc, (shift1>>8)&0xff);
290 crc = update_crc16(crc, (shift1>>16)&0xff);
291 crc = update_crc16(crc, (shift1>>24)&0xff);
292
293 Dbprintf("Info: Tag data: %x%08x, crc=%x",
294 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
295 if (crc != (shift2&0xffff)) {
296 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
297 } else {
298 DbpString("Info: CRC is good");
299 }
300 }
15c4dc5a 301}
302
f7e3ed82 303void WriteTIbyte(uint8_t b)
15c4dc5a 304{
c07b79fc 305 int i = 0;
306
307 // modulate 8 bits out to the antenna
308 for (i=0; i<8; i++)
309 {
310 if (b&(1<<i)) {
311 // stop modulating antenna
312 LOW(GPIO_SSC_DOUT);
313 SpinDelayUs(1000);
314 // modulate antenna
315 HIGH(GPIO_SSC_DOUT);
316 SpinDelayUs(1000);
317 } else {
318 // stop modulating antenna
319 LOW(GPIO_SSC_DOUT);
320 SpinDelayUs(300);
321 // modulate antenna
322 HIGH(GPIO_SSC_DOUT);
323 SpinDelayUs(1700);
324 }
325 }
15c4dc5a 326}
327
328void AcquireTiType(void)
329{
c07b79fc 330 int i, j, n;
331 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
332 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
333#define TIBUFLEN 1250
334
335 // clear buffer
336 memset(BigBuf,0,sizeof(BigBuf));
337
338 // Set up the synchronous serial port
339 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
340 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
341
342 // steal this pin from the SSP and use it to control the modulation
343 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
344 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
345
346 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
347 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
348
349 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
350 // 48/2 = 24 MHz clock must be divided by 12
351 AT91C_BASE_SSC->SSC_CMR = 12;
352
353 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
354 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
355 AT91C_BASE_SSC->SSC_TCMR = 0;
356 AT91C_BASE_SSC->SSC_TFMR = 0;
357
358 LED_D_ON();
359
360 // modulate antenna
361 HIGH(GPIO_SSC_DOUT);
362
363 // Charge TI tag for 50ms.
364 SpinDelay(50);
365
366 // stop modulating antenna and listen
367 LOW(GPIO_SSC_DOUT);
368
369 LED_D_OFF();
370
371 i = 0;
372 for(;;) {
373 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
374 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
375 i++; if(i >= TIBUFLEN) break;
376 }
377 WDT_HIT();
378 }
379
380 // return stolen pin to SSP
381 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
382 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
383
384 char *dest = (char *)BigBuf;
385 n = TIBUFLEN*32;
386 // unpack buffer
387 for (i=TIBUFLEN-1; i>=0; i--) {
388 for (j=0; j<32; j++) {
389 if(BigBuf[i] & (1 << j)) {
390 dest[--n] = 1;
391 } else {
392 dest[--n] = -1;
393 }
394 }
395 }
15c4dc5a 396}
397
398// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
399// if crc provided, it will be written with the data verbatim (even if bogus)
400// if not provided a valid crc will be computed from the data and written.
f7e3ed82 401void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
15c4dc5a 402{
c07b79fc 403 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
404 if(crc == 0) {
405 crc = update_crc16(crc, (idlo)&0xff);
406 crc = update_crc16(crc, (idlo>>8)&0xff);
407 crc = update_crc16(crc, (idlo>>16)&0xff);
408 crc = update_crc16(crc, (idlo>>24)&0xff);
409 crc = update_crc16(crc, (idhi)&0xff);
410 crc = update_crc16(crc, (idhi>>8)&0xff);
411 crc = update_crc16(crc, (idhi>>16)&0xff);
412 crc = update_crc16(crc, (idhi>>24)&0xff);
413 }
414 Dbprintf("Writing to tag: %x%08x, crc=%x",
415 (unsigned int) idhi, (unsigned int) idlo, crc);
416
417 // TI tags charge at 134.2Khz
418 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
419 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
420 // connects to SSP_DIN and the SSP_DOUT logic level controls
421 // whether we're modulating the antenna (high)
422 // or listening to the antenna (low)
423 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
424 LED_A_ON();
425
426 // steal this pin from the SSP and use it to control the modulation
427 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
428 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
429
430 // writing algorithm:
431 // a high bit consists of a field off for 1ms and field on for 1ms
432 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
433 // initiate a charge time of 50ms (field on) then immediately start writing bits
434 // start by writing 0xBB (keyword) and 0xEB (password)
435 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
436 // finally end with 0x0300 (write frame)
437 // all data is sent lsb firts
438 // finish with 15ms programming time
439
440 // modulate antenna
441 HIGH(GPIO_SSC_DOUT);
442 SpinDelay(50); // charge time
443
444 WriteTIbyte(0xbb); // keyword
445 WriteTIbyte(0xeb); // password
446 WriteTIbyte( (idlo )&0xff );
447 WriteTIbyte( (idlo>>8 )&0xff );
448 WriteTIbyte( (idlo>>16)&0xff );
449 WriteTIbyte( (idlo>>24)&0xff );
450 WriteTIbyte( (idhi )&0xff );
451 WriteTIbyte( (idhi>>8 )&0xff );
452 WriteTIbyte( (idhi>>16)&0xff );
453 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
454 WriteTIbyte( (crc )&0xff ); // crc lo
455 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
456 WriteTIbyte(0x00); // write frame lo
457 WriteTIbyte(0x03); // write frame hi
458 HIGH(GPIO_SSC_DOUT);
459 SpinDelay(50); // programming time
460
461 LED_A_OFF();
462
463 // get TI tag data into the buffer
464 AcquireTiType();
465
466 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
467 DbpString("Now use tiread to check");
15c4dc5a 468}
469
470void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
471{
c07b79fc 472 int i;
473 uint8_t *tab = (uint8_t *)BigBuf;
d19929cb 474
c07b79fc 475 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
476 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
d19929cb 477
c07b79fc 478 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
d19929cb 479
c07b79fc 480 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
481 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
d19929cb 482
15c4dc5a 483#define SHORT_COIL() LOW(GPIO_SSC_DOUT)
484#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
d19929cb 485
c07b79fc 486 i = 0;
487 for(;;) {
488 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
489 if(BUTTON_PRESS()) {
490 DbpString("Stopped");
491 return;
492 }
493 WDT_HIT();
494 }
d19929cb 495
c07b79fc 496 if (ledcontrol)
497 LED_D_ON();
d19929cb 498
c07b79fc 499 if(tab[i])
500 OPEN_COIL();
501 else
502 SHORT_COIL();
d19929cb 503
c07b79fc 504 if (ledcontrol)
505 LED_D_OFF();
d19929cb 506
c07b79fc 507 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
508 if(BUTTON_PRESS()) {
509 DbpString("Stopped");
510 return;
511 }
512 WDT_HIT();
513 }
d19929cb 514
c07b79fc 515 i++;
516 if(i == period) {
517 i = 0;
518 if (gap) {
519 SHORT_COIL();
520 SpinDelayUs(gap);
521 }
522 }
523 }
15c4dc5a 524}
525
15c4dc5a 526#define DEBUG_FRAME_CONTENTS 1
527void SimulateTagLowFrequencyBidir(int divisor, int t0)
528{
15c4dc5a 529}
530
531// compose fc/8 fc/10 waveform
532static void fc(int c, int *n) {
c07b79fc 533 uint8_t *dest = (uint8_t *)BigBuf;
534 int idx;
535
536 // for when we want an fc8 pattern every 4 logical bits
537 if(c==0) {
538 dest[((*n)++)]=1;
539 dest[((*n)++)]=1;
540 dest[((*n)++)]=0;
541 dest[((*n)++)]=0;
542 dest[((*n)++)]=0;
543 dest[((*n)++)]=0;
544 dest[((*n)++)]=0;
545 dest[((*n)++)]=0;
546 }
547 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
548 if(c==8) {
549 for (idx=0; idx<6; idx++) {
550 dest[((*n)++)]=1;
551 dest[((*n)++)]=1;
552 dest[((*n)++)]=0;
553 dest[((*n)++)]=0;
554 dest[((*n)++)]=0;
555 dest[((*n)++)]=0;
556 dest[((*n)++)]=0;
557 dest[((*n)++)]=0;
558 }
559 }
560
561 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
562 if(c==10) {
563 for (idx=0; idx<5; idx++) {
564 dest[((*n)++)]=1;
565 dest[((*n)++)]=1;
566 dest[((*n)++)]=1;
567 dest[((*n)++)]=0;
568 dest[((*n)++)]=0;
569 dest[((*n)++)]=0;
570 dest[((*n)++)]=0;
571 dest[((*n)++)]=0;
572 dest[((*n)++)]=0;
573 dest[((*n)++)]=0;
574 }
575 }
15c4dc5a 576}
577
578// prepare a waveform pattern in the buffer based on the ID given then
579// simulate a HID tag until the button is pressed
580void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
581{
c07b79fc 582 int n=0, i=0;
583 /*
584 HID tag bitstream format
585 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
586 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
587 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
588 A fc8 is inserted before every 4 bits
589 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
590 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
591 */
592
593 if (hi>0xFFF) {
594 DbpString("Tags can only have 44 bits.");
595 return;
596 }
597 fc(0,&n);
598 // special start of frame marker containing invalid bit sequences
599 fc(8, &n); fc(8, &n); // invalid
600 fc(8, &n); fc(10, &n); // logical 0
601 fc(10, &n); fc(10, &n); // invalid
602 fc(8, &n); fc(10, &n); // logical 0
603
604 WDT_HIT();
605 // manchester encode bits 43 to 32
606 for (i=11; i>=0; i--) {
607 if ((i%4)==3) fc(0,&n);
608 if ((hi>>i)&1) {
609 fc(10, &n); fc(8, &n); // low-high transition
610 } else {
611 fc(8, &n); fc(10, &n); // high-low transition
612 }
613 }
614
615 WDT_HIT();
616 // manchester encode bits 31 to 0
617 for (i=31; i>=0; i--) {
618 if ((i%4)==3) fc(0,&n);
619 if ((lo>>i)&1) {
620 fc(10, &n); fc(8, &n); // low-high transition
621 } else {
622 fc(8, &n); fc(10, &n); // high-low transition
623 }
624 }
625
626 if (ledcontrol)
627 LED_A_ON();
628 SimulateTagLowFrequency(n, 0, ledcontrol);
629
630 if (ledcontrol)
631 LED_A_OFF();
15c4dc5a 632}
eb191de6 633
b3b70669 634// loop to get raw HID waveform then FSK demodulate the TAG ID from it
69d88ec4
MHS		 635void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
636{
c07b79fc 637 uint8_t *dest = (uint8_t *)BigBuf;
638
639 size_t size=0; //, found=0;
640 uint32_t hi2=0, hi=0, lo=0;
641
642 // Configure to go in 125Khz listen mode
643 LFSetupFPGAForADC(95, true);
644
645 while(!BUTTON_PRESS()) {
646
647 WDT_HIT();
648 if (ledcontrol) LED_A_ON();
649
650 DoAcquisition125k_internal(-1,true);
651 size = sizeof(BigBuf);
652 if (size < 2000) continue;
653 // FSK demodulator
654
655 int bitLen = HIDdemodFSK(dest,size,&hi2,&hi,&lo);
656
657 WDT_HIT();
658
659 if (bitLen>0 && lo>0){
660 // final loop, go over previously decoded manchester data and decode into usable tag ID
661 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
662 if (hi2 != 0){ //extra large HID tags
663 Dbprintf("TAG ID: %x%08x%08x (%d)",
664 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
665 }else { //standard HID tags <38 bits
666 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
667 uint8_t bitlen = 0;
668 uint32_t fc = 0;
669 uint32_t cardnum = 0;
670 if (((hi>>5)&1)==1){//if bit 38 is set then < 37 bit format is used
671 uint32_t lo2=0;
672 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
673 uint8_t idx3 = 1;
674 while(lo2>1){ //find last bit set to 1 (format len bit)
675 lo2=lo2>>1;
676 idx3++;
677 }
678 bitlen =idx3+19;
679 fc =0;
680 cardnum=0;
681 if(bitlen==26){
682 cardnum = (lo>>1)&0xFFFF;
683 fc = (lo>>17)&0xFF;
684 }
685 if(bitlen==37){
686 cardnum = (lo>>1)&0x7FFFF;
687 fc = ((hi&0xF)<<12)|(lo>>20);
688 }
689 if(bitlen==34){
690 cardnum = (lo>>1)&0xFFFF;
691 fc= ((hi&1)<<15)|(lo>>17);
692 }
693 if(bitlen==35){
694 cardnum = (lo>>1)&0xFFFFF;
695 fc = ((hi&1)<<11)|(lo>>21);
696 }
697 }
698 else { //if bit 38 is not set then 37 bit format is used
699 bitlen= 37;
700 fc =0;
701 cardnum=0;
702 if(bitlen==37){
703 cardnum = (lo>>1)&0x7FFFF;
704 fc = ((hi&0xF)<<12)|(lo>>20);
705 }
706 }
707 //Dbprintf("TAG ID: %x%08x (%d)",
708 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
709 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
710 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
711 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
712 }
713 if (findone){
714 if (ledcontrol) LED_A_OFF();
715 return;
716 }
717 // reset
718 hi2 = hi = lo = 0;
719 }
720 WDT_HIT();
721 //SpinDelay(50);
722 }
723 DbpString("Stopped");
724 if (ledcontrol) LED_A_OFF();
eb191de6 725}
726
66707a3b 727void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
eb191de6 728{
c07b79fc 729 uint8_t *dest = (uint8_t *)BigBuf;
730
731 size_t size=0; //, found=0;
732 uint32_t bitLen=0;
733 int clk=0, invert=0, errCnt=0;
734 uint64_t lo=0;
735 // Configure to go in 125Khz listen mode
736 LFSetupFPGAForADC(95, true);
737
738 while(!BUTTON_PRESS()) {
739
740 WDT_HIT();
741 if (ledcontrol) LED_A_ON();
742
743 DoAcquisition125k_internal(-1,true);
744 size = sizeof(BigBuf);
745 if (size < 2000) continue;
746 // FSK demodulator
747 //int askmandemod(uint8_t *BinStream,uint32_t *BitLen,int *clk, int *invert);
748 bitLen=size;
749 //Dbprintf("DEBUG: Buffer got");
750 errCnt = askmandemod(dest,&bitLen,&clk,&invert); //HIDdemodFSK(dest,size,&hi2,&hi,&lo);
751 //Dbprintf("DEBUG: ASK Got");
752 WDT_HIT();
753
754 if (errCnt>=0){
755 lo = Em410xDecode(dest,bitLen);
756 //Dbprintf("DEBUG: EM GOT");
757 //printEM410x(lo);
758 if (lo>0){
759 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",(uint32_t)(lo>>32),(uint32_t)lo,(uint32_t)(lo&0xFFFF),(uint32_t)((lo>>16LL) & 0xFF),(uint32_t)(lo & 0xFFFFFF));
760 }
761 if (findone){
762 if (ledcontrol) LED_A_OFF();
763 return;
764 }
765 } else{
766 //Dbprintf("DEBUG: No Tag");
767 }
768 WDT_HIT();
769 lo = 0;
770 clk=0;
771 invert=0;
772 errCnt=0;
773 size=0;
774 //SpinDelay(50);
775 }
776 DbpString("Stopped");
777 if (ledcontrol) LED_A_OFF();
15c4dc5a 778}
69d88ec4 779
a1f3bb12 780void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
eb191de6 781{
c07b79fc 782 uint8_t *dest = (uint8_t *)BigBuf;
783 int idx=0;
784 uint32_t code=0, code2=0;
785 uint8_t version=0;
786 uint8_t facilitycode=0;
787 uint16_t number=0;
788 // Configure to go in 125Khz listen mode
789 LFSetupFPGAForADC(95, true);
790
791 while(!BUTTON_PRESS()) {
792 WDT_HIT();
793 if (ledcontrol) LED_A_ON();
794 DoAcquisition125k_internal(-1,true);
795 //fskdemod and get start index
796 WDT_HIT();
797 idx = IOdemodFSK(dest,sizeof(BigBuf));
798 if (idx>0){
799 //valid tag found
800
801 //Index map
802 //0 10 20 30 40 50 60
803 //| | | | | | |
804 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
805 //-----------------------------------------------------------------------------
806 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
807 //
808 //XSF(version)facility:codeone+codetwo
809 //Handle the data
810 if(findone){ //only print binary if we are doing one
811 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
812 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
813 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
814 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
815 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
816 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
817 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
818 }
819 code = bytebits_to_byte(dest+idx,32);
820 code2 = bytebits_to_byte(dest+idx+32,32);
821 version = bytebits_to_byte(dest+idx+27,8); //14,4
822 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
823 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
824
825 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
826 // if we're only looking for one tag
827 if (findone){
828 if (ledcontrol) LED_A_OFF();
829 //LED_A_OFF();
830 return;
831 }
832 code=code2=0;
833 version=facilitycode=0;
834 number=0;
835 idx=0;
836 }
837 WDT_HIT();
838 }
839 DbpString("Stopped");
840 if (ledcontrol) LED_A_OFF();
eb191de6 841}
a1f3bb12 842
2d4eae76 843/*------------------------------
844 * T5555/T5557/T5567 routines
845 *------------------------------
846 */
847
848/* T55x7 configuration register definitions */
849#define T55x7_POR_DELAY 0x00000001
850#define T55x7_ST_TERMINATOR 0x00000008
851#define T55x7_PWD 0x00000010
852#define T55x7_MAXBLOCK_SHIFT 5
853#define T55x7_AOR 0x00000200
854#define T55x7_PSKCF_RF_2 0
855#define T55x7_PSKCF_RF_4 0x00000400
856#define T55x7_PSKCF_RF_8 0x00000800
857#define T55x7_MODULATION_DIRECT 0
858#define T55x7_MODULATION_PSK1 0x00001000
859#define T55x7_MODULATION_PSK2 0x00002000
860#define T55x7_MODULATION_PSK3 0x00003000
861#define T55x7_MODULATION_FSK1 0x00004000
862#define T55x7_MODULATION_FSK2 0x00005000
863#define T55x7_MODULATION_FSK1a 0x00006000
864#define T55x7_MODULATION_FSK2a 0x00007000
865#define T55x7_MODULATION_MANCHESTER 0x00008000
866#define T55x7_MODULATION_BIPHASE 0x00010000
867#define T55x7_BITRATE_RF_8 0
868#define T55x7_BITRATE_RF_16 0x00040000
869#define T55x7_BITRATE_RF_32 0x00080000
870#define T55x7_BITRATE_RF_40 0x000C0000
871#define T55x7_BITRATE_RF_50 0x00100000
872#define T55x7_BITRATE_RF_64 0x00140000
873#define T55x7_BITRATE_RF_100 0x00180000
874#define T55x7_BITRATE_RF_128 0x001C0000
875
876/* T5555 (Q5) configuration register definitions */
877#define T5555_ST_TERMINATOR 0x00000001
878#define T5555_MAXBLOCK_SHIFT 0x00000001
879#define T5555_MODULATION_MANCHESTER 0
880#define T5555_MODULATION_PSK1 0x00000010
881#define T5555_MODULATION_PSK2 0x00000020
882#define T5555_MODULATION_PSK3 0x00000030
883#define T5555_MODULATION_FSK1 0x00000040
884#define T5555_MODULATION_FSK2 0x00000050
885#define T5555_MODULATION_BIPHASE 0x00000060
886#define T5555_MODULATION_DIRECT 0x00000070
887#define T5555_INVERT_OUTPUT 0x00000080
888#define T5555_PSK_RF_2 0
889#define T5555_PSK_RF_4 0x00000100
890#define T5555_PSK_RF_8 0x00000200
891#define T5555_USE_PWD 0x00000400
892#define T5555_USE_AOR 0x00000800
893#define T5555_BITRATE_SHIFT 12
894#define T5555_FAST_WRITE 0x00004000
895#define T5555_PAGE_SELECT 0x00008000
896
897/*
898 * Relevant times in microsecond
899 * To compensate antenna falling times shorten the write times
900 * and enlarge the gap ones.
901 */
902#define START_GAP 250
903#define WRITE_GAP 160
904#define WRITE_0 144 // 192
905#define WRITE_1 400 // 432 for T55x7; 448 for E5550
906
907// Write one bit to card
908void T55xxWriteBit(int bit)
ec09b62d 909{
c07b79fc 910 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
911 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
912 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
913 if (bit == 0)
914 SpinDelayUs(WRITE_0);
915 else
916 SpinDelayUs(WRITE_1);
917 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
918 SpinDelayUs(WRITE_GAP);
ec09b62d 919}
920
2d4eae76 921// Write one card block in page 0, no lock
54a942b0 922void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
ec09b62d 923{
c07b79fc 924 //unsigned int i; //enio adjustment 12/10/14
925 uint32_t i;
926
927 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
928 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
929 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
930
931 // Give it a bit of time for the resonant antenna to settle.
932 // And for the tag to fully power up
933 SpinDelay(150);
934
935 // Now start writting
936 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
937 SpinDelayUs(START_GAP);
938
939 // Opcode
940 T55xxWriteBit(1);
941 T55xxWriteBit(0); //Page 0
942 if (PwdMode == 1){
943 // Pwd
944 for (i = 0x80000000; i != 0; i >>= 1)
945 T55xxWriteBit(Pwd & i);
946 }
947 // Lock bit
948 T55xxWriteBit(0);
949
950 // Data
54a942b0 951 for (i = 0x80000000; i != 0; i >>= 1)
c07b79fc 952 T55xxWriteBit(Data & i);
953
954 // Block
955 for (i = 0x04; i != 0; i >>= 1)
956 T55xxWriteBit(Block & i);
957
958 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
959 // so wait a little more)
960 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
961 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
962 SpinDelay(20);
963 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
ec09b62d 964}
965
54a942b0 966// Read one card block in page 0
967void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
ec09b62d 968{
c07b79fc 969 uint8_t *dest = (uint8_t *)BigBuf;
970 //int m=0, i=0; //enio adjustment 12/10/14
971 uint32_t m=0, i=0;
972 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
973 m = sizeof(BigBuf);
974 // Clear destination buffer before sending the command
975 memset(dest, 128, m);
976 // Connect the A/D to the peak-detected low-frequency path.
977 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
978 // Now set up the SSC to get the ADC samples that are now streaming at us.
979 FpgaSetupSsc();
980
981 LED_D_ON();
982 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
983 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
984
985 // Give it a bit of time for the resonant antenna to settle.
986 // And for the tag to fully power up
987 SpinDelay(150);
988
989 // Now start writting
990 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
991 SpinDelayUs(START_GAP);
992
993 // Opcode
994 T55xxWriteBit(1);
995 T55xxWriteBit(0); //Page 0
996 if (PwdMode == 1){
997 // Pwd
998 for (i = 0x80000000; i != 0; i >>= 1)
999 T55xxWriteBit(Pwd & i);
1000 }
1001 // Lock bit
1002 T55xxWriteBit(0);
1003 // Block
1004 for (i = 0x04; i != 0; i >>= 1)
1005 T55xxWriteBit(Block & i);
1006
1007 // Turn field on to read the response
1008 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1009 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1010
1011 // Now do the acquisition
1012 i = 0;
1013 for(;;) {
1014 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1015 AT91C_BASE_SSC->SSC_THR = 0x43;
1016 }
1017 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1018 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1019 // we don't care about actual value, only if it's more or less than a
1020 // threshold essentially we capture zero crossings for later analysis
1021 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1022 i++;
1023 if (i >= m) break;
1024 }
1025 }
1026
1027 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1028 LED_D_OFF();
1029 DbpString("DONE!");
54a942b0 1030}
2d4eae76 1031
54a942b0 1032// Read card traceability data (page 1)
1033void T55xxReadTrace(void){
c07b79fc 1034 uint8_t *dest = (uint8_t *)BigBuf;
1035 int m=0, i=0;
1036
1037 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1038 m = sizeof(BigBuf);
1039 // Clear destination buffer before sending the command
1040 memset(dest, 128, m);
1041 // Connect the A/D to the peak-detected low-frequency path.
1042 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1043 // Now set up the SSC to get the ADC samples that are now streaming at us.
1044 FpgaSetupSsc();
1045
1046 LED_D_ON();
1047 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1048 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1049
1050 // Give it a bit of time for the resonant antenna to settle.
1051 // And for the tag to fully power up
1052 SpinDelay(150);
1053
1054 // Now start writting
1055 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1056 SpinDelayUs(START_GAP);
1057
1058 // Opcode
1059 T55xxWriteBit(1);
1060 T55xxWriteBit(1); //Page 1
1061
1062 // Turn field on to read the response
1063 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1064 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1065
1066 // Now do the acquisition
1067 i = 0;
1068 for(;;) {
1069 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1070 AT91C_BASE_SSC->SSC_THR = 0x43;
1071 }
1072 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1073 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1074 i++;
1075 if (i >= m) break;
1076 }
1077 }
1078
1079 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1080 LED_D_OFF();
1081 DbpString("DONE!");
54a942b0 1082}
ec09b62d 1083
54a942b0 1084/*-------------- Cloning routines -----------*/
1085// Copy HID id to card and setup block 0 config
1086void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1087{
c07b79fc 1088 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1089 int last_block = 0;
1090
1091 if (longFMT){
1092 // Ensure no more than 84 bits supplied
1093 if (hi2>0xFFFFF) {
1094 DbpString("Tags can only have 84 bits.");
1095 return;
1096 }
1097 // Build the 6 data blocks for supplied 84bit ID
1098 last_block = 6;
1099 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1100 for (int i=0;i<4;i++) {
1101 if (hi2 & (1<<(19-i)))
1102 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1103 else
1104 data1 |= (1<<((3-i)*2)); // 0 -> 01
1105 }
1106
1107 data2 = 0;
1108 for (int i=0;i<16;i++) {
1109 if (hi2 & (1<<(15-i)))
1110 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1111 else
1112 data2 |= (1<<((15-i)*2)); // 0 -> 01
1113 }
1114
1115 data3 = 0;
1116 for (int i=0;i<16;i++) {
1117 if (hi & (1<<(31-i)))
1118 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1119 else
1120 data3 |= (1<<((15-i)*2)); // 0 -> 01
1121 }
1122
1123 data4 = 0;
1124 for (int i=0;i<16;i++) {
1125 if (hi & (1<<(15-i)))
1126 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1127 else
1128 data4 |= (1<<((15-i)*2)); // 0 -> 01
1129 }
1130
1131 data5 = 0;
1132 for (int i=0;i<16;i++) {
1133 if (lo & (1<<(31-i)))
1134 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1135 else
1136 data5 |= (1<<((15-i)*2)); // 0 -> 01
1137 }
1138
1139 data6 = 0;
1140 for (int i=0;i<16;i++) {
1141 if (lo & (1<<(15-i)))
1142 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1143 else
1144 data6 |= (1<<((15-i)*2)); // 0 -> 01
1145 }
54a942b0 1146 }
c07b79fc 1147 else {
1148 // Ensure no more than 44 bits supplied
1149 if (hi>0xFFF) {
1150 DbpString("Tags can only have 44 bits.");
1151 return;
1152 }
1153
1154 // Build the 3 data blocks for supplied 44bit ID
1155 last_block = 3;
1156
1157 data1 = 0x1D000000; // load preamble
1158
1159 for (int i=0;i<12;i++) {
1160 if (hi & (1<<(11-i)))
1161 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1162 else
1163 data1 |= (1<<((11-i)*2)); // 0 -> 01
1164 }
1165
1166 data2 = 0;
1167 for (int i=0;i<16;i++) {
1168 if (lo & (1<<(31-i)))
1169 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1170 else
1171 data2 |= (1<<((15-i)*2)); // 0 -> 01
1172 }
1173
1174 data3 = 0;
1175 for (int i=0;i<16;i++) {
1176 if (lo & (1<<(15-i)))
1177 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1178 else
1179 data3 |= (1<<((15-i)*2)); // 0 -> 01
1180 }
54a942b0 1181 }
c07b79fc 1182
1183 LED_D_ON();
1184 // Program the data blocks for supplied ID
1185 // and the block 0 for HID format
1186 T55xxWriteBlock(data1,1,0,0);
1187 T55xxWriteBlock(data2,2,0,0);
1188 T55xxWriteBlock(data3,3,0,0);
1189
1190 if (longFMT) { // if long format there are 6 blocks
1191 T55xxWriteBlock(data4,4,0,0);
1192 T55xxWriteBlock(data5,5,0,0);
1193 T55xxWriteBlock(data6,6,0,0);
4118b74d 1194 }
c07b79fc 1195
1196 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1197 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1198 T55x7_MODULATION_FSK2a |
1199 last_block << T55x7_MAXBLOCK_SHIFT,
1200 0,0,0);
1201
1202 LED_D_OFF();
1203
1204 DbpString("DONE!");
2d4eae76 1205}
ec09b62d 1206
a1f3bb12 1207void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1208{
c07b79fc 1209 int data1=0, data2=0; //up to six blocks for long format
1210
a1f3bb12 1211 data1 = hi; // load preamble
1212 data2 = lo;
1213
1214 LED_D_ON();
1215 // Program the data blocks for supplied ID
1216 // and the block 0 for HID format
1217 T55xxWriteBlock(data1,1,0,0);
1218 T55xxWriteBlock(data2,2,0,0);
c07b79fc 1219
a1f3bb12 1220 //Config Block
1221 T55xxWriteBlock(0x00147040,0,0,0);
1222 LED_D_OFF();
c07b79fc 1223
a1f3bb12 1224 DbpString("DONE!");
1225}
1226
2d4eae76 1227// Define 9bit header for EM410x tags
1228#define EM410X_HEADER 0x1FF
1229#define EM410X_ID_LENGTH 40
ec09b62d 1230
2d4eae76 1231void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1232{
c07b79fc 1233 int i, id_bit;
1234 uint64_t id = EM410X_HEADER;
1235 uint64_t rev_id = 0; // reversed ID
1236 int c_parity[4]; // column parity
1237 int r_parity = 0; // row parity
1238 uint32_t clock = 0;
1239
1240 // Reverse ID bits given as parameter (for simpler operations)
1241 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1242 if (i < 32) {
1243 rev_id = (rev_id << 1) | (id_lo & 1);
1244 id_lo >>= 1;
1245 } else {
1246 rev_id = (rev_id << 1) | (id_hi & 1);
1247 id_hi >>= 1;
1248 }
1249 }
1250
1251 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1252 id_bit = rev_id & 1;
1253
1254 if (i % 4 == 0) {
1255 // Don't write row parity bit at start of parsing
1256 if (i)
1257 id = (id << 1) | r_parity;
1258 // Start counting parity for new row
1259 r_parity = id_bit;
1260 } else {
1261 // Count row parity
1262 r_parity ^= id_bit;
1263 }
1264
1265 // First elements in column?
1266 if (i < 4)
1267 // Fill out first elements
1268 c_parity[i] = id_bit;
1269 else
1270 // Count column parity
1271 c_parity[i % 4] ^= id_bit;
1272
1273 // Insert ID bit
1274 id = (id << 1) | id_bit;
1275 rev_id >>= 1;
1276 }
1277
1278 // Insert parity bit of last row
1279 id = (id << 1) | r_parity;
1280
1281 // Fill out column parity at the end of tag
1282 for (i = 0; i < 4; ++i)
1283 id = (id << 1) | c_parity[i];
1284
1285 // Add stop bit
1286 id <<= 1;
1287
1288 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1289 LED_D_ON();
1290
1291 // Write EM410x ID
1292 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1293 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1294
1295 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1296 if (card) {
1297 // Clock rate is stored in bits 8-15 of the card value
1298 clock = (card & 0xFF00) >> 8;
1299 Dbprintf("Clock rate: %d", clock);
1300 switch (clock)
1301 {
1302 case 32:
1303 clock = T55x7_BITRATE_RF_32;
1304 break;
1305 case 16:
1306 clock = T55x7_BITRATE_RF_16;
1307 break;
1308 case 0:
1309 // A value of 0 is assumed to be 64 for backwards-compatibility
1310 // Fall through...
1311 case 64:
1312 clock = T55x7_BITRATE_RF_64;
1313 break;
1314 default:
1315 Dbprintf("Invalid clock rate: %d", clock);
1316 return;
1317 }
1318
1319 // Writing configuration for T55x7 tag
1320 T55xxWriteBlock(clock |
1321 T55x7_MODULATION_MANCHESTER |
1322 2 << T55x7_MAXBLOCK_SHIFT,
1323 0, 0, 0);
1324 }
1325 else
1326 // Writing configuration for T5555(Q5) tag
1327 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1328 T5555_MODULATION_MANCHESTER |
1329 2 << T5555_MAXBLOCK_SHIFT,
1330 0, 0, 0);
1331
1332 LED_D_OFF();
1333 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1334 (uint32_t)(id >> 32), (uint32_t)id);
2d4eae76 1335}
2414f978 1336
1337// Clone Indala 64-bit tag by UID to T55x7
1338void CopyIndala64toT55x7(int hi, int lo)
1339{
2414f978 1340
c07b79fc 1341 //Program the 2 data blocks for supplied 64bit UID
1342 // and the block 0 for Indala64 format
1343 T55xxWriteBlock(hi,1,0,0);
1344 T55xxWriteBlock(lo,2,0,0);
1345 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1346 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1347 T55x7_MODULATION_PSK1 |
1348 2 << T55x7_MAXBLOCK_SHIFT,
1349 0, 0, 0);
1350 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1351 // T5567WriteBlock(0x603E1042,0);
4118b74d 1352
c07b79fc 1353 DbpString("DONE!");
4118b74d 1354
2414f978 1355}
1356
1357void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1358{
ae8e8a43 1359
c07b79fc 1360 //Program the 7 data blocks for supplied 224bit UID
1361 // and the block 0 for Indala224 format
1362 T55xxWriteBlock(uid1,1,0,0);
1363 T55xxWriteBlock(uid2,2,0,0);
1364 T55xxWriteBlock(uid3,3,0,0);
1365 T55xxWriteBlock(uid4,4,0,0);
1366 T55xxWriteBlock(uid5,5,0,0);
1367 T55xxWriteBlock(uid6,6,0,0);
1368 T55xxWriteBlock(uid7,7,0,0);
1369 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1370 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1371 T55x7_MODULATION_PSK1 |
1372 7 << T55x7_MAXBLOCK_SHIFT,
1373 0,0,0);
1374 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1375 // T5567WriteBlock(0x603E10E2,0);
1376
1377 DbpString("DONE!");
4118b74d 1378
2414f978 1379}
54a942b0 1380
1381
1382#define abs(x) ( ((x)<0) ? -(x) : (x) )
1383#define max(x,y) ( x<y ? y:x)
1384
1385int DemodPCF7931(uint8_t **outBlocks) {
c07b79fc 1386 uint8_t BitStream[256];
1387 uint8_t Blocks[8][16];
1388 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1389 int GraphTraceLen = sizeof(BigBuf);
1390 int i, j, lastval, bitidx, half_switch;
1391 int clock = 64;
1392 int tolerance = clock / 8;
1393 int pmc, block_done;
1394 int lc, warnings = 0;
1395 int num_blocks = 0;
1396 int lmin=128, lmax=128;
1397 uint8_t dir;
1398
1399 AcquireRawAdcSamples125k(0);
1400
1401 lmin = 64;
1402 lmax = 192;
1403
1404 i = 2;
1405
1406 /* Find first local max/min */
1407 if(GraphBuffer[1] > GraphBuffer[0]) {
1408 while(i < GraphTraceLen) {
1409 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1410 break;
1411 i++;
1412 }
1413 dir = 0;
54a942b0 1414 }
c07b79fc 1415 else {
1416 while(i < GraphTraceLen) {
1417 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1418 break;
1419 i++;
1420 }
1421 dir = 1;
ae8e8a43 1422 }
c07b79fc 1423
1424 lastval = i++;
1425 half_switch = 0;
1426 pmc = 0;
1427 block_done = 0;
1428
1429 for (bitidx = 0; i < GraphTraceLen; i++)
1430 {
1431 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1432 {
1433 lc = i - lastval;
1434 lastval = i;
1435
1436 // Switch depending on lc length:
1437 // Tolerance is 1/8 of clock rate (arbitrary)
1438 if (abs(lc-clock/4) < tolerance) {
1439 // 16T0
1440 if((i - pmc) == lc) { /* 16T0 was previous one */
1441 /* It's a PMC ! */
1442 i += (128+127+16+32+33+16)-1;
1443 lastval = i;
1444 pmc = 0;
1445 block_done = 1;
1446 }
1447 else {
1448 pmc = i;
1449 }
1450 } else if (abs(lc-clock/2) < tolerance) {
1451 // 32TO
1452 if((i - pmc) == lc) { /* 16T0 was previous one */
1453 /* It's a PMC ! */
1454 i += (128+127+16+32+33)-1;
1455 lastval = i;
1456 pmc = 0;
1457 block_done = 1;
1458 }
1459 else if(half_switch == 1) {
1460 BitStream[bitidx++] = 0;
1461 half_switch = 0;
1462 }
1463 else
1464 half_switch++;
1465 } else if (abs(lc-clock) < tolerance) {
1466 // 64TO
1467 BitStream[bitidx++] = 1;
1468 } else {
1469 // Error
1470 warnings++;
1471 if (warnings > 10)
1472 {
1473 Dbprintf("Error: too many detection errors, aborting.");
1474 return 0;
1475 }
1476 }
1477
1478 if(block_done == 1) {
1479 if(bitidx == 128) {
1480 for(j=0; j<16; j++) {
1481 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1482 64*BitStream[j*8+6]+
1483 32*BitStream[j*8+5]+
1484 16*BitStream[j*8+4]+
1485 8*BitStream[j*8+3]+
1486 4*BitStream[j*8+2]+
1487 2*BitStream[j*8+1]+
1488 BitStream[j*8];
1489 }
1490 num_blocks++;
1491 }
1492 bitidx = 0;
1493 block_done = 0;
1494 half_switch = 0;
1495 }
1496 if(i < GraphTraceLen)
1497 {
1498 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1499 else dir = 1;
1500 }
1501 }
1502 if(bitidx==255)
1503 bitidx=0;
1504 warnings = 0;
1505 if(num_blocks == 4) break;
1506 }
1507 memcpy(outBlocks, Blocks, 16*num_blocks);
1508 return num_blocks;
54a942b0 1509}
1510
1511int IsBlock0PCF7931(uint8_t *Block) {
c07b79fc 1512 // Assume RFU means 0 :)
1513 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1514 return 1;
1515 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1516 return 1;
1517 return 0;
54a942b0 1518}
1519
1520int IsBlock1PCF7931(uint8_t *Block) {
c07b79fc 1521 // Assume RFU means 0 :)
1522 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1523 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1524 return 1;
1525
1526 return 0;
54a942b0 1527}
4118b74d 1528
54a942b0 1529#define ALLOC 16
1530
1531void ReadPCF7931() {
c07b79fc 1532 uint8_t Blocks[8][17];
1533 uint8_t tmpBlocks[4][16];
1534 int i, j, ind, ind2, n;
1535 int num_blocks = 0;
1536 int max_blocks = 8;
1537 int ident = 0;
1538 int error = 0;
1539 int tries = 0;
1540
1541 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1542
1543 do {
1544 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1545 n = DemodPCF7931((uint8_t**)tmpBlocks);
1546 if(!n)
1547 error++;
1548 if(error==10 && num_blocks == 0) {
1549 Dbprintf("Error, no tag or bad tag");
1550 return;
ae8e8a43 1551 }
c07b79fc 1552 else if (tries==20 || error==10) {
1553 Dbprintf("Error reading the tag");
1554 Dbprintf("Here is the partial content");
1555 goto end;
1556 }
1557
1558 for(i=0; i<n; i++)
1559 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1560 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1561 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1562 if(!ident) {
1563 for(i=0; i<n; i++) {
1564 if(IsBlock0PCF7931(tmpBlocks[i])) {
1565 // Found block 0 ?
1566 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1567 // Found block 1!
1568 // \o/
1569 ident = 1;
1570 memcpy(Blocks[0], tmpBlocks[i], 16);
1571 Blocks[0][ALLOC] = 1;
1572 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1573 Blocks[1][ALLOC] = 1;
1574 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1575 // Debug print
1576 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1577 num_blocks = 2;
1578 // Handle following blocks
1579 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1580 if(j==n) j=0;
1581 if(j==i) break;
1582 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1583 Blocks[ind2][ALLOC] = 1;
1584 }
1585 break;
1586 }
54a942b0 1587 }
c07b79fc 1588 }
1589 }
1590 else {
1591 for(i=0; i<n; i++) { // Look for identical block in known blocks
1592 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1593 for(j=0; j<max_blocks; j++) {
1594 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1595 // Found an identical block
1596 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1597 if(ind2 < 0)
1598 ind2 = max_blocks;
1599 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1600 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1601 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1602 Blocks[ind2][ALLOC] = 1;
1603 num_blocks++;
1604 if(num_blocks == max_blocks) goto end;
1605 }
1606 }
1607 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1608 if(ind2 > max_blocks)
1609 ind2 = 0;
1610 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1611 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1612 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1613 Blocks[ind2][ALLOC] = 1;
1614 num_blocks++;
1615 if(num_blocks == max_blocks) goto end;
1616 }
1617 }
1618 }
1619 }
4118b74d 1620 }
54a942b0 1621 }
54a942b0 1622 }
c07b79fc 1623 tries++;
1624 if (BUTTON_PRESS()) return;
1625 } while (num_blocks != max_blocks);
4118b74d 1626end:
c07b79fc 1627 Dbprintf("-----------------------------------------");
1628 Dbprintf("Memory content:");
1629 Dbprintf("-----------------------------------------");
1630 for(i=0; i<max_blocks; i++) {
1631 if(Blocks[i][ALLOC]==1)
1632 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1633 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1634 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1635 else
1636 Dbprintf("<missing block %d>", i);
1637 }
1638 Dbprintf("-----------------------------------------");
1639
1640 return ;
54a942b0 1641}
1642
1643
1644//-----------------------------------
1645// EM4469 / EM4305 routines
1646//-----------------------------------
1647#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1648#define FWD_CMD_WRITE 0xA
1649#define FWD_CMD_READ 0x9
1650#define FWD_CMD_DISABLE 0x5
1651
1652
1653uint8_t forwardLink_data[64]; //array of forwarded bits
1654uint8_t * forward_ptr; //ptr for forward message preparation
1655uint8_t fwd_bit_sz; //forwardlink bit counter
1656uint8_t * fwd_write_ptr; //forwardlink bit pointer
1657
1658//====================================================================
1659// prepares command bits
1660// see EM4469 spec
1661//====================================================================
1662//--------------------------------------------------------------------
1663uint8_t Prepare_Cmd( uint8_t cmd ) {
c07b79fc 1664 //--------------------------------------------------------------------
1665
1666 *forward_ptr++ = 0; //start bit
1667 *forward_ptr++ = 0; //second pause for 4050 code
1668
1669 *forward_ptr++ = cmd;
1670 cmd >>= 1;
1671 *forward_ptr++ = cmd;
1672 cmd >>= 1;
1673 *forward_ptr++ = cmd;
1674 cmd >>= 1;
1675 *forward_ptr++ = cmd;
1676
1677 return 6; //return number of emited bits
54a942b0 1678}
1679
1680//====================================================================
1681// prepares address bits
1682// see EM4469 spec
1683//====================================================================
1684
1685//--------------------------------------------------------------------
1686uint8_t Prepare_Addr( uint8_t addr ) {
c07b79fc 1687 //--------------------------------------------------------------------
1688
1689 register uint8_t line_parity;
1690
1691 uint8_t i;
1692 line_parity = 0;
1693 for(i=0;i<6;i++) {
1694 *forward_ptr++ = addr;
1695 line_parity ^= addr;
1696 addr >>= 1;
1697 }
1698
1699 *forward_ptr++ = (line_parity & 1);
1700
1701 return 7; //return number of emited bits
54a942b0 1702}
1703
1704//====================================================================
1705// prepares data bits intreleaved with parity bits
1706// see EM4469 spec
1707//====================================================================
1708
1709//--------------------------------------------------------------------
1710uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
c07b79fc 1711 //--------------------------------------------------------------------
1712
1713 register uint8_t line_parity;
1714 register uint8_t column_parity;
1715 register uint8_t i, j;
1716 register uint16_t data;
1717
1718 data = data_low;
1719 column_parity = 0;
1720
1721 for(i=0; i<4; i++) {
1722 line_parity = 0;
1723 for(j=0; j<8; j++) {
1724 line_parity ^= data;
1725 column_parity ^= (data & 1) << j;
1726 *forward_ptr++ = data;
1727 data >>= 1;
1728 }
1729 *forward_ptr++ = line_parity;
1730 if(i == 1)
1731 data = data_hi;
1732 }
1733
54a942b0 1734 for(j=0; j<8; j++) {
c07b79fc 1735 *forward_ptr++ = column_parity;
1736 column_parity >>= 1;
54a942b0 1737 }
c07b79fc 1738 *forward_ptr = 0;
1739
1740 return 45; //return number of emited bits
54a942b0 1741}
1742
1743//====================================================================
1744// Forward Link send function
1745// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1746// fwd_bit_count set with number of bits to be sent
1747//====================================================================
1748void SendForward(uint8_t fwd_bit_count) {
c07b79fc 1749
1750 fwd_write_ptr = forwardLink_data;
1751 fwd_bit_sz = fwd_bit_count;
1752
1753 LED_D_ON();
1754
1755 //Field on
1756 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1757 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1758 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1759
1760 // Give it a bit of time for the resonant antenna to settle.
1761 // And for the tag to fully power up
1762 SpinDelay(150);
1763
1764 // force 1st mod pulse (start gap must be longer for 4305)
1765 fwd_bit_sz--; //prepare next bit modulation
1766 fwd_write_ptr++;
1767 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1768 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1769 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1770 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1771 SpinDelayUs(16*8); //16 cycles on (8us each)
1772
1773 // now start writting
1774 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1775 if(((*fwd_write_ptr++) & 1) == 1)
1776 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1777 else {
1778 //These timings work for 4469/4269/4305 (with the 55*8 above)
1779 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1780 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1781 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1782 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1783 SpinDelayUs(9*8); //16 cycles on (8us each)
1784 }
54a942b0 1785 }
54a942b0 1786}
1787
1788void EM4xLogin(uint32_t Password) {
c07b79fc 1789
1790 uint8_t fwd_bit_count;
1791
1792 forward_ptr = forwardLink_data;
1793 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1794 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1795
1796 SendForward(fwd_bit_count);
1797
1798 //Wait for command to complete
1799 SpinDelay(20);
1800
54a942b0 1801}
1802
1803void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
c07b79fc 1804
1805 uint8_t fwd_bit_count;
1806 uint8_t *dest = (uint8_t *)BigBuf;
1807 int m=0, i=0;
1808
1809 //If password mode do login
1810 if (PwdMode == 1) EM4xLogin(Pwd);
1811
1812 forward_ptr = forwardLink_data;
1813 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1814 fwd_bit_count += Prepare_Addr( Address );
1815
1816 m = sizeof(BigBuf);
1817 // Clear destination buffer before sending the command
1818 memset(dest, 128, m);
1819 // Connect the A/D to the peak-detected low-frequency path.
1820 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1821 // Now set up the SSC to get the ADC samples that are now streaming at us.
1822 FpgaSetupSsc();
1823
1824 SendForward(fwd_bit_count);
1825
1826 // Now do the acquisition
1827 i = 0;
1828 for(;;) {
1829 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1830 AT91C_BASE_SSC->SSC_THR = 0x43;
1831 }
1832 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1833 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1834 i++;
1835 if (i >= m) break;
1836 }
4118b74d 1837 }
c07b79fc 1838 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1839 LED_D_OFF();
54a942b0 1840}
1841
1842void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
c07b79fc 1843
1844 uint8_t fwd_bit_count;
1845
1846 //If password mode do login
1847 if (PwdMode == 1) EM4xLogin(Pwd);
1848
1849 forward_ptr = forwardLink_data;
1850 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1851 fwd_bit_count += Prepare_Addr( Address );
1852 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1853
1854 SendForward(fwd_bit_count);
1855
1856 //Wait for write to complete
1857 SpinDelay(20);
1858 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1859 LED_D_OFF();
54a942b0 1860}
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