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ADD: Marshmellows fixes for "lf t55xx" and "lf cmdread" ref: https://github.com...
[proxmark3-svn] / armsrc / iclass.c
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cee5a30d 1//-----------------------------------------------------------------------------
2// Gerhard de Koning Gans - May 2008
3// Hagen Fritsch - June 2010
4// Gerhard de Koning Gans - May 2011
1e262141 5// Gerhard de Koning Gans - June 2012 - Added iClass card and reader emulation
cee5a30d 6//
7// This code is licensed to you under the terms of the GNU GPL, version 2 or,
8// at your option, any later version. See the LICENSE.txt file for the text of
9// the license.
10//-----------------------------------------------------------------------------
11// Routines to support iClass.
12//-----------------------------------------------------------------------------
13// Based on ISO14443a implementation. Still in experimental phase.
14// Contribution made during a security research at Radboud University Nijmegen
15//
16// Please feel free to contribute and extend iClass support!!
17//-----------------------------------------------------------------------------
18//
cee5a30d 19// FIX:
20// ====
21// We still have sometimes a demodulation error when snooping iClass communication.
22// The resulting trace of a read-block-03 command may look something like this:
23//
24// + 22279: : 0c 03 e8 01
25//
26// ...with an incorrect answer...
27//
28// + 85: 0: TAG ff! ff! ff! ff! ff! ff! ff! ff! bb 33 bb 00 01! 0e! 04! bb !crc
29//
30// We still left the error signalling bytes in the traces like 0xbb
31//
32// A correct trace should look like this:
33//
34// + 21112: : 0c 03 e8 01
35// + 85: 0: TAG ff ff ff ff ff ff ff ff ea f5
36//
37//-----------------------------------------------------------------------------
38
99cf19d9 39#include "proxmark3.h"
cee5a30d 40#include "apps.h"
41#include "util.h"
42#include "string.h"
7e67e42f 43#include "common.h"
f38a1528 44#include "cmd.h"
1e262141 45// Needed for CRC in emulation mode;
46// same construction as in ISO 14443;
47// different initial value (CRC_ICLASS)
99cf19d9 48#include "iso14443crc.h"
49#include "iso15693tools.h"
b67f7ec3 50#include "protocols.h"
10a8875c 51#include "optimized_cipher.h"
cee5a30d 52
1e262141 53static int timeout = 4096;
cee5a30d 54
cee5a30d 55
1e262141 56static int SendIClassAnswer(uint8_t *resp, int respLen, int delay);
cee5a30d 57
58//-----------------------------------------------------------------------------
59// The software UART that receives commands from the reader, and its state
60// variables.
61//-----------------------------------------------------------------------------
62static struct {
63 enum {
64 STATE_UNSYNCD,
65 STATE_START_OF_COMMUNICATION,
66 STATE_RECEIVING
67 } state;
68 uint16_t shiftReg;
69 int bitCnt;
70 int byteCnt;
71 int byteCntMax;
72 int posCnt;
73 int nOutOfCnt;
74 int OutOfCnt;
75 int syncBit;
1e262141 76 int samples;
cee5a30d 77 int highCnt;
78 int swapper;
79 int counter;
80 int bitBuffer;
81 int dropPosition;
a501c82b 82 uint8_t *output;
cee5a30d 83} Uart;
84
1e262141 85static RAMFUNC int OutOfNDecoding(int bit)
cee5a30d 86{
9f693930 87 //int error = 0;
cee5a30d 88 int bitright;
89
90 if(!Uart.bitBuffer) {
91 Uart.bitBuffer = bit ^ 0xFF0;
92 return FALSE;
93 }
94 else {
95 Uart.bitBuffer <<= 4;
96 Uart.bitBuffer ^= bit;
97 }
98
99 /*if(Uart.swapper) {
100 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
101 Uart.byteCnt++;
102 Uart.swapper = 0;
103 if(Uart.byteCnt > 15) { return TRUE; }
104 }
105 else {
106 Uart.swapper = 1;
107 }*/
108
109 if(Uart.state != STATE_UNSYNCD) {
110 Uart.posCnt++;
111
112 if((Uart.bitBuffer & Uart.syncBit) ^ Uart.syncBit) {
113 bit = 0x00;
114 }
115 else {
116 bit = 0x01;
117 }
118 if(((Uart.bitBuffer << 1) & Uart.syncBit) ^ Uart.syncBit) {
119 bitright = 0x00;
120 }
121 else {
122 bitright = 0x01;
123 }
124 if(bit != bitright) { bit = bitright; }
125
126
127 // So, now we only have to deal with *bit*, lets see...
128 if(Uart.posCnt == 1) {
129 // measurement first half bitperiod
130 if(!bit) {
131 // Drop in first half means that we are either seeing
132 // an SOF or an EOF.
133
134 if(Uart.nOutOfCnt == 1) {
135 // End of Communication
136 Uart.state = STATE_UNSYNCD;
137 Uart.highCnt = 0;
138 if(Uart.byteCnt == 0) {
139 // Its not straightforward to show single EOFs
140 // So just leave it and do not return TRUE
a501c82b 141 Uart.output[0] = 0xf0;
cee5a30d 142 Uart.byteCnt++;
cee5a30d 143 }
144 else {
145 return TRUE;
146 }
147 }
148 else if(Uart.state != STATE_START_OF_COMMUNICATION) {
149 // When not part of SOF or EOF, it is an error
150 Uart.state = STATE_UNSYNCD;
151 Uart.highCnt = 0;
9f693930 152 //error = 4;
cee5a30d 153 }
154 }
155 }
156 else {
157 // measurement second half bitperiod
158 // Count the bitslot we are in... (ISO 15693)
159 Uart.nOutOfCnt++;
160
161 if(!bit) {
162 if(Uart.dropPosition) {
163 if(Uart.state == STATE_START_OF_COMMUNICATION) {
9f693930 164 //error = 1;
cee5a30d 165 }
166 else {
9f693930 167 //error = 7;
cee5a30d 168 }
169 // It is an error if we already have seen a drop in current frame
170 Uart.state = STATE_UNSYNCD;
171 Uart.highCnt = 0;
172 }
173 else {
174 Uart.dropPosition = Uart.nOutOfCnt;
175 }
176 }
177
178 Uart.posCnt = 0;
179
180
181 if(Uart.nOutOfCnt == Uart.OutOfCnt && Uart.OutOfCnt == 4) {
182 Uart.nOutOfCnt = 0;
183
184 if(Uart.state == STATE_START_OF_COMMUNICATION) {
185 if(Uart.dropPosition == 4) {
186 Uart.state = STATE_RECEIVING;
187 Uart.OutOfCnt = 256;
188 }
189 else if(Uart.dropPosition == 3) {
190 Uart.state = STATE_RECEIVING;
191 Uart.OutOfCnt = 4;
192 //Uart.output[Uart.byteCnt] = 0xdd;
193 //Uart.byteCnt++;
194 }
195 else {
196 Uart.state = STATE_UNSYNCD;
197 Uart.highCnt = 0;
198 }
199 Uart.dropPosition = 0;
200 }
201 else {
202 // RECEIVING DATA
203 // 1 out of 4
204 if(!Uart.dropPosition) {
205 Uart.state = STATE_UNSYNCD;
206 Uart.highCnt = 0;
9f693930 207 //error = 9;
cee5a30d 208 }
209 else {
210 Uart.shiftReg >>= 2;
211
212 // Swap bit order
213 Uart.dropPosition--;
214 //if(Uart.dropPosition == 1) { Uart.dropPosition = 2; }
215 //else if(Uart.dropPosition == 2) { Uart.dropPosition = 1; }
216
217 Uart.shiftReg ^= ((Uart.dropPosition & 0x03) << 6);
218 Uart.bitCnt += 2;
219 Uart.dropPosition = 0;
220
221 if(Uart.bitCnt == 8) {
222 Uart.output[Uart.byteCnt] = (Uart.shiftReg & 0xff);
223 Uart.byteCnt++;
cee5a30d 224 Uart.bitCnt = 0;
225 Uart.shiftReg = 0;
226 }
227 }
228 }
229 }
230 else if(Uart.nOutOfCnt == Uart.OutOfCnt) {
231 // RECEIVING DATA
232 // 1 out of 256
233 if(!Uart.dropPosition) {
234 Uart.state = STATE_UNSYNCD;
235 Uart.highCnt = 0;
9f693930 236 //error = 3;
cee5a30d 237 }
238 else {
239 Uart.dropPosition--;
240 Uart.output[Uart.byteCnt] = (Uart.dropPosition & 0xff);
241 Uart.byteCnt++;
cee5a30d 242 Uart.bitCnt = 0;
243 Uart.shiftReg = 0;
244 Uart.nOutOfCnt = 0;
245 Uart.dropPosition = 0;
246 }
247 }
248
249 /*if(error) {
250 Uart.output[Uart.byteCnt] = 0xAA;
251 Uart.byteCnt++;
252 Uart.output[Uart.byteCnt] = error & 0xFF;
253 Uart.byteCnt++;
254 Uart.output[Uart.byteCnt] = 0xAA;
255 Uart.byteCnt++;
256 Uart.output[Uart.byteCnt] = (Uart.bitBuffer >> 8) & 0xFF;
257 Uart.byteCnt++;
258 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
259 Uart.byteCnt++;
260 Uart.output[Uart.byteCnt] = (Uart.syncBit >> 3) & 0xFF;
261 Uart.byteCnt++;
262 Uart.output[Uart.byteCnt] = 0xAA;
263 Uart.byteCnt++;
264 return TRUE;
265 }*/
266 }
267
268 }
269 else {
270 bit = Uart.bitBuffer & 0xf0;
271 bit >>= 4;
272 bit ^= 0x0F; // drops become 1s ;-)
273 if(bit) {
274 // should have been high or at least (4 * 128) / fc
275 // according to ISO this should be at least (9 * 128 + 20) / fc
276 if(Uart.highCnt == 8) {
277 // we went low, so this could be start of communication
278 // it turns out to be safer to choose a less significant
279 // syncbit... so we check whether the neighbour also represents the drop
280 Uart.posCnt = 1; // apparently we are busy with our first half bit period
281 Uart.syncBit = bit & 8;
282 Uart.samples = 3;
283 if(!Uart.syncBit) { Uart.syncBit = bit & 4; Uart.samples = 2; }
284 else if(bit & 4) { Uart.syncBit = bit & 4; Uart.samples = 2; bit <<= 2; }
285 if(!Uart.syncBit) { Uart.syncBit = bit & 2; Uart.samples = 1; }
286 else if(bit & 2) { Uart.syncBit = bit & 2; Uart.samples = 1; bit <<= 1; }
287 if(!Uart.syncBit) { Uart.syncBit = bit & 1; Uart.samples = 0;
288 if(Uart.syncBit && (Uart.bitBuffer & 8)) {
289 Uart.syncBit = 8;
290
291 // the first half bit period is expected in next sample
292 Uart.posCnt = 0;
293 Uart.samples = 3;
294 }
295 }
296 else if(bit & 1) { Uart.syncBit = bit & 1; Uart.samples = 0; }
297
298 Uart.syncBit <<= 4;
299 Uart.state = STATE_START_OF_COMMUNICATION;
300 Uart.bitCnt = 0;
301 Uart.byteCnt = 0;
cee5a30d 302 Uart.nOutOfCnt = 0;
303 Uart.OutOfCnt = 4; // Start at 1/4, could switch to 1/256
304 Uart.dropPosition = 0;
305 Uart.shiftReg = 0;
9f693930 306 //error = 0;
cee5a30d 307 }
308 else {
309 Uart.highCnt = 0;
310 }
311 }
312 else {
313 if(Uart.highCnt < 8) {
314 Uart.highCnt++;
315 }
316 }
317 }
318
319 return FALSE;
320}
321
322//=============================================================================
1e262141 323// Manchester
cee5a30d 324//=============================================================================
325
326static struct {
327 enum {
328 DEMOD_UNSYNCD,
329 DEMOD_START_OF_COMMUNICATION,
330 DEMOD_START_OF_COMMUNICATION2,
331 DEMOD_START_OF_COMMUNICATION3,
332 DEMOD_SOF_COMPLETE,
333 DEMOD_MANCHESTER_D,
334 DEMOD_MANCHESTER_E,
335 DEMOD_END_OF_COMMUNICATION,
336 DEMOD_END_OF_COMMUNICATION2,
337 DEMOD_MANCHESTER_F,
338 DEMOD_ERROR_WAIT
339 } state;
340 int bitCount;
341 int posCount;
342 int syncBit;
cee5a30d 343 uint16_t shiftReg;
344 int buffer;
345 int buffer2;
346 int buffer3;
347 int buff;
348 int samples;
349 int len;
350 enum {
351 SUB_NONE,
352 SUB_FIRST_HALF,
353 SUB_SECOND_HALF,
354 SUB_BOTH
355 } sub;
356 uint8_t *output;
357} Demod;
358
359static RAMFUNC int ManchesterDecoding(int v)
360{
361 int bit;
362 int modulation;
363 int error = 0;
364
365 bit = Demod.buffer;
366 Demod.buffer = Demod.buffer2;
367 Demod.buffer2 = Demod.buffer3;
368 Demod.buffer3 = v;
369
370 if(Demod.buff < 3) {
371 Demod.buff++;
372 return FALSE;
373 }
374
375 if(Demod.state==DEMOD_UNSYNCD) {
376 Demod.output[Demod.len] = 0xfa;
377 Demod.syncBit = 0;
378 //Demod.samples = 0;
379 Demod.posCount = 1; // This is the first half bit period, so after syncing handle the second part
cee5a30d 380
381 if(bit & 0x08) {
382 Demod.syncBit = 0x08;
383 }
384
385 if(bit & 0x04) {
386 if(Demod.syncBit) {
387 bit <<= 4;
388 }
389 Demod.syncBit = 0x04;
390 }
391
392 if(bit & 0x02) {
393 if(Demod.syncBit) {
394 bit <<= 2;
395 }
396 Demod.syncBit = 0x02;
397 }
398
399 if(bit & 0x01 && Demod.syncBit) {
400 Demod.syncBit = 0x01;
401 }
402
403 if(Demod.syncBit) {
404 Demod.len = 0;
405 Demod.state = DEMOD_START_OF_COMMUNICATION;
406 Demod.sub = SUB_FIRST_HALF;
407 Demod.bitCount = 0;
408 Demod.shiftReg = 0;
cee5a30d 409 Demod.samples = 0;
410 if(Demod.posCount) {
411 //if(trigger) LED_A_OFF(); // Not useful in this case...
412 switch(Demod.syncBit) {
413 case 0x08: Demod.samples = 3; break;
414 case 0x04: Demod.samples = 2; break;
415 case 0x02: Demod.samples = 1; break;
416 case 0x01: Demod.samples = 0; break;
417 }
418 // SOF must be long burst... otherwise stay unsynced!!!
419 if(!(Demod.buffer & Demod.syncBit) || !(Demod.buffer2 & Demod.syncBit)) {
420 Demod.state = DEMOD_UNSYNCD;
421 }
422 }
423 else {
424 // SOF must be long burst... otherwise stay unsynced!!!
425 if(!(Demod.buffer2 & Demod.syncBit) || !(Demod.buffer3 & Demod.syncBit)) {
426 Demod.state = DEMOD_UNSYNCD;
427 error = 0x88;
428 }
5cc88edf 429
430 // TODO: use this error value to print? Ask Holiman.
431 // 2016-01-08 iceman
cee5a30d 432 }
433 error = 0;
cee5a30d 434 }
435 }
436 else {
437 modulation = bit & Demod.syncBit;
438 modulation |= ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit;
cee5a30d 439
440 Demod.samples += 4;
441
442 if(Demod.posCount==0) {
443 Demod.posCount = 1;
444 if(modulation) {
445 Demod.sub = SUB_FIRST_HALF;
446 }
447 else {
448 Demod.sub = SUB_NONE;
449 }
450 }
451 else {
452 Demod.posCount = 0;
453 /*(modulation && (Demod.sub == SUB_FIRST_HALF)) {
454 if(Demod.state!=DEMOD_ERROR_WAIT) {
455 Demod.state = DEMOD_ERROR_WAIT;
456 Demod.output[Demod.len] = 0xaa;
457 error = 0x01;
458 }
459 }*/
460 //else if(modulation) {
461 if(modulation) {
462 if(Demod.sub == SUB_FIRST_HALF) {
463 Demod.sub = SUB_BOTH;
464 }
465 else {
466 Demod.sub = SUB_SECOND_HALF;
467 }
468 }
469 else if(Demod.sub == SUB_NONE) {
470 if(Demod.state == DEMOD_SOF_COMPLETE) {
471 Demod.output[Demod.len] = 0x0f;
472 Demod.len++;
cee5a30d 473 Demod.state = DEMOD_UNSYNCD;
474// error = 0x0f;
475 return TRUE;
476 }
477 else {
478 Demod.state = DEMOD_ERROR_WAIT;
479 error = 0x33;
480 }
481 /*if(Demod.state!=DEMOD_ERROR_WAIT) {
482 Demod.state = DEMOD_ERROR_WAIT;
483 Demod.output[Demod.len] = 0xaa;
484 error = 0x01;
485 }*/
486 }
487
488 switch(Demod.state) {
489 case DEMOD_START_OF_COMMUNICATION:
490 if(Demod.sub == SUB_BOTH) {
491 //Demod.state = DEMOD_MANCHESTER_D;
492 Demod.state = DEMOD_START_OF_COMMUNICATION2;
493 Demod.posCount = 1;
494 Demod.sub = SUB_NONE;
495 }
496 else {
497 Demod.output[Demod.len] = 0xab;
498 Demod.state = DEMOD_ERROR_WAIT;
499 error = 0xd2;
500 }
501 break;
502 case DEMOD_START_OF_COMMUNICATION2:
503 if(Demod.sub == SUB_SECOND_HALF) {
504 Demod.state = DEMOD_START_OF_COMMUNICATION3;
505 }
506 else {
507 Demod.output[Demod.len] = 0xab;
508 Demod.state = DEMOD_ERROR_WAIT;
509 error = 0xd3;
510 }
511 break;
512 case DEMOD_START_OF_COMMUNICATION3:
513 if(Demod.sub == SUB_SECOND_HALF) {
514// Demod.state = DEMOD_MANCHESTER_D;
515 Demod.state = DEMOD_SOF_COMPLETE;
516 //Demod.output[Demod.len] = Demod.syncBit & 0xFF;
517 //Demod.len++;
518 }
519 else {
520 Demod.output[Demod.len] = 0xab;
521 Demod.state = DEMOD_ERROR_WAIT;
522 error = 0xd4;
523 }
524 break;
525 case DEMOD_SOF_COMPLETE:
526 case DEMOD_MANCHESTER_D:
527 case DEMOD_MANCHESTER_E:
528 // OPPOSITE FROM ISO14443 - 11110000 = 0 (1 in 14443)
529 // 00001111 = 1 (0 in 14443)
530 if(Demod.sub == SUB_SECOND_HALF) { // SUB_FIRST_HALF
531 Demod.bitCount++;
532 Demod.shiftReg = (Demod.shiftReg >> 1) ^ 0x100;
533 Demod.state = DEMOD_MANCHESTER_D;
534 }
535 else if(Demod.sub == SUB_FIRST_HALF) { // SUB_SECOND_HALF
536 Demod.bitCount++;
537 Demod.shiftReg >>= 1;
538 Demod.state = DEMOD_MANCHESTER_E;
539 }
540 else if(Demod.sub == SUB_BOTH) {
541 Demod.state = DEMOD_MANCHESTER_F;
542 }
543 else {
544 Demod.state = DEMOD_ERROR_WAIT;
545 error = 0x55;
546 }
547 break;
548
549 case DEMOD_MANCHESTER_F:
550 // Tag response does not need to be a complete byte!
551 if(Demod.len > 0 || Demod.bitCount > 0) {
552 if(Demod.bitCount > 1) { // was > 0, do not interpret last closing bit, is part of EOF
f5ed4d12 553 Demod.shiftReg >>= (9 - Demod.bitCount); // right align data
cee5a30d 554 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
555 Demod.len++;
cee5a30d 556 }
557
558 Demod.state = DEMOD_UNSYNCD;
559 return TRUE;
560 }
561 else {
562 Demod.output[Demod.len] = 0xad;
563 Demod.state = DEMOD_ERROR_WAIT;
564 error = 0x03;
565 }
566 break;
567
568 case DEMOD_ERROR_WAIT:
569 Demod.state = DEMOD_UNSYNCD;
570 break;
571
572 default:
573 Demod.output[Demod.len] = 0xdd;
574 Demod.state = DEMOD_UNSYNCD;
575 break;
576 }
577
578 /*if(Demod.bitCount>=9) {
579 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
580 Demod.len++;
581
582 Demod.parityBits <<= 1;
583 Demod.parityBits ^= ((Demod.shiftReg >> 8) & 0x01);
584
585 Demod.bitCount = 0;
586 Demod.shiftReg = 0;
587 }*/
588 if(Demod.bitCount>=8) {
589 Demod.shiftReg >>= 1;
590 Demod.output[Demod.len] = (Demod.shiftReg & 0xff);
591 Demod.len++;
cee5a30d 592 Demod.bitCount = 0;
593 Demod.shiftReg = 0;
594 }
595
596 if(error) {
597 Demod.output[Demod.len] = 0xBB;
598 Demod.len++;
599 Demod.output[Demod.len] = error & 0xFF;
600 Demod.len++;
601 Demod.output[Demod.len] = 0xBB;
602 Demod.len++;
603 Demod.output[Demod.len] = bit & 0xFF;
604 Demod.len++;
605 Demod.output[Demod.len] = Demod.buffer & 0xFF;
606 Demod.len++;
607 // Look harder ;-)
608 Demod.output[Demod.len] = Demod.buffer2 & 0xFF;
609 Demod.len++;
610 Demod.output[Demod.len] = Demod.syncBit & 0xFF;
611 Demod.len++;
612 Demod.output[Demod.len] = 0xBB;
613 Demod.len++;
614 return TRUE;
615 }
616
617 }
618
619 } // end (state != UNSYNCED)
620
621 return FALSE;
622}
623
624//=============================================================================
1e262141 625// Finally, a `sniffer' for iClass communication
cee5a30d 626// Both sides of communication!
627//=============================================================================
628
629//-----------------------------------------------------------------------------
630// Record the sequence of commands sent by the reader to the tag, with
631// triggering so that we start recording at the point that the tag is moved
632// near the reader.
633//-----------------------------------------------------------------------------
634void RAMFUNC SnoopIClass(void)
635{
cee5a30d 636 // We won't start recording the frames that we acquire until we trigger;
637 // a good trigger condition to get started is probably when we see a
638 // response from the tag.
9f693930 639 //int triggered = FALSE; // FALSE to wait first for card
cee5a30d 640
641 // The command (reader -> tag) that we're receiving.
642 // The length of a received command will in most cases be no more than 18 bytes.
643 // So 32 should be enough!
f71f4deb 644 #define ICLASS_BUFFER_SIZE 32
645 uint8_t readerToTagCmd[ICLASS_BUFFER_SIZE];
cee5a30d 646 // The response (tag -> reader) that we're receiving.
f71f4deb 647 uint8_t tagToReaderResponse[ICLASS_BUFFER_SIZE];
6a1f2d82 648
7cc204bf 649 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
650
f71f4deb 651 // free all BigBuf memory
652 BigBuf_free();
653 // The DMA buffer, used to stream samples from the FPGA
654 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
655
3000dc4e 656 clear_trace();
810f5379 657 set_tracing(TRUE);
658
1e262141 659 iso14a_set_trigger(FALSE);
cee5a30d 660
cee5a30d 661 int lastRxCounter;
117d9ec2 662 uint8_t *upTo;
cee5a30d 663 int smpl;
664 int maxBehindBy = 0;
665
666 // Count of samples received so far, so that we can include timing
667 // information in the trace buffer.
668 int samples = 0;
669 rsamples = 0;
670
cee5a30d 671 // Set up the demodulator for tag -> reader responses.
17cba269 672 Demod.output = tagToReaderResponse;
cee5a30d 673 Demod.len = 0;
674 Demod.state = DEMOD_UNSYNCD;
675
676 // Setup for the DMA.
677 FpgaSetupSsc();
678 upTo = dmaBuf;
679 lastRxCounter = DMA_BUFFER_SIZE;
680 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
681
682 // And the reader -> tag commands
683 memset(&Uart, 0, sizeof(Uart));
17cba269 684 Uart.output = readerToTagCmd;
cee5a30d 685 Uart.byteCntMax = 32; // was 100 (greg)////////////////////////////////////////////////////////////////////////
686 Uart.state = STATE_UNSYNCD;
687
688 // And put the FPGA in the appropriate mode
689 // Signal field is off with the appropriate LED
690 LED_D_OFF();
691 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_SNIFFER);
692 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
693
81012e67 694 uint32_t time_0 = GetCountSspClk();
55eaed8f
MHS		 695 uint32_t time_start = 0;
696 uint32_t time_stop = 0;
81012e67 697
cee5a30d 698 int div = 0;
699 //int div2 = 0;
700 int decbyte = 0;
701 int decbyter = 0;
702
703 // And now we loop, receiving samples.
704 for(;;) {
705 LED_A_ON();
706 WDT_HIT();
4a71da5a 707 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (DMA_BUFFER_SIZE-1);
708
709 if ( behindBy > maxBehindBy) {
cee5a30d 710 maxBehindBy = behindBy;
4a71da5a 711 if ( behindBy > (9 * DMA_BUFFER_SIZE / 10)) {
cee5a30d 712 Dbprintf("blew circular buffer! behindBy=0x%x", behindBy);
713 goto done;
714 }
715 }
4a71da5a 716 if( behindBy < 1) continue;
cee5a30d 717
4a71da5a 718 LED_A_OFF();
cee5a30d 719 smpl = upTo[0];
720 upTo++;
721 lastRxCounter -= 1;
4a71da5a 722 if (upTo - dmaBuf > DMA_BUFFER_SIZE) {
cee5a30d 723 upTo -= DMA_BUFFER_SIZE;
724 lastRxCounter += DMA_BUFFER_SIZE;
725 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
726 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
727 }
728
729 //samples += 4;
4a71da5a 730 samples += 1;
cee5a30d 731
4a71da5a 732 if(smpl & 0xF)
733 decbyte ^= (1 << (3 - div));
734
cee5a30d 735
4a71da5a 736 // FOR READER SIDE COMMUMICATION...
17cba269 737
4a71da5a 738 decbyter <<= 2;
739 decbyter ^= (smpl & 0x30);
cee5a30d 740
4a71da5a 741 ++div;
cee5a30d 742
4a71da5a 743 if (( div + 1) % 2 == 0) {
744 smpl = decbyter;
745 if ( OutOfNDecoding((smpl & 0xF0) >> 4)) {
746 rsamples = samples - Uart.samples;
747 time_stop = (GetCountSspClk()-time_0) << 4;
748 LED_C_ON();
749
750 //if(!LogTrace(Uart.output,Uart.byteCnt, rsamples, Uart.parityBits,TRUE)) break;
751 //if(!LogTrace(NULL, 0, Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, 0, TRUE)) break;
752 if(tracing) {
753 uint8_t parity[MAX_PARITY_SIZE];
754 GetParity(Uart.output, Uart.byteCnt, parity);
755 LogTrace(Uart.output,Uart.byteCnt, time_start, time_stop, parity, TRUE);
756 }
17cba269 757
4a71da5a 758 /* And ready to receive another command. */
759 Uart.state = STATE_UNSYNCD;
760 /* And also reset the demod code, which might have been */
761 /* false-triggered by the commands from the reader. */
762 Demod.state = DEMOD_UNSYNCD;
763 LED_B_OFF();
764 Uart.byteCnt = 0;
765 } else {
766 time_start = (GetCountSspClk()-time_0) << 4;
767 }
768 decbyter = 0;
cee5a30d 769 }
cee5a30d 770
4a71da5a 771 if(div > 3) {
772 smpl = decbyte;
773 if(ManchesterDecoding(smpl & 0x0F)) {
774 time_stop = (GetCountSspClk()-time_0) << 4;
55eaed8f 775
4a71da5a 776 rsamples = samples - Demod.samples;
777 LED_B_ON();
cee5a30d 778
4a71da5a 779 if(tracing) {
780 uint8_t parity[MAX_PARITY_SIZE];
781 GetParity(Demod.output, Demod.len, parity);
782 LogTrace(Demod.output, Demod.len, time_start, time_stop, parity, FALSE);
783 }
17cba269 784
4a71da5a 785 // And ready to receive another response.
786 memset(&Demod, 0, sizeof(Demod));
787 Demod.output = tagToReaderResponse;
788 Demod.state = DEMOD_UNSYNCD;
789 LED_C_OFF();
790 } else {
791 time_start = (GetCountSspClk()-time_0) << 4;
792 }
793
794 div = 0;
795 decbyte = 0x00;
cee5a30d 796 }
cee5a30d 797
4a71da5a 798 if (BUTTON_PRESS()) {
cee5a30d 799 DbpString("cancelled_a");
800 goto done;
801 }
802 }
803
804 DbpString("COMMAND FINISHED");
805
806 Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
3000dc4e 807 Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
cee5a30d 808
809done:
810 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
811 Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
3000dc4e 812 Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
4a71da5a 813 LEDsoff();
5ee53a0e 814 set_tracing(FALSE);
1e262141 815}
816
912a3e94 817void rotateCSN(uint8_t* originalCSN, uint8_t* rotatedCSN) {
818 int i;
4a71da5a 819 for(i = 0; i < 8; i++)
912a3e94 820 rotatedCSN[i] = (originalCSN[i] >> 3) | (originalCSN[(i+1)%8] << 5);
1e262141 821}
822
823//-----------------------------------------------------------------------------
824// Wait for commands from reader
825// Stop when button is pressed
826// Or return TRUE when command is captured
827//-----------------------------------------------------------------------------
828static int GetIClassCommandFromReader(uint8_t *received, int *len, int maxLen)
829{
912a3e94 830 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1e262141 831 // only, since we are receiving, not transmitting).
832 // Signal field is off with the appropriate LED
833 LED_D_OFF();
834 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
835
836 // Now run a `software UART' on the stream of incoming samples.
837 Uart.output = received;
838 Uart.byteCntMax = maxLen;
839 Uart.state = STATE_UNSYNCD;
840
841 for(;;) {
842 WDT_HIT();
843
844 if(BUTTON_PRESS()) return FALSE;
845
846 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
847 AT91C_BASE_SSC->SSC_THR = 0x00;
848 }
849 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
850 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
95e63594 851
1e262141 852 if(OutOfNDecoding(b & 0x0f)) {
853 *len = Uart.byteCnt;
854 return TRUE;
855 }
856 }
857 }
858}
859
645c960f
MHS		 860static uint8_t encode4Bits(const uint8_t b)
861{
862 uint8_t c = b & 0xF;
863 // OTA, the least significant bits first
864 // The columns are
865 // 1 - Bit value to send
866 // 2 - Reversed (big-endian)
867 // 3 - Encoded
868 // 4 - Hex values
869
870 switch(c){
871 // 1 2 3 4
872 case 15: return 0x55; // 1111 -> 1111 -> 01010101 -> 0x55
873 case 14: return 0x95; // 1110 -> 0111 -> 10010101 -> 0x95
874 case 13: return 0x65; // 1101 -> 1011 -> 01100101 -> 0x65
875 case 12: return 0xa5; // 1100 -> 0011 -> 10100101 -> 0xa5
876 case 11: return 0x59; // 1011 -> 1101 -> 01011001 -> 0x59
877 case 10: return 0x99; // 1010 -> 0101 -> 10011001 -> 0x99
878 case 9: return 0x69; // 1001 -> 1001 -> 01101001 -> 0x69
879 case 8: return 0xa9; // 1000 -> 0001 -> 10101001 -> 0xa9
880 case 7: return 0x56; // 0111 -> 1110 -> 01010110 -> 0x56
881 case 6: return 0x96; // 0110 -> 0110 -> 10010110 -> 0x96
882 case 5: return 0x66; // 0101 -> 1010 -> 01100110 -> 0x66
883 case 4: return 0xa6; // 0100 -> 0010 -> 10100110 -> 0xa6
884 case 3: return 0x5a; // 0011 -> 1100 -> 01011010 -> 0x5a
885 case 2: return 0x9a; // 0010 -> 0100 -> 10011010 -> 0x9a
886 case 1: return 0x6a; // 0001 -> 1000 -> 01101010 -> 0x6a
887 default: return 0xaa; // 0000 -> 0000 -> 10101010 -> 0xaa
888
889 }
890}
1e262141 891
892//-----------------------------------------------------------------------------
893// Prepare tag messages
894//-----------------------------------------------------------------------------
895static void CodeIClassTagAnswer(const uint8_t *cmd, int len)
896{
645c960f
MHS		 897
898 /*
899 * SOF comprises 3 parts;
900 * * An unmodulated time of 56.64 us
901 * * 24 pulses of 423.75 KHz (fc/32)
902 * * A logic 1, which starts with an unmodulated time of 18.88us
903 * followed by 8 pulses of 423.75kHz (fc/32)
904 *
905 *
906 * EOF comprises 3 parts:
907 * - A logic 0 (which starts with 8 pulses of fc/32 followed by an unmodulated
908 * time of 18.88us.
909 * - 24 pulses of fc/32
910 * - An unmodulated time of 56.64 us
911 *
912 *
913 * A logic 0 starts with 8 pulses of fc/32
914 * followed by an unmodulated time of 256/fc (~18,88us).
915 *
916 * A logic 0 starts with unmodulated time of 256/fc (~18,88us) followed by
917 * 8 pulses of fc/32 (also 18.88us)
918 *
919 * The mode FPGA_HF_SIMULATOR_MODULATE_424K_8BIT which we use to simulate tag,
920 * works like this.
921 * - A 1-bit input to the FPGA becomes 8 pulses on 423.5kHz (fc/32) (18.88us).
922 * - A 0-bit inptu to the FPGA becomes an unmodulated time of 18.88us
923 *
6b038d19 924 * In this mode the SOF can be written as 00011101 = 0x1D
645c960f
MHS		 925 * The EOF can be written as 10111000 = 0xb8
926 * A logic 1 is 01
927 * A logic 0 is 10
928 *
929 * */
930
1e262141 931 int i;
932
933 ToSendReset();
934
935 // Send SOF
645c960f 936 ToSend[++ToSendMax] = 0x1D;
1e262141 937
938 for(i = 0; i < len; i++) {
1e262141 939 uint8_t b = cmd[i];
645c960f
MHS		 940 ToSend[++ToSendMax] = encode4Bits(b & 0xF); //Least significant half
941 ToSend[++ToSendMax] = encode4Bits((b >>4) & 0xF);//Most significant half
1e262141 942 }
1e262141 943
944 // Send EOF
645c960f 945 ToSend[++ToSendMax] = 0xB8;
81012e67 946 //lastProxToAirDuration = 8*ToSendMax - 3*8 - 3*8;//Not counting zeroes in the beginning or end
1e262141 947 // Convert from last byte pos to length
948 ToSendMax++;
949}
950
951// Only SOF
952static void CodeIClassTagSOF()
953{
81012e67
MHS		 954 //So far a dummy implementation, not used
955 //int lastProxToAirDuration =0;
1e262141 956
81012e67 957 ToSendReset();
1e262141 958 // Send SOF
645c960f 959 ToSend[++ToSendMax] = 0x1D;
81012e67
MHS		 960// lastProxToAirDuration = 8*ToSendMax - 3*8;//Not counting zeroes in the beginning
961
1e262141 962 // Convert from last byte pos to length
963 ToSendMax++;
964}
b67f7ec3
MHS		 965#define MODE_SIM_CSN 0
966#define MODE_EXIT_AFTER_MAC 1
967#define MODE_FULLSIM 2
55eaed8f 968
b67f7ec3 969int doIClassSimulation(int simulationMode, uint8_t *reader_mac_buf);
ff7bb4ef
MHS		 970/**
971 * @brief SimulateIClass simulates an iClass card.
972 * @param arg0 type of simulation
973 * - 0 uses the first 8 bytes in usb data as CSN
974 * - 2 "dismantling iclass"-attack. This mode iterates through all CSN's specified
975 * in the usb data. This mode collects MAC from the reader, in order to do an offline
976 * attack on the keys. For more info, see "dismantling iclass" and proxclone.com.
977 * - Other : Uses the default CSN (031fec8af7ff12e0)
978 * @param arg1 - number of CSN's contained in datain (applicable for mode 2 only)
979 * @param arg2
980 * @param datain
981 */
982void SimulateIClass(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain)
1e262141 983{
ff7bb4ef
MHS		 984 uint32_t simType = arg0;
985 uint32_t numberOfCSNS = arg1;
7cc204bf 986 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1e262141 987
ff7bb4ef 988 // Enable and clear the trace
3000dc4e 989 clear_trace();
810f5379 990 set_tracing(TRUE);
991
b67f7ec3
MHS		 992 //Use the emulator memory for SIM
993 uint8_t *emulator = BigBuf_get_EM_addr();
81cd0474 994
ff7bb4ef
MHS		 995 if(simType == 0) {
996 // Use the CSN from commandline
b67f7ec3
MHS		 997 memcpy(emulator, datain, 8);
998 doIClassSimulation(MODE_SIM_CSN,NULL);
ff7bb4ef
MHS		 999 }else if(simType == 1)
1000 {
b67f7ec3
MHS		 1001 //Default CSN
1002 uint8_t csn_crc[] = { 0x03, 0x1f, 0xec, 0x8a, 0xf7, 0xff, 0x12, 0xe0, 0x00, 0x00 };
1003 // Use the CSN from commandline
1004 memcpy(emulator, csn_crc, 8);
1005 doIClassSimulation(MODE_SIM_CSN,NULL);
ff7bb4ef
MHS		 1006 }
1007 else if(simType == 2)
1008 {
9f6e9d15 1009
7b941c8d 1010 uint8_t mac_responses[USB_CMD_DATA_SIZE] = { 0 };
a501c82b 1011 Dbprintf("Going into attack mode, %d CSNS sent", numberOfCSNS);
ff7bb4ef
MHS		 1012 // In this mode, a number of csns are within datain. We'll simulate each one, one at a time
1013 // in order to collect MAC's from the reader. This can later be used in an offlne-attack
1014 // in order to obtain the keys, as in the "dismantling iclass"-paper.
9f6e9d15
MHS		 1015 int i = 0;
1016 for( ; i < numberOfCSNS && i*8+8 < USB_CMD_DATA_SIZE; i++)
ff7bb4ef
MHS		 1017 {
1018 // The usb data is 512 bytes, fitting 65 8-byte CSNs in there.
1019
b67f7ec3
MHS		 1020 memcpy(emulator, datain+(i*8), 8);
1021 if(doIClassSimulation(MODE_EXIT_AFTER_MAC,mac_responses+i*8))
f83cc126 1022 {
645c960f 1023 cmd_send(CMD_ACK,CMD_SIMULATE_TAG_ICLASS,i,0,mac_responses,i*8);
f83cc126
MHS		 1024 return; // Button pressed
1025 }
ff7bb4ef 1026 }
9f6e9d15
MHS		 1027 cmd_send(CMD_ACK,CMD_SIMULATE_TAG_ICLASS,i,0,mac_responses,i*8);
1028
b67f7ec3
MHS		 1029 }else if(simType == 3){
1030 //This is 'full sim' mode, where we use the emulator storage for data.
1031 doIClassSimulation(MODE_FULLSIM, NULL);
81012e67
MHS		 1032 }
1033 else{
ff7bb4ef
MHS		 1034 // We may want a mode here where we hardcode the csns to use (from proxclone).
1035 // That will speed things up a little, but not required just yet.
1036 Dbprintf("The mode is not implemented, reserved for future use");
1037 }
9f6e9d15 1038 Dbprintf("Done...");
5ee53a0e 1039 set_tracing(FALSE);
ff7bb4ef 1040}
c8387e85
MHS		 1041void AppendCrc(uint8_t* data, int len)
1042{
1043 ComputeCrc14443(CRC_ICLASS,data,len,data+len,data+len+1);
1044}
b67f7ec3 1045
ff7bb4ef
MHS		 1046/**
1047 * @brief Does the actual simulation
1048 * @param csn - csn to use
1049 * @param breakAfterMacReceived if true, returns after reader MAC has been received.
1050 */
b67f7ec3 1051int doIClassSimulation( int simulationMode, uint8_t *reader_mac_buf)
ff7bb4ef 1052{
b67f7ec3
MHS		 1053 // free eventually allocated BigBuf memory
1054 BigBuf_free_keep_EM();
55eaed8f 1055
61fe9073
MHS		 1056 State cipher_state;
1057// State cipher_state_reserve;
b67f7ec3
MHS		 1058 uint8_t *csn = BigBuf_get_EM_addr();
1059 uint8_t *emulator = csn;
1060 uint8_t sof_data[] = { 0x0F} ;
1e262141 1061 // CSN followed by two CRC bytes
b67f7ec3
MHS		 1062 uint8_t anticoll_data[10] = { 0 };
1063 uint8_t csn_data[10] = { 0 };
1064 memcpy(csn_data,csn,sizeof(csn_data));
f83cc126 1065 Dbprintf("Simulating CSN %02x%02x%02x%02x%02x%02x%02x%02x",csn[0],csn[1],csn[2],csn[3],csn[4],csn[5],csn[6],csn[7]);
1e262141 1066
1e262141 1067 // Construct anticollision-CSN
b67f7ec3 1068 rotateCSN(csn_data,anticoll_data);
1e262141 1069
1070 // Compute CRC on both CSNs
b67f7ec3
MHS		 1071 ComputeCrc14443(CRC_ICLASS, anticoll_data, 8, &anticoll_data[8], &anticoll_data[9]);
1072 ComputeCrc14443(CRC_ICLASS, csn_data, 8, &csn_data[8], &csn_data[9]);
1073
61fe9073 1074 uint8_t diversified_key[8] = { 0 };
b67f7ec3
MHS		 1075 // e-Purse
1076 uint8_t card_challenge_data[8] = { 0x00 };
1077 if(simulationMode == MODE_FULLSIM)
1078 {
e5cd4ee4
MHS		 1079 //The diversified key should be stored on block 3
1080 //Get the diversified key from emulator memory
1081 memcpy(diversified_key, emulator+(8*3),8);
1082
b67f7ec3
MHS		 1083 //Card challenge, a.k.a e-purse is on block 2
1084 memcpy(card_challenge_data,emulator + (8 * 2) , 8);
61fe9073 1085 //Precalculate the cipher state, feeding it the CC
e5cd4ee4
MHS		 1086 cipher_state = opt_doTagMAC_1(card_challenge_data,diversified_key);
1087
b67f7ec3 1088 }
1e262141 1089
ff7bb4ef 1090 int exitLoop = 0;
1e262141 1091 // Reader 0a
1092 // Tag 0f
1093 // Reader 0c
1094 // Tag anticoll. CSN
1095 // Reader 81 anticoll. CSN
1096 // Tag CSN
1097
55eaed8f 1098 uint8_t *modulated_response;
b19caaef 1099 int modulated_response_size = 0;
55eaed8f
MHS		 1100 uint8_t* trace_data = NULL;
1101 int trace_data_size = 0;
1e262141 1102
b67f7ec3 1103
645c960f 1104 // Respond SOF -- takes 1 bytes
b67f7ec3
MHS		 1105 uint8_t *resp_sof = BigBuf_malloc(2);
1106 int resp_sof_Len;
1e262141 1107
1108 // Anticollision CSN (rotated CSN)
645c960f 1109 // 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
b67f7ec3
MHS		 1110 uint8_t *resp_anticoll = BigBuf_malloc(28);
1111 int resp_anticoll_len;
1e262141 1112
1113 // CSN
645c960f 1114 // 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
b67f7ec3
MHS		 1115 uint8_t *resp_csn = BigBuf_malloc(30);
1116 int resp_csn_len;
1e262141 1117
1118 // e-Purse
b3cc5f29 1119 // 18: Takes 2 bytes for SOF/EOF and 8 * 2 = 16 bytes (2 bytes/bit)
b67f7ec3
MHS		 1120 uint8_t *resp_cc = BigBuf_malloc(20);
1121 int resp_cc_len;
1e262141 1122
f71f4deb 1123 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1e262141 1124 int len;
1125
1e262141 1126 // Prepare card messages
1127 ToSendMax = 0;
1128
1129 // First card answer: SOF
1130 CodeIClassTagSOF();
b67f7ec3 1131 memcpy(resp_sof, ToSend, ToSendMax); resp_sof_Len = ToSendMax;
1e262141 1132
1133 // Anticollision CSN
b67f7ec3
MHS		 1134 CodeIClassTagAnswer(anticoll_data, sizeof(anticoll_data));
1135 memcpy(resp_anticoll, ToSend, ToSendMax); resp_anticoll_len = ToSendMax;
1e262141 1136
1137 // CSN
b67f7ec3
MHS		 1138 CodeIClassTagAnswer(csn_data, sizeof(csn_data));
1139 memcpy(resp_csn, ToSend, ToSendMax); resp_csn_len = ToSendMax;
1e262141 1140
1141 // e-Purse
b67f7ec3
MHS		 1142 CodeIClassTagAnswer(card_challenge_data, sizeof(card_challenge_data));
1143 memcpy(resp_cc, ToSend, ToSendMax); resp_cc_len = ToSendMax;
1e262141 1144
b19caaef 1145 //This is used for responding to READ-block commands or other data which is dynamically generated
c8387e85
MHS		 1146 //First the 'trace'-data, not encoded for FPGA
1147 uint8_t *data_generic_trace = BigBuf_malloc(8 + 2);//8 bytes data + 2byte CRC is max tag answer
1148 //Then storage for the modulated data
1149 //Each bit is doubled when modulated for FPGA, and we also have SOF and EOF (2 bytes)
1150 uint8_t *data_response = BigBuf_malloc( (8+2) * 2 + 2);
e3dc1e4c
MHS		 1151
1152 // Start from off (no field generated)
fa541aca
MHS		 1153 //FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1154 //SpinDelay(200);
1155 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1156 SpinDelay(100);
1157 StartCountSspClk();
1e262141 1158 // We need to listen to the high-frequency, peak-detected path.
1159 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1160 FpgaSetupSsc();
1161
1162 // To control where we are in the protocol
1e262141 1163 int cmdsRecvd = 0;
81012e67
MHS		 1164 uint32_t time_0 = GetCountSspClk();
1165 uint32_t t2r_time =0;
1166 uint32_t r2t_time =0;
912a3e94 1167
1e262141 1168 LED_A_ON();
f83cc126 1169 bool buttonPressed = false;
e5cd4ee4 1170 uint8_t response_delay = 1;
ff7bb4ef 1171 while(!exitLoop) {
e5cd4ee4 1172 response_delay = 1;
1e262141 1173 LED_B_OFF();
e3dc1e4c
MHS		 1174 //Signal tracer
1175 // Can be used to get a trigger for an oscilloscope..
1176 LED_C_OFF();
1177
1e262141 1178 if(!GetIClassCommandFromReader(receivedCmd, &len, 100)) {
f83cc126 1179 buttonPressed = true;
1e262141 1180 break;
81cd0474 1181 }
81012e67 1182 r2t_time = GetCountSspClk();
e3dc1e4c
MHS		 1183 //Signal tracer
1184 LED_C_ON();
1e262141 1185
81cd0474 1186 // Okay, look at the command now.
b67f7ec3 1187 if(receivedCmd[0] == ICLASS_CMD_ACTALL ) {
1e262141 1188 // Reader in anticollission phase
b67f7ec3
MHS		 1189 modulated_response = resp_sof; modulated_response_size = resp_sof_Len; //order = 1;
1190 trace_data = sof_data;
1191 trace_data_size = sizeof(sof_data);
1192 } else if(receivedCmd[0] == ICLASS_CMD_READ_OR_IDENTIFY && len == 1) {
1e262141 1193 // Reader asks for anticollission CSN
b67f7ec3
MHS		 1194 modulated_response = resp_anticoll; modulated_response_size = resp_anticoll_len; //order = 2;
1195 trace_data = anticoll_data;
1196 trace_data_size = sizeof(anticoll_data);
1e262141 1197 //DbpString("Reader requests anticollission CSN:");
b67f7ec3 1198 } else if(receivedCmd[0] == ICLASS_CMD_SELECT) {
1e262141 1199 // Reader selects anticollission CSN.
1200 // Tag sends the corresponding real CSN
b67f7ec3
MHS		 1201 modulated_response = resp_csn; modulated_response_size = resp_csn_len; //order = 3;
1202 trace_data = csn_data;
1203 trace_data_size = sizeof(csn_data);
1e262141 1204 //DbpString("Reader selects anticollission CSN:");
b67f7ec3 1205 } else if(receivedCmd[0] == ICLASS_CMD_READCHECK_KD) {
1e262141 1206 // Read e-purse (88 02)
b67f7ec3
MHS		 1207 modulated_response = resp_cc; modulated_response_size = resp_cc_len; //order = 4;
1208 trace_data = card_challenge_data;
1209 trace_data_size = sizeof(card_challenge_data);
1e262141 1210 LED_B_ON();
b67f7ec3 1211 } else if(receivedCmd[0] == ICLASS_CMD_CHECK) {
1e262141 1212 // Reader random and reader MAC!!!
b67f7ec3 1213 if(simulationMode == MODE_FULLSIM)
61fe9073
MHS		 1214 {
1215 //NR, from reader, is in receivedCmd +1
1216 opt_doTagMAC_2(cipher_state,receivedCmd+1,data_generic_trace,diversified_key);
1217
b19caaef 1218 trace_data = data_generic_trace;
b67f7ec3
MHS		 1219 trace_data_size = 4;
1220 CodeIClassTagAnswer(trace_data , trace_data_size);
1221 memcpy(data_response, ToSend, ToSendMax);
1222 modulated_response = data_response;
1223 modulated_response_size = ToSendMax;
e5cd4ee4 1224 response_delay = 0;//We need to hurry here...
10a8875c 1225 //exitLoop = true;
b67f7ec3
MHS		 1226 }else
1227 { //Not fullsim, we don't respond
f38a1528 1228 // We do not know what to answer, so lets keep quiet
b67f7ec3 1229 modulated_response = resp_sof; modulated_response_size = 0;
55eaed8f
MHS		 1230 trace_data = NULL;
1231 trace_data_size = 0;
b67f7ec3 1232 if (simulationMode == MODE_EXIT_AFTER_MAC){
ff7bb4ef 1233 // dbprintf:ing ...
f5ed4d12 1234 Dbprintf("CSN: %02x %02x %02x %02x %02x %02x %02x %02x"
1235 ,csn[0],csn[1],csn[2],csn[3],csn[4],csn[5],csn[6],csn[7]);
ff7bb4ef 1236 Dbprintf("RDR: (len=%02d): %02x %02x %02x %02x %02x %02x %02x %02x %02x",len,
a501c82b 1237 receivedCmd[0], receivedCmd[1], receivedCmd[2],
ff7bb4ef
MHS		 1238 receivedCmd[3], receivedCmd[4], receivedCmd[5],
1239 receivedCmd[6], receivedCmd[7], receivedCmd[8]);
9f6e9d15
MHS		 1240 if (reader_mac_buf != NULL)
1241 {
1242 memcpy(reader_mac_buf,receivedCmd+1,8);
1243 }
ff7bb4ef
MHS		 1244 exitLoop = true;
1245 }
ff7bb4ef 1246 }
b67f7ec3
MHS		 1247
1248 } else if(receivedCmd[0] == ICLASS_CMD_HALT && len == 1) {
1e262141 1249 // Reader ends the session
b67f7ec3 1250 modulated_response = resp_sof; modulated_response_size = 0; //order = 0;
55eaed8f
MHS		 1251 trace_data = NULL;
1252 trace_data_size = 0;
b67f7ec3
MHS		 1253 } else if(simulationMode == MODE_FULLSIM && receivedCmd[0] == ICLASS_CMD_READ_OR_IDENTIFY && len == 4){
1254 //Read block
1255 uint16_t blk = receivedCmd[1];
c8387e85
MHS		 1256 //Take the data...
1257 memcpy(data_generic_trace, emulator+(blk << 3),8);
1258 //Add crc
1259 AppendCrc(data_generic_trace, 8);
1260 trace_data = data_generic_trace;
1261 trace_data_size = 10;
1262 CodeIClassTagAnswer(trace_data , trace_data_size);
1263 memcpy(data_response, ToSend, ToSendMax);
1264 modulated_response = data_response;
1265 modulated_response_size = ToSendMax;
1266 }else if(receivedCmd[0] == ICLASS_CMD_UPDATE && simulationMode == MODE_FULLSIM)
1267 {//Probably the reader wants to update the nonce. Let's just ignore that for now.
1268 // OBS! If this is implemented, don't forget to regenerate the cipher_state
1269 //We're expected to respond with the data+crc, exactly what's already in the receivedcmd
1270 //receivedcmd is now UPDATE 1b | ADDRESS 1b| DATA 8b| Signature 4b or CRC 2b|
1271
1272 //Take the data...
1273 memcpy(data_generic_trace, receivedCmd+2,8);
1274 //Add crc
1275 AppendCrc(data_generic_trace, 8);
1276 trace_data = data_generic_trace;
1277 trace_data_size = 10;
b67f7ec3
MHS		 1278 CodeIClassTagAnswer(trace_data , trace_data_size);
1279 memcpy(data_response, ToSend, ToSendMax);
1280 modulated_response = data_response;
1281 modulated_response_size = ToSendMax;
1282 }
b19caaef
MHS		 1283 else if(receivedCmd[0] == ICLASS_CMD_PAGESEL)
1284 {//Pagesel
1285 //Pagesel enables to select a page in the selected chip memory and return its configuration block
1286 //Chips with a single page will not answer to this command
1287 // It appears we're fine ignoring this.
1288 //Otherwise, we should answer 8bytes (block) + 2bytes CRC
1289 }
b67f7ec3 1290 else {
17cba269 1291 //#db# Unknown command received from reader (len=5): 26 1 0 f6 a 44 44 44 44
1e262141 1292 // Never seen this command before
1293 Dbprintf("Unknown command received from reader (len=%d): %x %x %x %x %x %x %x %x %x",
1294 len,
1295 receivedCmd[0], receivedCmd[1], receivedCmd[2],
1296 receivedCmd[3], receivedCmd[4], receivedCmd[5],
1297 receivedCmd[6], receivedCmd[7], receivedCmd[8]);
1298 // Do not respond
b67f7ec3 1299 modulated_response = resp_sof; modulated_response_size = 0; //order = 0;
55eaed8f
MHS		 1300 trace_data = NULL;
1301 trace_data_size = 0;
1e262141 1302 }
1303
81012e67
MHS		 1304 if(cmdsRecvd > 100) {
1305 //DbpString("100 commands later...");
9f6e9d15 1306 //break;
1e262141 1307 }
1308 else {
1309 cmdsRecvd++;
1310 }
55eaed8f 1311 /**
6b038d19 1312 A legit tag has about 380us delay between reader EOT and tag SOF.
55eaed8f
MHS		 1313 **/
1314 if(modulated_response_size > 0) {
e5cd4ee4 1315 SendIClassAnswer(modulated_response, modulated_response_size, response_delay);
81012e67 1316 t2r_time = GetCountSspClk();
81cd0474 1317 }
f83cc126 1318
81cd0474 1319 if (tracing) {
a501c82b 1320 uint8_t parity[MAX_PARITY_SIZE];
1321 GetParity(receivedCmd, len, parity);
1322 LogTrace(receivedCmd,len, (r2t_time-time_0)<< 4, (r2t_time-time_0) << 4, parity, TRUE);
17cba269 1323
55eaed8f
MHS		 1324 if (trace_data != NULL) {
1325 GetParity(trace_data, trace_data_size, parity);
1326 LogTrace(trace_data, trace_data_size, (t2r_time-time_0) << 4, (t2r_time-time_0) << 4, parity, FALSE);
17cba269 1327 }
810f5379 1328 if(!tracing)
81012e67 1329 DbpString("Trace full");
81012e67 1330
81cd0474 1331 }
81cd0474 1332 }
1e262141 1333
4a71da5a 1334 LEDsoff();
1335
f83cc126 1336 if(buttonPressed)
f83cc126 1337 DbpString("Button pressed");
4a71da5a 1338
f83cc126 1339 return buttonPressed;
1e262141 1340}
1341
1342static int SendIClassAnswer(uint8_t *resp, int respLen, int delay)
1343{
e3dc1e4c 1344 int i = 0, d=0;//, u = 0, d = 0;
1e262141 1345 uint8_t b = 0;
e3dc1e4c 1346
645c960f
MHS		 1347 //FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K);
1348 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K_8BIT);
e3dc1e4c 1349
1e262141 1350 AT91C_BASE_SSC->SSC_THR = 0x00;
1351 FpgaSetupSsc();
e3dc1e4c
MHS		 1352 while(!BUTTON_PRESS()) {
1353 if((AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)){
1354 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1e262141 1355 }
e3dc1e4c
MHS		 1356 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)){
1357 b = 0x00;
1e262141 1358 if(d < delay) {
1e262141 1359 d++;
1360 }
e3dc1e4c
MHS		 1361 else {
1362 if( i < respLen){
1363 b = resp[i];
1364 //Hack
1365 //b = 0xAC;
1366 }
1367 i++;
1e262141 1368 }
1369 AT91C_BASE_SSC->SSC_THR = b;
1e262141 1370 }
e3dc1e4c 1371
645c960f
MHS		 1372// if (i > respLen +4) break;
1373 if (i > respLen +1) break;
1e262141 1374 }
1375
1376 return 0;
1377}
1378
1379/// THE READER CODE
1380
1381//-----------------------------------------------------------------------------
1382// Transmit the command (to the tag) that was placed in ToSend[].
1383//-----------------------------------------------------------------------------
1384static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait)
1385{
5f5254d6 1386 int c;
1387 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1388 AT91C_BASE_SSC->SSC_THR = 0x00;
1389 FpgaSetupSsc();
1e262141 1390
5f5254d6 1391 if (wait) {
1392 if(*wait < 10) *wait = 10;
1393
1394 for(c = 0; c < *wait;) {
1395 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1396 AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing!
1397 c++;
1398 }
1399 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1400 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1401 (void)r;
1402 }
1403 WDT_HIT();
1404 }
1405 }
f5ed4d12 1406
1407
5f5254d6 1408 uint8_t sendbyte;
1409 bool firstpart = TRUE;
1410 c = 0;
1e262141 1411 for(;;) {
1412 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1413
1414 // DOUBLE THE SAMPLES!
1415 if(firstpart) {
1416 sendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4);
1417 }
1418 else {
1419 sendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4);
1420 c++;
1421 }
1422 if(sendbyte == 0xff) {
1423 sendbyte = 0xfe;
1424 }
1425 AT91C_BASE_SSC->SSC_THR = sendbyte;
1426 firstpart = !firstpart;
1427
1428 if(c >= len) {
1429 break;
1430 }
1431 }
1432 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1433 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1434 (void)r;
1435 }
1436 WDT_HIT();
1437 }
5f5254d6 1438 if (samples && wait) *samples = (c + *wait) << 3;
1e262141 1439}
1440
1441
1442//-----------------------------------------------------------------------------
1443// Prepare iClass reader command to send to FPGA
1444//-----------------------------------------------------------------------------
1445void CodeIClassCommand(const uint8_t * cmd, int len)
1446{
1447 int i, j, k;
1448 uint8_t b;
1449
1450 ToSendReset();
1451
1452 // Start of Communication: 1 out of 4
1453 ToSend[++ToSendMax] = 0xf0;
1454 ToSend[++ToSendMax] = 0x00;
1455 ToSend[++ToSendMax] = 0x0f;
1456 ToSend[++ToSendMax] = 0x00;
1457
1458 // Modulate the bytes
1459 for (i = 0; i < len; i++) {
1460 b = cmd[i];
1461 for(j = 0; j < 4; j++) {
1462 for(k = 0; k < 4; k++) {
e3dc1e4c
MHS		 1463 if(k == (b & 3)) {
1464 ToSend[++ToSendMax] = 0x0f;
1465 }
1466 else {
1467 ToSend[++ToSendMax] = 0x00;
1468 }
1e262141 1469 }
1470 b >>= 2;
1471 }
1472 }
1473
1474 // End of Communication
1475 ToSend[++ToSendMax] = 0x00;
1476 ToSend[++ToSendMax] = 0x00;
1477 ToSend[++ToSendMax] = 0xf0;
1478 ToSend[++ToSendMax] = 0x00;
1479
1480 // Convert from last character reference to length
1481 ToSendMax++;
1482}
1483
1484void ReaderTransmitIClass(uint8_t* frame, int len)
1485{
1486 int wait = 0;
1487 int samples = 0;
1e262141 1488
1489 // This is tied to other size changes
1e262141 1490 CodeIClassCommand(frame,len);
1491
1492 // Select the card
1493 TransmitIClassCommand(ToSend, ToSendMax, &samples, &wait);
1494 if(trigger)
1495 LED_A_ON();
1496
1497 // Store reader command in buffer
6a1f2d82 1498 if (tracing) {
a501c82b 1499 uint8_t par[MAX_PARITY_SIZE];
1500 GetParity(frame, len, par);
1501 LogTrace(frame, len, rsamples, rsamples, par, TRUE);
1502 }
1e262141 1503}
1504
1505//-----------------------------------------------------------------------------
1506// Wait a certain time for tag response
1507// If a response is captured return TRUE
1508// If it takes too long return FALSE
1509//-----------------------------------------------------------------------------
1510static int GetIClassAnswer(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed) //uint8_t *buffer
1511{
1512 // buffer needs to be 512 bytes
1513 int c;
1514
1515 // Set FPGA mode to "reader listen mode", no modulation (listen
1516 // only, since we are receiving, not transmitting).
1517 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1518
1519 // Now get the answer from the card
1520 Demod.output = receivedResponse;
1521 Demod.len = 0;
1522 Demod.state = DEMOD_UNSYNCD;
1523
1524 uint8_t b;
1525 if (elapsed) *elapsed = 0;
1526
1527 bool skip = FALSE;
1528
1529 c = 0;
1530 for(;;) {
1531 WDT_HIT();
1532
95e63594 1533 if(BUTTON_PRESS()) return FALSE;
1e262141 1534
1535 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1536 AT91C_BASE_SSC->SSC_THR = 0x00; // To make use of exact timing of next command from reader!!
1537 if (elapsed) (*elapsed)++;
1538 }
1539 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1540 if(c < timeout) { c++; } else { return FALSE; }
1541 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1542 skip = !skip;
1543 if(skip) continue;
95e63594 1544
1e262141 1545 if(ManchesterDecoding(b & 0x0f)) {
1546 *samples = c << 3;
1547 return TRUE;
1548 }
1549 }
1550 }
1551}
1552
1553int ReaderReceiveIClass(uint8_t* receivedAnswer)
1554{
1555 int samples = 0;
1556 if (!GetIClassAnswer(receivedAnswer,160,&samples,0)) return FALSE;
7bc95e2e 1557 rsamples += samples;
6a1f2d82 1558 if (tracing) {
1559 uint8_t parity[MAX_PARITY_SIZE];
1560 GetParity(receivedAnswer, Demod.len, parity);
1561 LogTrace(receivedAnswer,Demod.len,rsamples,rsamples,parity,FALSE);
a501c82b 1562 }
1e262141 1563 if(samples == 0) return FALSE;
1564 return Demod.len;
1565}
1566
f38a1528 1567void setupIclassReader()
1568{
1569 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1570 // Reset trace buffer
3000dc4e 1571 clear_trace();
810f5379 1572 set_tracing(TRUE);
1573
f38a1528 1574 // Setup SSC
1575 FpgaSetupSsc();
1576 // Start from off (no field generated)
1577 // Signal field is off with the appropriate LED
1578 LED_D_OFF();
1579 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1580 SpinDelay(200);
1581
1582 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1583
1584 // Now give it time to spin up.
1585 // Signal field is on with the appropriate LED
1586 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1587 SpinDelay(200);
1588 LED_A_ON();
1589
1590}
1591
e98572a1 1592bool sendCmdGetResponseWithRetries(uint8_t* command, size_t cmdsize, uint8_t* resp, uint8_t expected_size, uint8_t retries)
d3a22c7d 1593{
1594 while(retries-- > 0)
1595 {
1596 ReaderTransmitIClass(command, cmdsize);
1597 if(expected_size == ReaderReceiveIClass(resp)){
e98572a1 1598 return true;
d3a22c7d 1599 }
1600 }
e98572a1 1601 return false;//Error
d3a22c7d 1602}
1603
1604/**
1605 * @brief Talks to an iclass tag, sends the commands to get CSN and CC.
1606 * @param card_data where the CSN and CC are stored for return
1607 * @return 0 = fail
1608 * 1 = Got CSN
1609 * 2 = Got CSN and CC
1610 */
e98572a1 1611uint8_t handshakeIclassTag_ext(uint8_t *card_data, bool use_credit_key)
d3a22c7d 1612{
1613 static uint8_t act_all[] = { 0x0a };
e98572a1 1614 //static uint8_t identify[] = { 0x0c };
1615 static uint8_t identify[] = { 0x0c, 0x00, 0x73, 0x33 };
d3a22c7d 1616 static uint8_t select[] = { 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
e98572a1 1617 static uint8_t readcheck_cc[]= { 0x88, 0x02 };
1618 if (use_credit_key)
1619 readcheck_cc[0] = 0x18;
1620 else
1621 readcheck_cc[0] = 0x88;
caaf9618 1622
f71f4deb 1623 uint8_t resp[ICLASS_BUFFER_SIZE];
d3a22c7d 1624
1625 uint8_t read_status = 0;
1626
1627 // Send act_all
1628 ReaderTransmitIClass(act_all, 1);
1629 // Card present?
1630 if(!ReaderReceiveIClass(resp)) return read_status;//Fail
1631 //Send Identify
1632 ReaderTransmitIClass(identify, 1);
1633 //We expect a 10-byte response here, 8 byte anticollision-CSN and 2 byte CRC
1634 uint8_t len = ReaderReceiveIClass(resp);
1635 if(len != 10) return read_status;//Fail
1636
1637 //Copy the Anti-collision CSN to our select-packet
1638 memcpy(&select[1],resp,8);
1639 //Select the card
1640 ReaderTransmitIClass(select, sizeof(select));
1641 //We expect a 10-byte response here, 8 byte CSN and 2 byte CRC
1642 len = ReaderReceiveIClass(resp);
1643 if(len != 10) return read_status;//Fail
1644
1645 //Success - level 1, we got CSN
1646 //Save CSN in response data
1647 memcpy(card_data,resp,8);
1648
1649 //Flag that we got to at least stage 1, read CSN
1650 read_status = 1;
1651
1652 // Card selected, now read e-purse (cc)
1653 ReaderTransmitIClass(readcheck_cc, sizeof(readcheck_cc));
1654 if(ReaderReceiveIClass(resp) == 8) {
1655 //Save CC (e-purse) in response data
1656 memcpy(card_data+8,resp,8);
caaf9618 1657 read_status++;
d3a22c7d 1658 }
1659
1660 return read_status;
1661}
e98572a1 1662uint8_t handshakeIclassTag(uint8_t *card_data){
1663 return handshakeIclassTag_ext(card_data, false);
1664}
d3a22c7d 1665
caaf9618 1666
1e262141 1667// Reader iClass Anticollission
1668void ReaderIClass(uint8_t arg0) {
f38a1528 1669
83602aff
MHS		 1670 uint8_t card_data[6 * 8]={0};
1671 memset(card_data, 0xFF, sizeof(card_data));
f38a1528 1672 uint8_t last_csn[8]={0};
6a1f2d82 1673
caaf9618
MHS		 1674 //Read conf block CRC(0x01) => 0xfa 0x22
1675 uint8_t readConf[] = { ICLASS_CMD_READ_OR_IDENTIFY,0x01, 0xfa, 0x22};
1676 //Read conf block CRC(0x05) => 0xde 0x64
1677 uint8_t readAA[] = { ICLASS_CMD_READ_OR_IDENTIFY,0x05, 0xde, 0x64};
1678
1679
f38a1528 1680 int read_status= 0;
caaf9618 1681 uint8_t result_status = 0;
f38a1528 1682 bool abort_after_read = arg0 & FLAG_ICLASS_READER_ONLY_ONCE;
8949bb5d 1683 bool try_once = arg0 & FLAG_ICLASS_READER_ONE_TRY;
e98572a1 1684 bool use_credit_key = false;
1685 if (arg0 & FLAG_ICLASS_READER_CEDITKEY)
1686 use_credit_key = true;
3000dc4e 1687 set_tracing(TRUE);
f38a1528 1688 setupIclassReader();
1689
8949bb5d 1690 uint16_t tryCnt=0;
f38a1528 1691 while(!BUTTON_PRESS())
1692 {
8949bb5d 1693 if (try_once && tryCnt > 5) break;
810f5379 1694
8949bb5d 1695 tryCnt++;
810f5379 1696
3000dc4e 1697 if(!tracing) {
d3a22c7d 1698 DbpString("Trace full");
1699 break;
1700 }
c8dd9b09 1701 WDT_HIT();
f38a1528 1702
e98572a1 1703 read_status = handshakeIclassTag_ext(card_data, use_credit_key);
d3a22c7d 1704
1705 if(read_status == 0) continue;
caaf9618
MHS		 1706 if(read_status == 1) result_status = FLAG_ICLASS_READER_CSN;
1707 if(read_status == 2) result_status = FLAG_ICLASS_READER_CSN|FLAG_ICLASS_READER_CC;
1708
1709 // handshakeIclass returns CSN|CC, but the actual block
1710 // layout is CSN|CONFIG|CC, so here we reorder the data,
1711 // moving CC forward 8 bytes
1712 memcpy(card_data+16,card_data+8, 8);
1713 //Read block 1, config
1714 if(arg0 & FLAG_ICLASS_READER_CONF)
1715 {
1716 if(sendCmdGetResponseWithRetries(readConf, sizeof(readConf),card_data+8, 10, 10))
caaf9618
MHS		 1717 {
1718 result_status |= FLAG_ICLASS_READER_CONF;
e98572a1 1719 } else {
1720 Dbprintf("Failed to dump config block");
caaf9618
MHS		 1721 }
1722 }
f38a1528 1723
caaf9618
MHS		 1724 //Read block 5, AA
1725 if(arg0 & FLAG_ICLASS_READER_AA){
1726 if(sendCmdGetResponseWithRetries(readAA, sizeof(readAA),card_data+(8*4), 10, 10))
1727 {
caaf9618 1728 result_status |= FLAG_ICLASS_READER_AA;
e98572a1 1729 } else {
1730 //Dbprintf("Failed to dump AA block");
caaf9618
MHS		 1731 }
1732 }
1733
1734 // 0 : CSN
b67f7ec3 1735 // 1 : Configuration
caaf9618
MHS		 1736 // 2 : e-purse
1737 // (3,4 write-only, kc and kd)
b67f7ec3
MHS		 1738 // 5 Application issuer area
1739 //
1740 //Then we can 'ship' back the 8 * 5 bytes of data,
1741 // with 0xFF:s in block 3 and 4.
1742
f38a1528 1743 LED_B_ON();
1744 //Send back to client, but don't bother if we already sent this
1745 if(memcmp(last_csn, card_data, 8) != 0)
d3a22c7d 1746 {
caaf9618
MHS		 1747 // If caller requires that we get CC, continue until we got it
1748 if( (arg0 & read_status & FLAG_ICLASS_READER_CC) || !(arg0 & FLAG_ICLASS_READER_CC))
d3a22c7d 1749 {
caaf9618 1750 cmd_send(CMD_ACK,result_status,0,0,card_data,sizeof(card_data));
d3a22c7d 1751 if(abort_after_read) {
1752 LED_A_OFF();
5ee53a0e 1753 set_tracing(FALSE);
d3a22c7d 1754 return;
1755 }
5ee53a0e 1756 //Save that we already sent this....
1757 memcpy(last_csn, card_data, 8);
d3a22c7d 1758 }
d3a22c7d 1759 }
c8dd9b09 1760 LED_B_OFF();
f38a1528 1761 }
d3a22c7d 1762 cmd_send(CMD_ACK,0,0,0,card_data, 0);
aa41c605 1763 LED_A_OFF();
5ee53a0e 1764 set_tracing(FALSE);
f38a1528 1765}
1766
1767void ReaderIClass_Replay(uint8_t arg0, uint8_t *MAC) {
d3a22c7d 1768
14edfd09 1769 uint8_t card_data[USB_CMD_DATA_SIZE]={0};
d3a22c7d 1770 uint16_t block_crc_LUT[255] = {0};
1771
1772 {//Generate a lookup table for block crc
1773 for(int block = 0; block < 255; block++){
1774 char bl = block;
1775 block_crc_LUT[block] = iclass_crc16(&bl ,1);
1776 }
1777 }
1778 //Dbprintf("Lookup table: %02x %02x %02x" ,block_crc_LUT[0],block_crc_LUT[1],block_crc_LUT[2]);
1779
f38a1528 1780 uint8_t check[] = { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1781 uint8_t read[] = { 0x0c, 0x00, 0x00, 0x00 };
1782
fecd8202 1783 uint16_t crc = 0;
f38a1528 1784 uint8_t cardsize=0;
f38a1528 1785 uint8_t mem=0;
1786
1787 static struct memory_t{
1788 int k16;
1789 int book;
1790 int k2;
1791 int lockauth;
1792 int keyaccess;
1793 } memory;
1794
f71f4deb 1795 uint8_t resp[ICLASS_BUFFER_SIZE];
6a1f2d82 1796
f38a1528 1797 setupIclassReader();
3000dc4e 1798 set_tracing(TRUE);
f38a1528 1799
d3a22c7d 1800 while(!BUTTON_PRESS()) {
1801
1802 WDT_HIT();
39d3ce5d 1803
3000dc4e 1804 if(!tracing) {
f38a1528 1805 DbpString("Trace full");
1806 break;
1807 }
1808
d3a22c7d 1809 uint8_t read_status = handshakeIclassTag(card_data);
1810 if(read_status < 2) continue;
1811
5ee53a0e 1812 //for now replay captured auth (as cc not updated)
1813 memcpy(check+5,MAC,4);
d3a22c7d 1814
e98572a1 1815 if(!sendCmdGetResponseWithRetries(check, sizeof(check),resp, 4, 5))
d3a22c7d 1816 {
5ee53a0e 1817 Dbprintf("Error: Authentication Fail!");
d3a22c7d 1818 continue;
5ee53a0e 1819 }
d3a22c7d 1820
1821 //first get configuration block (block 1)
1822 crc = block_crc_LUT[1];
5ee53a0e 1823 read[1]=1;
1824 read[2] = crc >> 8;
1825 read[3] = crc & 0xff;
d3a22c7d 1826
e98572a1 1827 if(!sendCmdGetResponseWithRetries(read, sizeof(read),resp, 10, 10))
d3a22c7d 1828 {
1829 Dbprintf("Dump config (block 1) failed");
1830 continue;
1831 }
1832
5ee53a0e 1833 mem=resp[5];
1834 memory.k16= (mem & 0x80);
1835 memory.book= (mem & 0x20);
1836 memory.k2= (mem & 0x8);
1837 memory.lockauth= (mem & 0x2);
1838 memory.keyaccess= (mem & 0x1);
f38a1528 1839
d3a22c7d 1840 cardsize = memory.k16 ? 255 : 32;
1841 WDT_HIT();
14edfd09 1842 //Set card_data to all zeroes, we'll fill it with data
1843 memset(card_data,0x0,USB_CMD_DATA_SIZE);
1844 uint8_t failedRead =0;
428d6221 1845 uint32_t stored_data_length =0;
f38a1528 1846 //then loop around remaining blocks
d3a22c7d 1847 for(int block=0; block < cardsize; block++){
1848
1849 read[1]= block;
1850 crc = block_crc_LUT[block];
5ee53a0e 1851 read[2] = crc >> 8;
1852 read[3] = crc & 0xff;
d3a22c7d 1853
e98572a1 1854 if(sendCmdGetResponseWithRetries(read, sizeof(read), resp, 10, 10))
d3a22c7d 1855 {
5ee53a0e 1856 Dbprintf(" %02x: %02x %02x %02x %02x %02x %02x %02x %02x",
1857 block, resp[0], resp[1], resp[2],
1858 resp[3], resp[4], resp[5],
1859 resp[6], resp[7]);
d3a22c7d 1860
14edfd09 1861 //Fill up the buffer
1862 memcpy(card_data+stored_data_length,resp,8);
1863 stored_data_length += 8;
14edfd09 1864 if(stored_data_length +8 > USB_CMD_DATA_SIZE)
1865 {//Time to send this off and start afresh
1866 cmd_send(CMD_ACK,
1867 stored_data_length,//data length
1868 failedRead,//Failed blocks?
1869 0,//Not used ATM
1870 card_data, stored_data_length);
1871 //reset
1872 stored_data_length = 0;
1873 failedRead = 0;
1874 }
5ee53a0e 1875 } else {
14edfd09 1876 failedRead = 1;
1877 stored_data_length +=8;//Otherwise, data becomes misaligned
d3a22c7d 1878 Dbprintf("Failed to dump block %d", block);
f38a1528 1879 }
1880 }
428d6221 1881
14edfd09 1882 //Send off any remaining data
1883 if(stored_data_length > 0)
1884 {
1885 cmd_send(CMD_ACK,
1886 stored_data_length,//data length
1887 failedRead,//Failed blocks?
1888 0,//Not used ATM
1889 card_data, stored_data_length);
1890 }
d3a22c7d 1891 //If we got here, let's break
1892 break;
f38a1528 1893 }
14edfd09 1894 //Signal end of transmission
1895 cmd_send(CMD_ACK,
1896 0,//data length
1897 0,//Failed blocks?
1898 0,//Not used ATM
1899 card_data, 0);
1900
f38a1528 1901 LED_A_OFF();
5ee53a0e 1902 set_tracing(FALSE);
f38a1528 1903}
1904
e98572a1 1905void iClass_ReadCheck(uint8_t blockNo, uint8_t keyType) {
1906 uint8_t readcheck[] = { keyType, blockNo };
1907 uint8_t resp[] = {0,0,0,0,0,0,0,0};
1908 size_t isOK = 0;
1909 isOK = sendCmdGetResponseWithRetries(readcheck, sizeof(readcheck), resp, sizeof(resp), 6);
1910 cmd_send(CMD_ACK,isOK,0,0,0,0);
1911}
1e262141 1912
e98572a1 1913void iClass_Authentication(uint8_t *MAC) {
1914 uint8_t check[] = { ICLASS_CMD_CHECK, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1915 uint8_t resp[ICLASS_BUFFER_SIZE];
1916 memcpy(check+5,MAC,4);
1917 bool isOK;
1918 isOK = sendCmdGetResponseWithRetries(check, sizeof(check), resp, 4, 6);
1919 cmd_send(CMD_ACK,isOK,0,0,0,0);
1920}
1921bool iClass_ReadBlock(uint8_t blockNo, uint8_t *readdata) {
1922 uint8_t readcmd[] = {ICLASS_CMD_READ_OR_IDENTIFY, blockNo, 0x00, 0x00}; //0x88, 0x00 // can i use 0C?
1923 char bl = blockNo;
1924 uint16_t rdCrc = iclass_crc16(&bl, 1);
1925 readcmd[2] = rdCrc >> 8;
1926 readcmd[3] = rdCrc & 0xff;
1927 uint8_t resp[] = {0,0,0,0,0,0,0,0,0,0};
1928 bool isOK = false;
1929
1930 //readcmd[1] = blockNo;
1931 isOK = sendCmdGetResponseWithRetries(readcmd, sizeof(readcmd), resp, 10, 10);
1932 memcpy(readdata, resp, sizeof(resp));
1933
1934 return isOK;
1935}
1e262141 1936
e98572a1 1937void iClass_ReadBlk(uint8_t blockno) {
1938 uint8_t readblockdata[] = {0,0,0,0,0,0,0,0,0,0};
1939 bool isOK = false;
1940 isOK = iClass_ReadBlock(blockno, readblockdata);
1941 cmd_send(CMD_ACK, isOK, 0, 0, readblockdata, 8);
1942}
1e262141 1943
e98572a1 1944void iClass_Dump(uint8_t blockno, uint8_t numblks) {
1945 uint8_t readblockdata[] = {0,0,0,0,0,0,0,0,0,0};
1946 bool isOK = false;
1947 uint8_t blkCnt = 0;
1e262141 1948
e98572a1 1949 BigBuf_free();
1950 uint8_t *dataout = BigBuf_malloc(255*8);
1951 if (dataout == NULL){
1952 Dbprintf("out of memory");
1953 OnError(1);
1954 return;
1955 }
1956 memset(dataout,0xFF,255*8);
1957
1958 for (;blkCnt < numblks; blkCnt++) {
1959 isOK = iClass_ReadBlock(blockno+blkCnt, readblockdata);
1960 if (!isOK || (readblockdata[0] == 0xBB || readblockdata[7] == 0xBB || readblockdata[2] == 0xBB)) { //try again
1961 isOK = iClass_ReadBlock(blockno+blkCnt, readblockdata);
1962 if (!isOK) {
1963 Dbprintf("Block %02X failed to read", blkCnt+blockno);
4ab4336a 1964 break;
1965 }
e98572a1 1966 }
1967 memcpy(dataout+(blkCnt*8),readblockdata,8);
1968 }
1969 //return pointer to dump memory in arg3
1970 cmd_send(CMD_ACK,isOK,blkCnt,BigBuf_max_traceLen(),0,0);
1971 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1972 LEDsoff();
1973 BigBuf_free();
1974}
1975
1976bool iClass_WriteBlock_ext(uint8_t blockNo, uint8_t *data) {
1977 uint8_t write[] = { ICLASS_CMD_UPDATE, blockNo, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1978 //uint8_t readblockdata[10];
1979 //write[1] = blockNo;
1980 memcpy(write+2, data, 12); // data + mac
1981 uint8_t resp[] = {0,0,0,0,0,0,0,0,0,0};
1982 bool isOK;
1983 isOK = sendCmdGetResponseWithRetries(write,sizeof(write),resp,sizeof(resp),10);
1984 if (isOK) {
1985 //Dbprintf("WriteResp: %02X%02X%02X%02X%02X%02X%02X%02X%02X%02X",resp[0],resp[1],resp[2],resp[3],resp[4],resp[5],resp[6],resp[7],resp[8],resp[9]);
1986 if (memcmp(write+2,resp,8)) {
1987 //error try again
1988 isOK = sendCmdGetResponseWithRetries(write,sizeof(write),resp,sizeof(resp),10);
1989 }
1990 }
1991 return isOK;
1992}
1993
1994void iClass_WriteBlock(uint8_t blockNo, uint8_t *data) {
1995 bool isOK = iClass_WriteBlock_ext(blockNo, data);
1996 if (isOK){
1997 Dbprintf("Write block [%02x] successful",blockNo);
f38a1528 1998 }else {
e98572a1 1999 Dbprintf("Write block [%02x] failed",blockNo);
2000 }
2001 cmd_send(CMD_ACK,isOK,0,0,0,0);
2002}
f38a1528 2003
e98572a1 2004void iClass_Clone(uint8_t startblock, uint8_t endblock, uint8_t *data) {
2005 int i;
2006 int written = 0;
2007 int total_block = (endblock - startblock) + 1;
2008 for (i = 0; i < total_block;i++){
2009 // block number
2010 if (iClass_WriteBlock_ext(i+startblock, data+(i*12))){
2011 Dbprintf("Write block [%02x] successful",i + startblock);
2012 written++;
2013 } else {
2014 if (iClass_WriteBlock_ext(i+startblock, data+(i*12))){
2015 Dbprintf("Write block [%02x] successful",i + startblock);
2016 written++;
2017 } else {
2018 Dbprintf("Write block [%02x] failed",i + startblock);
2019 }
1e262141 2020 }
1e262141 2021 }
e98572a1 2022 if (written == total_block)
2023 Dbprintf("Clone complete");
2024 else
2025 Dbprintf("Clone incomplete");
2026
2027 cmd_send(CMD_ACK,1,0,0,0,0);
2028 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2029 LEDsoff();
2030}
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