[proxmark3-svn] / armsrc / util.c

//-----------------------------------------------------------------------------
// Jonathan Westhues, Sept 2005
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// Utility functions used in many places, not specific to any piece of code.
//-----------------------------------------------------------------------------

#include "proxmark3.h"
#include "util.h"
#include "string.h"
#include "apps.h"


void print_result(char *name, uint8_t *buf, size_t len) {
   uint8_t *p = buf;

   if ( len % 16 == 0 ) {
	   for(; p-buf < len; p += 16)
       Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
				name,
				p-buf,
				len,
				p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]
	   );
   }
   else {
   for(; p-buf < len; p += 8)
       Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
   }
}

size_t nbytes(size_t nbits) {
	return (nbits/8)+((nbits%8)>0);
}

uint32_t SwapBits(uint32_t value, int nrbits) {
	int i;
	uint32_t newvalue = 0;
	for(i = 0; i < nrbits; i++) {
		newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
	}
	return newvalue;
}

void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
{
	while (len--) {
		dest[len] = (uint8_t) n;
		n >>= 8;
	}
}

uint64_t bytes_to_num(uint8_t* src, size_t len)
{
	uint64_t num = 0;
	while (len--)
	{
		num = (num << 8) | (*src);
		src++;
	}
	return num;
}

// RotateLeft - Ultralight, Desfire
void rol(uint8_t *data, const size_t len){
    uint8_t first = data[0];
    for (size_t i = 0; i < len-1; i++) {
        data[i] = data[i+1];
    }
    data[len-1] = first;
}
void lsl (uint8_t *data, size_t len) {
    for (size_t n = 0; n < len - 1; n++) {
        data[n] = (data[n] << 1) | (data[n+1] >> 7);
    }
    data[len - 1] <<= 1;
}

int32_t le24toh (uint8_t data[3])
{
    return (data[2] << 16) | (data[1] << 8) | data[0];
}

void LEDsoff()
{
	LED_A_OFF();
	LED_B_OFF();
	LED_C_OFF();
	LED_D_OFF();
}

// LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
void LED(int led, int ms)
{
	if (led & LED_RED)
		LED_C_ON();
	if (led & LED_ORANGE)
		LED_A_ON();
	if (led & LED_GREEN)
		LED_B_ON();
	if (led & LED_RED2)
		LED_D_ON();

	if (!ms)
		return;

	SpinDelay(ms);

	if (led & LED_RED)
		LED_C_OFF();
	if (led & LED_ORANGE)
		LED_A_OFF();
	if (led & LED_GREEN)
		LED_B_OFF();
	if (led & LED_RED2)
		LED_D_OFF();
}


// Determine if a button is double clicked, single clicked,
// not clicked, or held down (for ms || 1sec)
// In general, don't use this function unless you expect a
// double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
int BUTTON_CLICKED(int ms)
{
	// Up to 500ms in between clicks to mean a double click
	int ticks = (48000 * (ms ? ms : 1000)) >> 10;

	// If we're not even pressed, forget about it!
	if (!BUTTON_PRESS())
		return BUTTON_NO_CLICK;

	// Borrow a PWM unit for my real-time clock
	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	// 48 MHz / 1024 gives 46.875 kHz
	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;

	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

	int letoff = 0;
	for(;;)
	{
		uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

		// We haven't let off the button yet
		if (!letoff)
		{
			// We just let it off!
			if (!BUTTON_PRESS())
			{
				letoff = 1;

				// reset our timer for 500ms
				start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
				ticks = (48000 * (500)) >> 10;
			}

			// Still haven't let it off
			else
				// Have we held down a full second?
				if (now == (uint16_t)(start + ticks))
					return BUTTON_HOLD;
		}

		// We already let off, did we click again?
		else
			// Sweet, double click!
			if (BUTTON_PRESS())
				return BUTTON_DOUBLE_CLICK;

			// Have we ran out of time to double click?
			else
				if (now == (uint16_t)(start + ticks))
					// At least we did a single click
					return BUTTON_SINGLE_CLICK;

		WDT_HIT();
	}

	// We should never get here
	return BUTTON_ERROR;
}

// Determine if a button is held down
int BUTTON_HELD(int ms)
{
	// If button is held for one second
	int ticks = (48000 * (ms ? ms : 1000)) >> 10;

	// If we're not even pressed, forget about it!
	if (!BUTTON_PRESS())
		return BUTTON_NO_CLICK;

	// Borrow a PWM unit for my real-time clock
	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	// 48 MHz / 1024 gives 46.875 kHz
	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;

	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

	for(;;)
	{
		uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

		// As soon as our button let go, we didn't hold long enough
		if (!BUTTON_PRESS())
			return BUTTON_SINGLE_CLICK;

		// Have we waited the full second?
		else
			if (now == (uint16_t)(start + ticks))
				return BUTTON_HOLD;

		WDT_HIT();
	}

	// We should never get here
	return BUTTON_ERROR;
}

// attempt at high resolution microsecond timer
// beware: timer counts in 21.3uS increments (1024/48Mhz)
void SpinDelayUs(int us)
{
	int ticks = (48*us) >> 10;

	// Borrow a PWM unit for my real-time clock
	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	// 48 MHz / 1024 gives 46.875 kHz
	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;

	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

	for(;;) {
		uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
		if (now == (uint16_t)(start + ticks))
			return;

		WDT_HIT();
	}
}

void SpinDelay(int ms)
{
  // convert to uS and call microsecond delay function
	SpinDelayUs(ms*1000);
}

/* Similar to FpgaGatherVersion this formats stored version information
 * into a string representation. It takes a pointer to the struct version_information,
 * verifies the magic properties, then stores a formatted string, prefixed by
 * prefix in dst.
 */
void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information)
{
	struct version_information *v = (struct version_information*)version_information;
	dst[0] = 0;
	strncat(dst, prefix, len-1);
	if(v->magic != VERSION_INFORMATION_MAGIC) {
		strncat(dst, "Missing/Invalid version information", len - strlen(dst) - 1);
		return;
	}
	if(v->versionversion != 1) {
		strncat(dst, "Version information not understood", len - strlen(dst) - 1);
		return;
	}
	if(!v->present) {
		strncat(dst, "Version information not available", len - strlen(dst) - 1);
		return;
	}

	strncat(dst, v->gitversion, len - strlen(dst) - 1);
	if(v->clean == 0) {
		strncat(dst, "-unclean", len - strlen(dst) - 1);
	} else if(v->clean == 2) {
		strncat(dst, "-suspect", len - strlen(dst) - 1);
	}

	strncat(dst, " ", len - strlen(dst) - 1);
	strncat(dst, v->buildtime, len - strlen(dst) - 1);
}

//  -------------------------------------------------------------------------
//  timer lib
//  -------------------------------------------------------------------------
//  test procedure:
//
//	ti = GetTickCount();
//	SpinDelay(1000);
//	ti = GetTickCount() - ti;
//	Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());

void StartTickCount()
{
//  must be 0x40, but on my cpu - included divider is optimal
//  0x20 - 1 ms / bit 
//  0x40 - 2 ms / bit

	AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST + 0x001D; // was 0x003B
}

/*
* Get the current count.
*/
uint32_t RAMFUNC GetTickCount(){
	return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
}

//  -------------------------------------------------------------------------
//  microseconds timer 
//  -------------------------------------------------------------------------
void StartCountUS()
{
	AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
//	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;

	// fast clock
	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
														AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
														AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
	AT91C_BASE_TC0->TC_RA = 1;
	AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
	
	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable  
	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
	
	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
	AT91C_BASE_TCB->TCB_BCR = 1;
	}

uint32_t RAMFUNC GetCountUS(){
	return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
}

static uint32_t GlobalUsCounter = 0;

uint32_t RAMFUNC GetDeltaCountUS(){
	uint32_t g_cnt = GetCountUS();
	uint32_t g_res = g_cnt - GlobalUsCounter;
	GlobalUsCounter = g_cnt;
	return g_res;
}


//  -------------------------------------------------------------------------
//  Timer for iso14443 commands. Uses ssp_clk from FPGA 
//  -------------------------------------------------------------------------
void StartCountSspClk()
{
	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 		// XC0 Clock = TIOA1
							| AT91C_TCB_TC1XC1S_NONE 		// XC1 Clock = none
							| AT91C_TCB_TC2XC2S_TIOA0;		// XC2 Clock = TIOA0

	// configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; 				// disable TC1
	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
							| AT91C_TC_CPCSTOP				// Stop clock on RC compare
							| AT91C_TC_EEVTEDG_RISING		// Trigger on rising edge of Event
							| AT91C_TC_EEVT_TIOB			// Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
							| AT91C_TC_ENETRG				// Enable external trigger event
							| AT91C_TC_WAVESEL_UP	 		// Upmode without automatic trigger on RC compare
							| AT91C_TC_WAVE 				// Waveform Mode
							| AT91C_TC_AEEVT_SET 			// Set TIOA1 on external event
							| AT91C_TC_ACPC_CLEAR; 			// Clear TIOA1 on RC Compare
	AT91C_BASE_TC1->TC_RC = 0x04; 							// RC Compare value = 0x04

	// use TC0 to count TIOA1 pulses
	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;				// disable TC0
	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0	 			// TC0 clock = XC0 clock = TIOA1
							| AT91C_TC_WAVE 				// Waveform Mode
							| AT91C_TC_WAVESEL_UP	 		// just count
							| AT91C_TC_ACPA_CLEAR 			// Clear TIOA0 on RA Compare
							| AT91C_TC_ACPC_SET; 			// Set TIOA0 on RC Compare
	AT91C_BASE_TC0->TC_RA = 1;								// RA Compare value = 1; pulse width to TC2
	AT91C_BASE_TC0->TC_RC = 0; 								// RC Compare value = 0; increment TC2 on overflow

	// use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; 				// disable TC2  
	AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2	 			// TC2 clock = XC2 clock = TIOA0
							| AT91C_TC_WAVE 				// Waveform Mode
							| AT91C_TC_WAVESEL_UP;	 		// just count
	
	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;				// enable TC0
	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;				// enable TC1
	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;				// enable TC2

	//
	// synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present 
	//
	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); 	// wait for ssp_frame to go high (start of frame)
	while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); 		// wait for ssp_frame to be low
	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); 	// wait for ssp_clk to go high
	// note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
	// it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
	AT91C_BASE_TCB->TCB_BCR = 1;							// assert Sync (set all timers to 0 on next active clock edge)
	// at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
	// at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
	// whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
	// (just started with the transfer of the 4th Bit).
	// The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
	// we can use the counter.
	while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
}


uint32_t RAMFUNC GetCountSspClk(){
	uint32_t tmp_count;
	tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
	if ((tmp_count & 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2
		return (AT91C_BASE_TC2->TC_CV << 16);
	} 
	else {
		return tmp_count;
	}
}
Commit	Line	Data
e30c654b	1	//-----------------------------------------------------------------------------
e30c654b	2	// Jonathan Westhues, Sept 2005
bd20f8f4	3	//
	4	// This code is licensed to you under the terms of the GNU GPL, version 2 or,
	5	// at your option, any later version. See the LICENSE.txt file for the text of
	6	// the license.
	7	//-----------------------------------------------------------------------------
	8	// Utility functions used in many places, not specific to any piece of code.
e30c654b	9	//-----------------------------------------------------------------------------
bd20f8f4	10
e30c654b	11	#include "proxmark3.h"
f7e3ed82	12	#include "util.h"
9ab7a6c7	13	#include "string.h"
9492e0b0	14	#include "apps.h"
e30c654b	15
787b5bd8	16
	17
	18	void print_result(char name, uint8_t buf, size_t len) {
	19	uint8_t *p = buf;
	20
	21	if ( len % 16 == 0 ) {
	22	for(; p-buf < len; p += 16)
	23	Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
	24	name,
	25	p-buf,
	26	len,
	27	p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]
	28	);
	29	}
	30	else {
	31	for(; p-buf < len; p += 8)
	32	Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
	33	}
	34	}
	35
195af472	36	size_t nbytes(size_t nbits) {
	37	return (nbits/8)+((nbits%8)>0);
	38	}
	39
81cd0474	40	uint32_t SwapBits(uint32_t value, int nrbits) {
	41	int i;
	42	uint32_t newvalue = 0;
	43	for(i = 0; i < nrbits; i++) {
	44	newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
	45	}
	46	return newvalue;
	47	}
	48
f7e3ed82	49	void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
e30c654b	50	{
e30c654b	51	while (len--) {
f7e3ed82	52	dest[len] = (uint8_t) n;
e30c654b	53	n >>= 8;
	54	}
	55	}
	56
f7e3ed82	57	uint64_t bytes_to_num(uint8_t* src, size_t len)
e30c654b	58	{
	59	uint64_t num = 0;
	60	while (len--)
	61	{
	62	num = (num << 8) \| (*src);
	63	src++;
	64	}
	65	return num;
	66	}
	67
787b5bd8	68	// RotateLeft - Ultralight, Desfire
	69	void rol(uint8_t *data, const size_t len){
	70	uint8_t first = data[0];
	71	for (size_t i = 0; i < len-1; i++) {
	72	data[i] = data[i+1];
	73	}
	74	data[len-1] = first;
	75	}
	76	void lsl (uint8_t *data, size_t len) {
	77	for (size_t n = 0; n < len - 1; n++) {
	78	data[n] = (data[n] << 1) \| (data[n+1] >> 7);
	79	}
	80	data[len - 1] <<= 1;
	81	}
	82
	83	int32_t le24toh (uint8_t data[3])
	84	{
	85	return (data[2] << 16) \| (data[1] << 8) \| data[0];
	86	}
	87
e30c654b	88	void LEDsoff()
	89	{
	90	LED_A_OFF();
	91	LED_B_OFF();
	92	LED_C_OFF();
	93	LED_D_OFF();
	94	}
	95
	96	// LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
	97	void LED(int led, int ms)
	98	{
	99	if (led & LED_RED)
	100	LED_C_ON();
	101	if (led & LED_ORANGE)
	102	LED_A_ON();
	103	if (led & LED_GREEN)
	104	LED_B_ON();
	105	if (led & LED_RED2)
	106	LED_D_ON();
	107
	108	if (!ms)
	109	return;
	110
	111	SpinDelay(ms);
	112
	113	if (led & LED_RED)
	114	LED_C_OFF();
	115	if (led & LED_ORANGE)
	116	LED_A_OFF();
	117	if (led & LED_GREEN)
	118	LED_B_OFF();
	119	if (led & LED_RED2)
	120	LED_D_OFF();
	121	}
	122
	123
	124	// Determine if a button is double clicked, single clicked,
	125	// not clicked, or held down (for ms \|\| 1sec)
	126	// In general, don't use this function unless you expect a
	127	// double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
	128	int BUTTON_CLICKED(int ms)
	129	{
	130	// Up to 500ms in between clicks to mean a double click
	131	int ticks = (48000 * (ms ? ms : 1000)) >> 10;
	132
	133	// If we're not even pressed, forget about it!
	134	if (!BUTTON_PRESS())
	135	return BUTTON_NO_CLICK;
	136
	137	// Borrow a PWM unit for my real-time clock
	138	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	139	// 48 MHz / 1024 gives 46.875 kHz
	140	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	141	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	142	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
	143
f7e3ed82	144	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	145
	146	int letoff = 0;
	147	for(;;)
	148	{
f7e3ed82	149	uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	150
	151	// We haven't let off the button yet
	152	if (!letoff)
	153	{
	154	// We just let it off!
	155	if (!BUTTON_PRESS())
	156	{
	157	letoff = 1;
	158
	159	// reset our timer for 500ms
	160	start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
	161	ticks = (48000 * (500)) >> 10;
	162	}
	163
	164	// Still haven't let it off
	165	else
	166	// Have we held down a full second?
f7e3ed82	167	if (now == (uint16_t)(start + ticks))
e30c654b	168	return BUTTON_HOLD;
	169	}
	170
	171	// We already let off, did we click again?
	172	else
	173	// Sweet, double click!
	174	if (BUTTON_PRESS())
	175	return BUTTON_DOUBLE_CLICK;
	176
	177	// Have we ran out of time to double click?
	178	else
f7e3ed82	179	if (now == (uint16_t)(start + ticks))
e30c654b	180	// At least we did a single click
	181	return BUTTON_SINGLE_CLICK;
	182
	183	WDT_HIT();
	184	}
	185
	186	// We should never get here
	187	return BUTTON_ERROR;
	188	}
	189
	190	// Determine if a button is held down
	191	int BUTTON_HELD(int ms)
	192	{
	193	// If button is held for one second
	194	int ticks = (48000 * (ms ? ms : 1000)) >> 10;
	195
	196	// If we're not even pressed, forget about it!
	197	if (!BUTTON_PRESS())
	198	return BUTTON_NO_CLICK;
	199
	200	// Borrow a PWM unit for my real-time clock
	201	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	202	// 48 MHz / 1024 gives 46.875 kHz
	203	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	204	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	205	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
	206
f7e3ed82	207	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	208
	209	for(;;)
	210	{
f7e3ed82	211	uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	212
	213	// As soon as our button let go, we didn't hold long enough
	214	if (!BUTTON_PRESS())
	215	return BUTTON_SINGLE_CLICK;
	216
	217	// Have we waited the full second?
	218	else
f7e3ed82	219	if (now == (uint16_t)(start + ticks))
e30c654b	220	return BUTTON_HOLD;
	221
	222	WDT_HIT();
	223	}
	224
	225	// We should never get here
	226	return BUTTON_ERROR;
	227	}
	228
	229	// attempt at high resolution microsecond timer
	230	// beware: timer counts in 21.3uS increments (1024/48Mhz)
	231	void SpinDelayUs(int us)
	232	{
	233	int ticks = (48*us) >> 10;
	234
	235	// Borrow a PWM unit for my real-time clock
	236	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	237	// 48 MHz / 1024 gives 46.875 kHz
	238	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	239	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	240	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
	241
f7e3ed82	242	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	243
e30c654b	244	for(;;) {
f7e3ed82	245	uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
f7e3ed82	246	if (now == (uint16_t)(start + ticks))
e30c654b	247	return;
	248
	249	WDT_HIT();
	250	}
	251	}
	252
	253	void SpinDelay(int ms)
	254	{
	255	// convert to uS and call microsecond delay function
	256	SpinDelayUs(ms*1000);
	257	}
	258
	259	/* Similar to FpgaGatherVersion this formats stored version information
	260	* into a string representation. It takes a pointer to the struct version_information,
	261	* verifies the magic properties, then stores a formatted string, prefixed by
	262	* prefix in dst.
	263	*/
	264	void FormatVersionInformation(char dst, int len, const char prefix, void *version_information)
	265	{
	266	struct version_information v = (struct version_information)version_information;
	267	dst[0] = 0;
2ed270a8	268	strncat(dst, prefix, len-1);
e30c654b	269	if(v->magic != VERSION_INFORMATION_MAGIC) {
cba867f2	270	strncat(dst, "Missing/Invalid version information", len - strlen(dst) - 1);
e30c654b	271	return;
	272	}
	273	if(v->versionversion != 1) {
cba867f2	274	strncat(dst, "Version information not understood", len - strlen(dst) - 1);
e30c654b	275	return;
	276	}
	277	if(!v->present) {
cba867f2	278	strncat(dst, "Version information not available", len - strlen(dst) - 1);
e30c654b	279	return;
	280	}
	281
cba867f2	282	strncat(dst, v->gitversion, len - strlen(dst) - 1);
e30c654b	283	if(v->clean == 0) {
cba867f2	284	strncat(dst, "-unclean", len - strlen(dst) - 1);
e30c654b	285	} else if(v->clean == 2) {
cba867f2	286	strncat(dst, "-suspect", len - strlen(dst) - 1);
e30c654b	287	}
e30c654b	288
cba867f2 MHS	289	strncat(dst, " ", len - strlen(dst) - 1);
cba867f2 MHS	290	strncat(dst, v->buildtime, len - strlen(dst) - 1);
e30c654b	291	}
9ca155ba M	292
	293	// -------------------------------------------------------------------------
	294	// timer lib
	295	// -------------------------------------------------------------------------
	296	// test procedure:
	297	//
	298	// ti = GetTickCount();
	299	// SpinDelay(1000);
	300	// ti = GetTickCount() - ti;
	301	// Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
	302
	303	void StartTickCount()
	304	{
	305	// must be 0x40, but on my cpu - included divider is optimal
	306	// 0x20 - 1 ms / bit
	307	// 0x40 - 2 ms / bit
	308
0a39986e	309	AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST + 0x001D; // was 0x003B
9ca155ba M	310	}
	311
	312	/*
	313	* Get the current count.
	314	*/
	315	uint32_t RAMFUNC GetTickCount(){
8f51ddb0	316	return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
9ca155ba M	317	}
9ca155ba M	318
8f51ddb0 M	319	// -------------------------------------------------------------------------
	320	// microseconds timer
	321	// -------------------------------------------------------------------------
	322	void StartCountUS()
	323	{
	324	AT91C_BASE_PMC->PMC_PCER \|= (0x1 << 12) \| (0x1 << 13) \| (0x1 << 14);
	325	// AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
	326	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE \| AT91C_TCB_TC1XC1S_TIOA0 \| AT91C_TCB_TC2XC2S_NONE;
	327
	328	// fast clock
	329	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
	330	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK \| // MCK(48MHz)/32 -- tick=1.5mks
	331	AT91C_TC_WAVE \| AT91C_TC_WAVESEL_UP_AUTO \| AT91C_TC_ACPA_CLEAR \|
	332	AT91C_TC_ACPC_SET \| AT91C_TC_ASWTRG_SET;
	333	AT91C_BASE_TC0->TC_RA = 1;
	334	AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
	335
	336	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
	337	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
1c611bbd	338
8f51ddb0 M	339	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
	340	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
	341	AT91C_BASE_TCB->TCB_BCR = 1;
1c611bbd	342	}
8f51ddb0 M	343
	344	uint32_t RAMFUNC GetCountUS(){
	345	return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
	346	}
	347
	348	static uint32_t GlobalUsCounter = 0;
	349
	350	uint32_t RAMFUNC GetDeltaCountUS(){
	351	uint32_t g_cnt = GetCountUS();
	352	uint32_t g_res = g_cnt - GlobalUsCounter;
	353	GlobalUsCounter = g_cnt;
	354	return g_res;
	355	}
	356
	357
1c611bbd	358	// -------------------------------------------------------------------------
7bc95e2e	359	// Timer for iso14443 commands. Uses ssp_clk from FPGA
1c611bbd	360	// -------------------------------------------------------------------------
7bc95e2e	361	void StartCountSspClk()
1c611bbd	362	{
	363	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) \| (1 << AT91C_ID_TC1) \| (1 << AT91C_ID_TC2); // Enable Clock to all timers
	364	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1
	365	\| AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none
	366	\| AT91C_TCB_TC2XC2S_TIOA0; // XC2 Clock = TIOA0
	367
	368	// configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
	369	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // disable TC1
	370	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
	371	\| AT91C_TC_CPCSTOP // Stop clock on RC compare
	372	\| AT91C_TC_EEVTEDG_RISING // Trigger on rising edge of Event
7bc95e2e	373	\| AT91C_TC_EEVT_TIOB // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
1c611bbd	374	\| AT91C_TC_ENETRG // Enable external trigger event
	375	\| AT91C_TC_WAVESEL_UP // Upmode without automatic trigger on RC compare
	376	\| AT91C_TC_WAVE // Waveform Mode
	377	\| AT91C_TC_AEEVT_SET // Set TIOA1 on external event
	378	\| AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare
	379	AT91C_BASE_TC1->TC_RC = 0x04; // RC Compare value = 0x04
	380
	381	// use TC0 to count TIOA1 pulses
7bc95e2e	382	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0
1c611bbd	383	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0 // TC0 clock = XC0 clock = TIOA1
	384	\| AT91C_TC_WAVE // Waveform Mode
	385	\| AT91C_TC_WAVESEL_UP // just count
	386	\| AT91C_TC_ACPA_CLEAR // Clear TIOA0 on RA Compare
	387	\| AT91C_TC_ACPC_SET; // Set TIOA0 on RC Compare
	388	AT91C_BASE_TC0->TC_RA = 1; // RA Compare value = 1; pulse width to TC2
	389	AT91C_BASE_TC0->TC_RC = 0; // RC Compare value = 0; increment TC2 on overflow
	390
	391	// use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
	392	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; // disable TC2
	393	AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2 // TC2 clock = XC2 clock = TIOA0
	394	\| AT91C_TC_WAVE // Waveform Mode
	395	\| AT91C_TC_WAVESEL_UP; // just count
	396
1c611bbd	397	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; // enable TC0
	398	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; // enable TC1
	399	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN; // enable TC2
9492e0b0	400
7bc95e2e	401	//
	402	// synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present
	403	//
	404	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); // wait for ssp_frame to go high (start of frame)
9492e0b0	405	while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); // wait for ssp_frame to be low
7bc95e2e	406	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high
	407	// note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
	408	// it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
1c611bbd	409	AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge)
7bc95e2e	410	// at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
	411	// at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
	412	// whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
	413	// (just started with the transfer of the 4th Bit).
	414	// The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
	415	// we can use the counter.
	416	while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
1c611bbd	417	}
	418
	419
7bc95e2e	420	uint32_t RAMFUNC GetCountSspClk(){
1c611bbd	421	uint32_t tmp_count;
1c611bbd	422	tmp_count = (AT91C_BASE_TC2->TC_CV << 16) \| AT91C_BASE_TC0->TC_CV;
7bc95e2e	423	if ((tmp_count & 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2
1c611bbd	424	return (AT91C_BASE_TC2->TC_CV << 16);
	425	}
	426	else {
	427	return tmp_count;
	428	}
	429	}
7bc95e2e	430
7bc95e2e	431