]> cvs.zerfleddert.de Git - proxmark3-svn/blame - armsrc/lfops.c
Fixed bug in HID clone short format. Added EM4xxx block read/write commands
[proxmark3-svn] / armsrc / lfops.c
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15c4dc5a 1//-----------------------------------------------------------------------------
bd20f8f4 2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
15c4dc5a 6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10
e30c654b 11#include "proxmark3.h"
15c4dc5a 12#include "apps.h"
f7e3ed82 13#include "util.h"
15c4dc5a 14#include "hitag2.h"
15#include "crc16.h"
9ab7a6c7 16#include "string.h"
15c4dc5a 17
f7e3ed82 18void AcquireRawAdcSamples125k(int at134khz)
15c4dc5a 19{
20 if (at134khz)
21 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
22 else
23 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
24
25 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
26
27 // Connect the A/D to the peak-detected low-frequency path.
28 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
29
30 // Give it a bit of time for the resonant antenna to settle.
31 SpinDelay(50);
32
33 // Now set up the SSC to get the ADC samples that are now streaming at us.
34 FpgaSetupSsc();
35
36 // Now call the acquisition routine
37 DoAcquisition125k();
38}
39
40// split into two routines so we can avoid timing issues after sending commands //
41void DoAcquisition125k(void)
42{
f7e3ed82 43 uint8_t *dest = (uint8_t *)BigBuf;
15c4dc5a 44 int n = sizeof(BigBuf);
45 int i;
e30c654b 46
15c4dc5a 47 memset(dest, 0, n);
48 i = 0;
49 for(;;) {
50 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
51 AT91C_BASE_SSC->SSC_THR = 0x43;
52 LED_D_ON();
53 }
54 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
f7e3ed82 55 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 56 i++;
57 LED_D_OFF();
58 if (i >= n) break;
59 }
60 }
61 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
62 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
63}
64
f7e3ed82 65void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
15c4dc5a 66{
f7e3ed82 67 int at134khz;
15c4dc5a 68
69 /* Make sure the tag is reset */
70 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
71 SpinDelay(2500);
e30c654b 72
15c4dc5a 73 // see if 'h' was specified
74 if (command[strlen((char *) command) - 1] == 'h')
75 at134khz = TRUE;
76 else
77 at134khz = FALSE;
78
79 if (at134khz)
80 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
81 else
82 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
83
84 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
85
86 // Give it a bit of time for the resonant antenna to settle.
87 SpinDelay(50);
88 // And a little more time for the tag to fully power up
89 SpinDelay(2000);
90
91 // Now set up the SSC to get the ADC samples that are now streaming at us.
92 FpgaSetupSsc();
93
94 // now modulate the reader field
95 while(*command != '\0' && *command != ' ') {
96 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
97 LED_D_OFF();
98 SpinDelayUs(delay_off);
99 if (at134khz)
100 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
101 else
102 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
103
104 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
105 LED_D_ON();
106 if(*(command++) == '0')
107 SpinDelayUs(period_0);
108 else
109 SpinDelayUs(period_1);
110 }
111 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
112 LED_D_OFF();
113 SpinDelayUs(delay_off);
114 if (at134khz)
115 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
116 else
117 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
118
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
120
121 // now do the read
122 DoAcquisition125k();
123}
124
125/* blank r/w tag data stream
126...0000000000000000 01111111
1271010101010101010101010101010101010101010101010101010101010101010
1280011010010100001
12901111111
130101010101010101[0]000...
131
132[5555fe852c5555555555555555fe0000]
133*/
134void ReadTItag(void)
135{
136 // some hardcoded initial params
137 // when we read a TI tag we sample the zerocross line at 2Mhz
138 // TI tags modulate a 1 as 16 cycles of 123.2Khz
139 // TI tags modulate a 0 as 16 cycles of 134.2Khz
140 #define FSAMPLE 2000000
141 #define FREQLO 123200
142 #define FREQHI 134200
143
144 signed char *dest = (signed char *)BigBuf;
145 int n = sizeof(BigBuf);
146// int *dest = GraphBuffer;
147// int n = GraphTraceLen;
148
149 // 128 bit shift register [shift3:shift2:shift1:shift0]
f7e3ed82 150 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
15c4dc5a 151
152 int i, cycles=0, samples=0;
153 // how many sample points fit in 16 cycles of each frequency
f7e3ed82 154 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
15c4dc5a 155 // when to tell if we're close enough to one freq or another
f7e3ed82 156 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
15c4dc5a 157
158 // TI tags charge at 134.2Khz
159 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
160
161 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
162 // connects to SSP_DIN and the SSP_DOUT logic level controls
163 // whether we're modulating the antenna (high)
164 // or listening to the antenna (low)
165 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
166
167 // get TI tag data into the buffer
168 AcquireTiType();
169
170 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
171
172 for (i=0; i<n-1; i++) {
173 // count cycles by looking for lo to hi zero crossings
174 if ( (dest[i]<0) && (dest[i+1]>0) ) {
175 cycles++;
176 // after 16 cycles, measure the frequency
177 if (cycles>15) {
178 cycles=0;
179 samples=i-samples; // number of samples in these 16 cycles
180
181 // TI bits are coming to us lsb first so shift them
182 // right through our 128 bit right shift register
183 shift0 = (shift0>>1) | (shift1 << 31);
184 shift1 = (shift1>>1) | (shift2 << 31);
185 shift2 = (shift2>>1) | (shift3 << 31);
186 shift3 >>= 1;
187
188 // check if the cycles fall close to the number
189 // expected for either the low or high frequency
190 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
191 // low frequency represents a 1
192 shift3 |= (1<<31);
193 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
194 // high frequency represents a 0
195 } else {
196 // probably detected a gay waveform or noise
197 // use this as gaydar or discard shift register and start again
198 shift3 = shift2 = shift1 = shift0 = 0;
199 }
200 samples = i;
201
202 // for each bit we receive, test if we've detected a valid tag
203
204 // if we see 17 zeroes followed by 6 ones, we might have a tag
205 // remember the bits are backwards
206 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
207 // if start and end bytes match, we have a tag so break out of the loop
208 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
209 cycles = 0xF0B; //use this as a flag (ugly but whatever)
210 break;
211 }
212 }
213 }
214 }
215 }
216
217 // if flag is set we have a tag
218 if (cycles!=0xF0B) {
219 DbpString("Info: No valid tag detected.");
220 } else {
221 // put 64 bit data into shift1 and shift0
222 shift0 = (shift0>>24) | (shift1 << 8);
223 shift1 = (shift1>>24) | (shift2 << 8);
224
225 // align 16 bit crc into lower half of shift2
226 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
227
228 // if r/w tag, check ident match
229 if ( shift3&(1<<15) ) {
230 DbpString("Info: TI tag is rewriteable");
231 // only 15 bits compare, last bit of ident is not valid
232 if ( ((shift3>>16)^shift0)&0x7fff ) {
233 DbpString("Error: Ident mismatch!");
234 } else {
235 DbpString("Info: TI tag ident is valid");
236 }
237 } else {
238 DbpString("Info: TI tag is readonly");
239 }
240
241 // WARNING the order of the bytes in which we calc crc below needs checking
242 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
243 // bytes in reverse or something
244 // calculate CRC
f7e3ed82 245 uint32_t crc=0;
15c4dc5a 246
247 crc = update_crc16(crc, (shift0)&0xff);
248 crc = update_crc16(crc, (shift0>>8)&0xff);
249 crc = update_crc16(crc, (shift0>>16)&0xff);
250 crc = update_crc16(crc, (shift0>>24)&0xff);
251 crc = update_crc16(crc, (shift1)&0xff);
252 crc = update_crc16(crc, (shift1>>8)&0xff);
253 crc = update_crc16(crc, (shift1>>16)&0xff);
254 crc = update_crc16(crc, (shift1>>24)&0xff);
255
256 Dbprintf("Info: Tag data: %x%08x, crc=%x",
257 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
258 if (crc != (shift2&0xffff)) {
259 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
260 } else {
261 DbpString("Info: CRC is good");
262 }
263 }
264}
265
f7e3ed82 266void WriteTIbyte(uint8_t b)
15c4dc5a 267{
268 int i = 0;
269
270 // modulate 8 bits out to the antenna
271 for (i=0; i<8; i++)
272 {
273 if (b&(1<<i)) {
274 // stop modulating antenna
275 LOW(GPIO_SSC_DOUT);
276 SpinDelayUs(1000);
277 // modulate antenna
278 HIGH(GPIO_SSC_DOUT);
279 SpinDelayUs(1000);
280 } else {
281 // stop modulating antenna
282 LOW(GPIO_SSC_DOUT);
283 SpinDelayUs(300);
284 // modulate antenna
285 HIGH(GPIO_SSC_DOUT);
286 SpinDelayUs(1700);
287 }
288 }
289}
290
291void AcquireTiType(void)
292{
293 int i, j, n;
294 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
f7e3ed82 295 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
15c4dc5a 296 #define TIBUFLEN 1250
297
298 // clear buffer
299 memset(BigBuf,0,sizeof(BigBuf));
300
301 // Set up the synchronous serial port
302 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
303 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
304
305 // steal this pin from the SSP and use it to control the modulation
306 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
307 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
308
309 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
310 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
311
312 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
313 // 48/2 = 24 MHz clock must be divided by 12
314 AT91C_BASE_SSC->SSC_CMR = 12;
315
316 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
317 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
318 AT91C_BASE_SSC->SSC_TCMR = 0;
319 AT91C_BASE_SSC->SSC_TFMR = 0;
320
321 LED_D_ON();
322
323 // modulate antenna
324 HIGH(GPIO_SSC_DOUT);
325
326 // Charge TI tag for 50ms.
327 SpinDelay(50);
328
329 // stop modulating antenna and listen
330 LOW(GPIO_SSC_DOUT);
331
332 LED_D_OFF();
333
334 i = 0;
335 for(;;) {
336 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
337 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
338 i++; if(i >= TIBUFLEN) break;
339 }
340 WDT_HIT();
341 }
342
343 // return stolen pin to SSP
344 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
345 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
346
347 char *dest = (char *)BigBuf;
348 n = TIBUFLEN*32;
349 // unpack buffer
350 for (i=TIBUFLEN-1; i>=0; i--) {
351 for (j=0; j<32; j++) {
352 if(BigBuf[i] & (1 << j)) {
353 dest[--n] = 1;
354 } else {
355 dest[--n] = -1;
356 }
357 }
358 }
359}
360
361// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
362// if crc provided, it will be written with the data verbatim (even if bogus)
363// if not provided a valid crc will be computed from the data and written.
f7e3ed82 364void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
15c4dc5a 365{
366 if(crc == 0) {
367 crc = update_crc16(crc, (idlo)&0xff);
368 crc = update_crc16(crc, (idlo>>8)&0xff);
369 crc = update_crc16(crc, (idlo>>16)&0xff);
370 crc = update_crc16(crc, (idlo>>24)&0xff);
371 crc = update_crc16(crc, (idhi)&0xff);
372 crc = update_crc16(crc, (idhi>>8)&0xff);
373 crc = update_crc16(crc, (idhi>>16)&0xff);
374 crc = update_crc16(crc, (idhi>>24)&0xff);
375 }
376 Dbprintf("Writing to tag: %x%08x, crc=%x",
377 (unsigned int) idhi, (unsigned int) idlo, crc);
378
379 // TI tags charge at 134.2Khz
380 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
381 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
382 // connects to SSP_DIN and the SSP_DOUT logic level controls
383 // whether we're modulating the antenna (high)
384 // or listening to the antenna (low)
385 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
386 LED_A_ON();
387
388 // steal this pin from the SSP and use it to control the modulation
389 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
390 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
391
392 // writing algorithm:
393 // a high bit consists of a field off for 1ms and field on for 1ms
394 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
395 // initiate a charge time of 50ms (field on) then immediately start writing bits
396 // start by writing 0xBB (keyword) and 0xEB (password)
397 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
398 // finally end with 0x0300 (write frame)
399 // all data is sent lsb firts
400 // finish with 15ms programming time
401
402 // modulate antenna
403 HIGH(GPIO_SSC_DOUT);
404 SpinDelay(50); // charge time
405
406 WriteTIbyte(0xbb); // keyword
407 WriteTIbyte(0xeb); // password
408 WriteTIbyte( (idlo )&0xff );
409 WriteTIbyte( (idlo>>8 )&0xff );
410 WriteTIbyte( (idlo>>16)&0xff );
411 WriteTIbyte( (idlo>>24)&0xff );
412 WriteTIbyte( (idhi )&0xff );
413 WriteTIbyte( (idhi>>8 )&0xff );
414 WriteTIbyte( (idhi>>16)&0xff );
415 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
416 WriteTIbyte( (crc )&0xff ); // crc lo
417 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
418 WriteTIbyte(0x00); // write frame lo
419 WriteTIbyte(0x03); // write frame hi
420 HIGH(GPIO_SSC_DOUT);
421 SpinDelay(50); // programming time
422
423 LED_A_OFF();
424
425 // get TI tag data into the buffer
426 AcquireTiType();
427
428 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
429 DbpString("Now use tiread to check");
430}
431
432void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
433{
434 int i;
f7e3ed82 435 uint8_t *tab = (uint8_t *)BigBuf;
d19929cb 436
437 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
438
15c4dc5a 439 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
d19929cb 440
15c4dc5a 441 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
442 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
d19929cb 443
15c4dc5a 444#define SHORT_COIL() LOW(GPIO_SSC_DOUT)
445#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
d19929cb 446
15c4dc5a 447 i = 0;
448 for(;;) {
449 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
450 if(BUTTON_PRESS()) {
451 DbpString("Stopped");
452 return;
453 }
454 WDT_HIT();
455 }
d19929cb 456
15c4dc5a 457 if (ledcontrol)
458 LED_D_ON();
d19929cb 459
15c4dc5a 460 if(tab[i])
461 OPEN_COIL();
462 else
463 SHORT_COIL();
d19929cb 464
15c4dc5a 465 if (ledcontrol)
466 LED_D_OFF();
d19929cb 467
15c4dc5a 468 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
469 if(BUTTON_PRESS()) {
470 DbpString("Stopped");
471 return;
472 }
473 WDT_HIT();
474 }
d19929cb 475
15c4dc5a 476 i++;
477 if(i == period) {
478 i = 0;
e30c654b 479 if (gap) {
15c4dc5a 480 SHORT_COIL();
481 SpinDelayUs(gap);
482 }
483 }
484 }
485}
486
15c4dc5a 487#define DEBUG_FRAME_CONTENTS 1
488void SimulateTagLowFrequencyBidir(int divisor, int t0)
489{
15c4dc5a 490}
491
492// compose fc/8 fc/10 waveform
493static void fc(int c, int *n) {
f7e3ed82 494 uint8_t *dest = (uint8_t *)BigBuf;
15c4dc5a 495 int idx;
496
497 // for when we want an fc8 pattern every 4 logical bits
498 if(c==0) {
499 dest[((*n)++)]=1;
500 dest[((*n)++)]=1;
501 dest[((*n)++)]=0;
502 dest[((*n)++)]=0;
503 dest[((*n)++)]=0;
504 dest[((*n)++)]=0;
505 dest[((*n)++)]=0;
506 dest[((*n)++)]=0;
507 }
508 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
509 if(c==8) {
510 for (idx=0; idx<6; idx++) {
511 dest[((*n)++)]=1;
512 dest[((*n)++)]=1;
513 dest[((*n)++)]=0;
514 dest[((*n)++)]=0;
515 dest[((*n)++)]=0;
516 dest[((*n)++)]=0;
517 dest[((*n)++)]=0;
518 dest[((*n)++)]=0;
519 }
520 }
521
522 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
523 if(c==10) {
524 for (idx=0; idx<5; idx++) {
525 dest[((*n)++)]=1;
526 dest[((*n)++)]=1;
527 dest[((*n)++)]=1;
528 dest[((*n)++)]=0;
529 dest[((*n)++)]=0;
530 dest[((*n)++)]=0;
531 dest[((*n)++)]=0;
532 dest[((*n)++)]=0;
533 dest[((*n)++)]=0;
534 dest[((*n)++)]=0;
535 }
536 }
537}
538
539// prepare a waveform pattern in the buffer based on the ID given then
540// simulate a HID tag until the button is pressed
541void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
542{
543 int n=0, i=0;
544 /*
545 HID tag bitstream format
546 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
547 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
548 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
549 A fc8 is inserted before every 4 bits
550 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
551 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
552 */
553
554 if (hi>0xFFF) {
555 DbpString("Tags can only have 44 bits.");
556 return;
557 }
558 fc(0,&n);
559 // special start of frame marker containing invalid bit sequences
560 fc(8, &n); fc(8, &n); // invalid
561 fc(8, &n); fc(10, &n); // logical 0
562 fc(10, &n); fc(10, &n); // invalid
563 fc(8, &n); fc(10, &n); // logical 0
564
565 WDT_HIT();
566 // manchester encode bits 43 to 32
567 for (i=11; i>=0; i--) {
568 if ((i%4)==3) fc(0,&n);
569 if ((hi>>i)&1) {
570 fc(10, &n); fc(8, &n); // low-high transition
571 } else {
572 fc(8, &n); fc(10, &n); // high-low transition
573 }
574 }
575
576 WDT_HIT();
577 // manchester encode bits 31 to 0
578 for (i=31; i>=0; i--) {
579 if ((i%4)==3) fc(0,&n);
580 if ((lo>>i)&1) {
581 fc(10, &n); fc(8, &n); // low-high transition
582 } else {
583 fc(8, &n); fc(10, &n); // high-low transition
584 }
585 }
586
587 if (ledcontrol)
588 LED_A_ON();
589 SimulateTagLowFrequency(n, 0, ledcontrol);
590
591 if (ledcontrol)
592 LED_A_OFF();
593}
594
595
596// loop to capture raw HID waveform then FSK demodulate the TAG ID from it
597void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
598{
f7e3ed82 599 uint8_t *dest = (uint8_t *)BigBuf;
15c4dc5a 600 int m=0, n=0, i=0, idx=0, found=0, lastval=0;
e98300f2 601 uint32_t hi2=0, hi=0, lo=0;
15c4dc5a 602
603 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
604 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
605
606 // Connect the A/D to the peak-detected low-frequency path.
607 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
608
609 // Give it a bit of time for the resonant antenna to settle.
610 SpinDelay(50);
611
612 // Now set up the SSC to get the ADC samples that are now streaming at us.
613 FpgaSetupSsc();
614
615 for(;;) {
616 WDT_HIT();
617 if (ledcontrol)
618 LED_A_ON();
619 if(BUTTON_PRESS()) {
620 DbpString("Stopped");
621 if (ledcontrol)
622 LED_A_OFF();
623 return;
624 }
625
626 i = 0;
627 m = sizeof(BigBuf);
628 memset(dest,128,m);
629 for(;;) {
630 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
631 AT91C_BASE_SSC->SSC_THR = 0x43;
632 if (ledcontrol)
633 LED_D_ON();
634 }
635 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
f7e3ed82 636 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 637 // we don't care about actual value, only if it's more or less than a
638 // threshold essentially we capture zero crossings for later analysis
639 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
640 i++;
641 if (ledcontrol)
642 LED_D_OFF();
643 if(i >= m) {
644 break;
645 }
646 }
647 }
648
649 // FSK demodulator
650
651 // sync to first lo-hi transition
652 for( idx=1; idx<m; idx++) {
653 if (dest[idx-1]<dest[idx])
654 lastval=idx;
655 break;
656 }
657 WDT_HIT();
658
659 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
660 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
661 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
662 for( i=0; idx<m; idx++) {
663 if (dest[idx-1]<dest[idx]) {
664 dest[i]=idx-lastval;
665 if (dest[i] <= 8) {
666 dest[i]=1;
667 } else {
668 dest[i]=0;
669 }
670
671 lastval=idx;
672 i++;
673 }
674 }
675 m=i;
676 WDT_HIT();
677
678 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
679 lastval=dest[0];
680 idx=0;
681 i=0;
682 n=0;
683 for( idx=0; idx<m; idx++) {
684 if (dest[idx]==lastval) {
685 n++;
686 } else {
687 // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,
688 // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets
689 // swallowed up by rounding
690 // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding
691 // special start of frame markers use invalid manchester states (no transitions) by using sequences
692 // like 111000
693 if (dest[idx-1]) {
694 n=(n+1)/6; // fc/8 in sets of 6
695 } else {
696 n=(n+1)/5; // fc/10 in sets of 5
697 }
698 switch (n) { // stuff appropriate bits in buffer
699 case 0:
700 case 1: // one bit
701 dest[i++]=dest[idx-1];
702 break;
703 case 2: // two bits
704 dest[i++]=dest[idx-1];
705 dest[i++]=dest[idx-1];
706 break;
707 case 3: // 3 bit start of frame markers
708 dest[i++]=dest[idx-1];
709 dest[i++]=dest[idx-1];
710 dest[i++]=dest[idx-1];
711 break;
712 // When a logic 0 is immediately followed by the start of the next transmisson
713 // (special pattern) a pattern of 4 bit duration lengths is created.
714 case 4:
715 dest[i++]=dest[idx-1];
716 dest[i++]=dest[idx-1];
717 dest[i++]=dest[idx-1];
718 dest[i++]=dest[idx-1];
719 break;
720 default: // this shouldn't happen, don't stuff any bits
721 break;
722 }
723 n=0;
724 lastval=dest[idx];
725 }
726 }
727 m=i;
728 WDT_HIT();
729
730 // final loop, go over previously decoded manchester data and decode into usable tag ID
731 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
732 for( idx=0; idx<m-6; idx++) {
733 // search for a start of frame marker
734 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
735 {
736 found=1;
737 idx+=6;
e98300f2 738 if (found && (hi2|hi|lo)) {
739 if (hi2 != 0){
740 Dbprintf("TAG ID: %x%08x%08x (%d)",
741 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
742 }
743 else {
744 Dbprintf("TAG ID: %x%08x (%d)",
745 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
746 }
15c4dc5a 747 /* if we're only looking for one tag */
748 if (findone)
749 {
750 *high = hi;
751 *low = lo;
752 return;
753 }
e98300f2 754 hi2=0;
15c4dc5a 755 hi=0;
756 lo=0;
757 found=0;
758 }
759 }
760 if (found) {
761 if (dest[idx] && (!dest[idx+1]) ) {
e98300f2 762 hi2=(hi2<<1)|(hi>>31);
15c4dc5a 763 hi=(hi<<1)|(lo>>31);
764 lo=(lo<<1)|0;
765 } else if ( (!dest[idx]) && dest[idx+1]) {
e98300f2 766 hi2=(hi2<<1)|(hi>>31);
15c4dc5a 767 hi=(hi<<1)|(lo>>31);
768 lo=(lo<<1)|1;
769 } else {
770 found=0;
e98300f2 771 hi2=0;
15c4dc5a 772 hi=0;
773 lo=0;
774 }
775 idx++;
776 }
777 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
778 {
779 found=1;
780 idx+=6;
781 if (found && (hi|lo)) {
e98300f2 782 if (hi2 != 0){
783 Dbprintf("TAG ID: %x%08x%08x (%d)",
784 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
785 }
786 else {
787 Dbprintf("TAG ID: %x%08x (%d)",
788 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
789 }
15c4dc5a 790 /* if we're only looking for one tag */
791 if (findone)
792 {
793 *high = hi;
794 *low = lo;
795 return;
796 }
e98300f2 797 hi2=0;
15c4dc5a 798 hi=0;
799 lo=0;
800 found=0;
801 }
802 }
803 }
804 WDT_HIT();
805 }
806}
ec09b62d 807
e98300f2 808
2d4eae76 809/*------------------------------
810 * T5555/T5557/T5567 routines
811 *------------------------------
812 */
813
814/* T55x7 configuration register definitions */
815#define T55x7_POR_DELAY 0x00000001
816#define T55x7_ST_TERMINATOR 0x00000008
817#define T55x7_PWD 0x00000010
818#define T55x7_MAXBLOCK_SHIFT 5
819#define T55x7_AOR 0x00000200
820#define T55x7_PSKCF_RF_2 0
821#define T55x7_PSKCF_RF_4 0x00000400
822#define T55x7_PSKCF_RF_8 0x00000800
823#define T55x7_MODULATION_DIRECT 0
824#define T55x7_MODULATION_PSK1 0x00001000
825#define T55x7_MODULATION_PSK2 0x00002000
826#define T55x7_MODULATION_PSK3 0x00003000
827#define T55x7_MODULATION_FSK1 0x00004000
828#define T55x7_MODULATION_FSK2 0x00005000
829#define T55x7_MODULATION_FSK1a 0x00006000
830#define T55x7_MODULATION_FSK2a 0x00007000
831#define T55x7_MODULATION_MANCHESTER 0x00008000
832#define T55x7_MODULATION_BIPHASE 0x00010000
833#define T55x7_BITRATE_RF_8 0
834#define T55x7_BITRATE_RF_16 0x00040000
835#define T55x7_BITRATE_RF_32 0x00080000
836#define T55x7_BITRATE_RF_40 0x000C0000
837#define T55x7_BITRATE_RF_50 0x00100000
838#define T55x7_BITRATE_RF_64 0x00140000
839#define T55x7_BITRATE_RF_100 0x00180000
840#define T55x7_BITRATE_RF_128 0x001C0000
841
842/* T5555 (Q5) configuration register definitions */
843#define T5555_ST_TERMINATOR 0x00000001
844#define T5555_MAXBLOCK_SHIFT 0x00000001
845#define T5555_MODULATION_MANCHESTER 0
846#define T5555_MODULATION_PSK1 0x00000010
847#define T5555_MODULATION_PSK2 0x00000020
848#define T5555_MODULATION_PSK3 0x00000030
849#define T5555_MODULATION_FSK1 0x00000040
850#define T5555_MODULATION_FSK2 0x00000050
851#define T5555_MODULATION_BIPHASE 0x00000060
852#define T5555_MODULATION_DIRECT 0x00000070
853#define T5555_INVERT_OUTPUT 0x00000080
854#define T5555_PSK_RF_2 0
855#define T5555_PSK_RF_4 0x00000100
856#define T5555_PSK_RF_8 0x00000200
857#define T5555_USE_PWD 0x00000400
858#define T5555_USE_AOR 0x00000800
859#define T5555_BITRATE_SHIFT 12
860#define T5555_FAST_WRITE 0x00004000
861#define T5555_PAGE_SELECT 0x00008000
862
863/*
864 * Relevant times in microsecond
865 * To compensate antenna falling times shorten the write times
866 * and enlarge the gap ones.
867 */
868#define START_GAP 250
869#define WRITE_GAP 160
870#define WRITE_0 144 // 192
871#define WRITE_1 400 // 432 for T55x7; 448 for E5550
872
873// Write one bit to card
874void T55xxWriteBit(int bit)
ec09b62d 875{
876 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
877 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
2d4eae76 878 if (bit == 0)
879 SpinDelayUs(WRITE_0);
880 else
881 SpinDelayUs(WRITE_1);
ec09b62d 882 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2d4eae76 883 SpinDelayUs(WRITE_GAP);
ec09b62d 884}
885
2d4eae76 886// Write one card block in page 0, no lock
e98300f2 887void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
ec09b62d 888{
2d4eae76 889 unsigned int i;
ec09b62d 890
891 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
892 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
893
894 // Give it a bit of time for the resonant antenna to settle.
895 // And for the tag to fully power up
896 SpinDelay(150);
897
2d4eae76 898 // Now start writting
ec09b62d 899 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2d4eae76 900 SpinDelayUs(START_GAP);
901
902 // Opcode
903 T55xxWriteBit(1);
904 T55xxWriteBit(0); //Page 0
e98300f2 905 if (PwdMode == 1){
906 // Pwd
907 for (i = 0x80000000; i != 0; i >>= 1)
908 T55xxWriteBit(Pwd & i);
909 }
2d4eae76 910 // Lock bit
911 T55xxWriteBit(0);
912
913 // Data
914 for (i = 0x80000000; i != 0; i >>= 1)
915 T55xxWriteBit(Data & i);
916
e98300f2 917 // Block
2d4eae76 918 for (i = 0x04; i != 0; i >>= 1)
919 T55xxWriteBit(Block & i);
920
921 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
922 // so wait a little more)
923 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
ec09b62d 924 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
925 SpinDelay(20);
2d4eae76 926 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
ec09b62d 927}
928
e98300f2 929
930// Read one card block in page 0
931void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
ec09b62d 932{
e98300f2 933 uint8_t *dest = (uint8_t *)BigBuf;
934 int m=0, i=0;
935
936 m = sizeof(BigBuf);
937 // Clear destination buffer before sending the command
938 memset(dest, 128, m);
939 // Connect the A/D to the peak-detected low-frequency path.
940 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
941 // Now set up the SSC to get the ADC samples that are now streaming at us.
942 FpgaSetupSsc();
ec09b62d 943
e98300f2 944 LED_D_ON();
945 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
946 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
2d4eae76 947
e98300f2 948 // Give it a bit of time for the resonant antenna to settle.
949 // And for the tag to fully power up
950 SpinDelay(150);
2d4eae76 951
e98300f2 952 // Now start writting
953 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
954 SpinDelayUs(START_GAP);
2d4eae76 955
e98300f2 956 // Opcode
957 T55xxWriteBit(1);
958 T55xxWriteBit(0); //Page 0
959 if (PwdMode == 1){
960 // Pwd
961 for (i = 0x80000000; i != 0; i >>= 1)
962 T55xxWriteBit(Pwd & i);
963 }
964 // Lock bit
965 T55xxWriteBit(0);
966 // Block
967 for (i = 0x04; i != 0; i >>= 1)
968 T55xxWriteBit(Block & i);
969
970 // Turn field on to read the response
971 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
972 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
973
974 // Now do the acquisition
975 i = 0;
976 for(;;) {
977 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
978 AT91C_BASE_SSC->SSC_THR = 0x43;
979 }
980 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
981 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
982 // we don't care about actual value, only if it's more or less than a
983 // threshold essentially we capture zero crossings for later analysis
984// if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
985 i++;
986 if (i >= m) break;
987 }
ec09b62d 988 }
2d4eae76 989
e98300f2 990 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
991 LED_D_OFF();
992 DbpString("DONE!");
993}
994
995// Read card traceability data (page 1)
996void T55xxReadTrace(void){
997 uint8_t *dest = (uint8_t *)BigBuf;
998 int m=0, i=0;
999
1000 m = sizeof(BigBuf);
1001 // Clear destination buffer before sending the command
1002 memset(dest, 128, m);
1003 // Connect the A/D to the peak-detected low-frequency path.
1004 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1005 // Now set up the SSC to get the ADC samples that are now streaming at us.
1006 FpgaSetupSsc();
1007
1008 LED_D_ON();
1009 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1010 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
1011
1012 // Give it a bit of time for the resonant antenna to settle.
1013 // And for the tag to fully power up
1014 SpinDelay(150);
1015
1016 // Now start writting
1017 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1018 SpinDelayUs(START_GAP);
1019
1020 // Opcode
1021 T55xxWriteBit(1);
1022 T55xxWriteBit(1); //Page 1
1023
1024 // Turn field on to read the response
1025 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1026 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
1027
1028 // Now do the acquisition
1029 i = 0;
1030 for(;;) {
1031 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1032 AT91C_BASE_SSC->SSC_THR = 0x43;
1033 }
1034 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1035 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1036 i++;
1037 if (i >= m) break;
1038 }
ec09b62d 1039 }
1040
e98300f2 1041 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1042 LED_D_OFF();
1043 DbpString("DONE!");
1044}
2d4eae76 1045
e98300f2 1046/*-------------- Cloning routines -----------*/
1047// Copy HID id to card and setup block 0 config
1048void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1049{
1050 int data1, data2, data3, data4, data5, data6; //up to six blocks for long format
1051 int last_block = 0;
1052
1053 if (longFMT){
1054 // Ensure no more than 84 bits supplied
1055 if (hi2>0xFFFFF) {
1056 DbpString("Tags can only have 84 bits.");
1057 return;
1058 }
1059 // Build the 6 data blocks for supplied 84bit ID
1060 last_block = 6;
1061 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1062 for (int i=0;i<4;i++) {
1063 if (hi2 & (1<<(19-i)))
1064 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1065 else
1066 data1 |= (1<<((3-i)*2)); // 0 -> 01
1067 }
1068
1069 data2 = 0;
1070 for (int i=0;i<16;i++) {
1071 if (hi2 & (1<<(15-i)))
1072 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1073 else
1074 data2 |= (1<<((15-i)*2)); // 0 -> 01
1075 }
1076
1077 data3 = 0;
1078 for (int i=0;i<16;i++) {
1079 if (hi & (1<<(31-i)))
1080 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1081 else
1082 data3 |= (1<<((15-i)*2)); // 0 -> 01
1083 }
1084
1085 data4 = 0;
1086 for (int i=0;i<16;i++) {
1087 if (hi & (1<<(15-i)))
1088 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1089 else
1090 data4 |= (1<<((15-i)*2)); // 0 -> 01
1091 }
1092
1093 data5 = 0;
1094 for (int i=0;i<16;i++) {
1095 if (lo & (1<<(31-i)))
1096 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1097 else
1098 data5 |= (1<<((15-i)*2)); // 0 -> 01
1099 }
1100
1101 data6 = 0;
1102 for (int i=0;i<16;i++) {
1103 if (lo & (1<<(15-i)))
1104 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1105 else
1106 data6 |= (1<<((15-i)*2)); // 0 -> 01
1107 }
1108 }
1109 else {
1110 // Ensure no more than 44 bits supplied
1111 if (hi>0xFFF) {
1112 DbpString("Tags can only have 44 bits.");
1113 return;
1114 }
1115
1116 // Build the 3 data blocks for supplied 44bit ID
1117 last_block = 3;
1118
1119 data1 = 0x1D000000; // load preamble
1120
1121 for (int i=0;i<12;i++) {
d16e0478 1122 if (hi & (1<<(11-i)))
1123 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
e98300f2 1124 else
d16e0478 1125 data1 |= (1<<((11-i)*2)); // 0 -> 01
e98300f2 1126 }
1127
1128 data2 = 0;
1129 for (int i=0;i<16;i++) {
1130 if (lo & (1<<(31-i)))
1131 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1132 else
1133 data2 |= (1<<((15-i)*2)); // 0 -> 01
1134 }
1135
1136 data3 = 0;
1137 for (int i=0;i<16;i++) {
1138 if (lo & (1<<(15-i)))
1139 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1140 else
1141 data3 |= (1<<((15-i)*2)); // 0 -> 01
1142 }
1143 }
1144
1145 LED_D_ON();
1146 // Program the data blocks for supplied ID
1147 // and the block 0 for HID format
1148 T55xxWriteBlock(data1,1,0,0);
1149 T55xxWriteBlock(data2,2,0,0);
1150 T55xxWriteBlock(data3,3,0,0);
1151
1152 if (longFMT) { // if long format there are 6 blocks
1153 T55xxWriteBlock(data4,4,0,0);
1154 T55xxWriteBlock(data5,5,0,0);
1155 T55xxWriteBlock(data6,6,0,0);
1156 }
1157
1158 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
2414f978 1159 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1160 T55x7_MODULATION_FSK2a |
e98300f2 1161 last_block << T55x7_MAXBLOCK_SHIFT,
1162 0,0,0);
1163
1164 LED_D_OFF();
1165
ec09b62d 1166 DbpString("DONE!");
2d4eae76 1167}
ec09b62d 1168
2d4eae76 1169// Define 9bit header for EM410x tags
1170#define EM410X_HEADER 0x1FF
1171#define EM410X_ID_LENGTH 40
ec09b62d 1172
2d4eae76 1173void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1174{
1175 int i, id_bit;
1176 uint64_t id = EM410X_HEADER;
1177 uint64_t rev_id = 0; // reversed ID
1178 int c_parity[4]; // column parity
1179 int r_parity = 0; // row parity
1180
1181 // Reverse ID bits given as parameter (for simpler operations)
1182 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1183 if (i < 32) {
1184 rev_id = (rev_id << 1) | (id_lo & 1);
1185 id_lo >>= 1;
1186 } else {
1187 rev_id = (rev_id << 1) | (id_hi & 1);
1188 id_hi >>= 1;
1189 }
1190 }
1191
1192 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1193 id_bit = rev_id & 1;
1194
1195 if (i % 4 == 0) {
1196 // Don't write row parity bit at start of parsing
1197 if (i)
1198 id = (id << 1) | r_parity;
1199 // Start counting parity for new row
1200 r_parity = id_bit;
1201 } else {
1202 // Count row parity
1203 r_parity ^= id_bit;
1204 }
1205
1206 // First elements in column?
1207 if (i < 4)
1208 // Fill out first elements
1209 c_parity[i] = id_bit;
1210 else
1211 // Count column parity
1212 c_parity[i % 4] ^= id_bit;
1213
1214 // Insert ID bit
1215 id = (id << 1) | id_bit;
1216 rev_id >>= 1;
1217 }
1218
1219 // Insert parity bit of last row
1220 id = (id << 1) | r_parity;
1221
1222 // Fill out column parity at the end of tag
1223 for (i = 0; i < 4; ++i)
1224 id = (id << 1) | c_parity[i];
1225
1226 // Add stop bit
1227 id <<= 1;
1228
1229 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1230 LED_D_ON();
1231
1232 // Write EM410x ID
e98300f2 1233 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1234 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
2d4eae76 1235
1236 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1237 if (card)
1238 // Writing configuration for T55x7 tag
1239 T55xxWriteBlock(T55x7_BITRATE_RF_64 |
1240 T55x7_MODULATION_MANCHESTER |
1241 2 << T55x7_MAXBLOCK_SHIFT,
e98300f2 1242 0, 0, 0);
2d4eae76 1243 else
1244 // Writing configuration for T5555(Q5) tag
1245 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1246 T5555_MODULATION_MANCHESTER |
1247 2 << T5555_MAXBLOCK_SHIFT,
e98300f2 1248 0, 0, 0);
2d4eae76 1249
1250 LED_D_OFF();
1251 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1252 (uint32_t)(id >> 32), (uint32_t)id);
1253}
2414f978 1254
1255// Clone Indala 64-bit tag by UID to T55x7
1256void CopyIndala64toT55x7(int hi, int lo)
1257{
1258
1259 //Program the 2 data blocks for supplied 64bit UID
1260 // and the block 0 for Indala64 format
e98300f2 1261 T55xxWriteBlock(hi,1,0,0);
1262 T55xxWriteBlock(lo,2,0,0);
2414f978 1263 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1264 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1265 T55x7_MODULATION_PSK1 |
1266 2 << T55x7_MAXBLOCK_SHIFT,
e98300f2 1267 0,0,0);
2414f978 1268 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1269// T5567WriteBlock(0x603E1042,0);
1270
1271 DbpString("DONE!");
1272
1273}
1274
1275void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1276{
1277
1278 //Program the 7 data blocks for supplied 224bit UID
1279 // and the block 0 for Indala224 format
e98300f2 1280 T55xxWriteBlock(uid1,1,0,0);
1281 T55xxWriteBlock(uid2,2,0,0);
1282 T55xxWriteBlock(uid3,3,0,0);
1283 T55xxWriteBlock(uid4,4,0,0);
1284 T55xxWriteBlock(uid5,5,0,0);
1285 T55xxWriteBlock(uid6,6,0,0);
1286 T55xxWriteBlock(uid7,7,0,0);
2414f978 1287 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1288 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1289 T55x7_MODULATION_PSK1 |
1290 7 << T55x7_MAXBLOCK_SHIFT,
e98300f2 1291 0,0,0);
2414f978 1292 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1293// T5567WriteBlock(0x603E10E2,0);
1294
1295 DbpString("DONE!");
1296
1297}
f5fca2ed 1298
1299#define abs(x) ( ((x)<0) ? -(x) : (x) )
1300#define max(x,y) ( x<y ? y:x)
1301
1302int DemodPCF7931(uint8_t **outBlocks) {
1303 uint8_t BitStream[256];
1304 uint8_t Blocks[8][16];
1305 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1306 int GraphTraceLen = sizeof(BigBuf);
1307 int i, j, lastval, bitidx, half_switch;
1308 int clock = 64;
1309 int tolerance = clock / 8;
1310 int pmc, block_done;
1311 int lc, warnings = 0;
1312 int num_blocks = 0;
1313 int lmin=128, lmax=128;
1314 uint8_t dir;
1315
1316 AcquireRawAdcSamples125k(0);
1317
1318 lmin = 64;
1319 lmax = 192;
1320
1321 i = 2;
1322
1323 /* Find first local max/min */
1324 if(GraphBuffer[1] > GraphBuffer[0]) {
1325 while(i < GraphTraceLen) {
1326 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1327 break;
1328 i++;
1329 }
1330 dir = 0;
1331 }
1332 else {
1333 while(i < GraphTraceLen) {
1334 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1335 break;
1336 i++;
1337 }
1338 dir = 1;
1339 }
1340
1341 lastval = i++;
1342 half_switch = 0;
1343 pmc = 0;
1344 block_done = 0;
1345
1346 for (bitidx = 0; i < GraphTraceLen; i++)
1347 {
1348 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1349 {
1350 lc = i - lastval;
1351 lastval = i;
1352
1353 // Switch depending on lc length:
1354 // Tolerance is 1/8 of clock rate (arbitrary)
1355 if (abs(lc-clock/4) < tolerance) {
1356 // 16T0
1357 if((i - pmc) == lc) { /* 16T0 was previous one */
1358 /* It's a PMC ! */
1359 i += (128+127+16+32+33+16)-1;
1360 lastval = i;
1361 pmc = 0;
1362 block_done = 1;
1363 }
1364 else {
1365 pmc = i;
1366 }
1367 } else if (abs(lc-clock/2) < tolerance) {
1368 // 32TO
1369 if((i - pmc) == lc) { /* 16T0 was previous one */
1370 /* It's a PMC ! */
1371 i += (128+127+16+32+33)-1;
1372 lastval = i;
1373 pmc = 0;
1374 block_done = 1;
1375 }
1376 else if(half_switch == 1) {
1377 BitStream[bitidx++] = 0;
1378 half_switch = 0;
1379 }
1380 else
1381 half_switch++;
1382 } else if (abs(lc-clock) < tolerance) {
1383 // 64TO
1384 BitStream[bitidx++] = 1;
1385 } else {
1386 // Error
1387 warnings++;
1388 if (warnings > 10)
1389 {
1390 Dbprintf("Error: too many detection errors, aborting.");
1391 return 0;
1392 }
1393 }
1394
1395 if(block_done == 1) {
1396 if(bitidx == 128) {
1397 for(j=0; j<16; j++) {
1398 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1399 64*BitStream[j*8+6]+
1400 32*BitStream[j*8+5]+
1401 16*BitStream[j*8+4]+
1402 8*BitStream[j*8+3]+
1403 4*BitStream[j*8+2]+
1404 2*BitStream[j*8+1]+
1405 BitStream[j*8];
1406 }
1407 num_blocks++;
1408 }
1409 bitidx = 0;
1410 block_done = 0;
1411 half_switch = 0;
1412 }
1413 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1414 else dir = 1;
1415 }
1416 if(bitidx==255)
1417 bitidx=0;
1418 warnings = 0;
1419 if(num_blocks == 4) break;
1420 }
1421 memcpy(outBlocks, Blocks, 16*num_blocks);
1422 return num_blocks;
1423}
1424
1425int IsBlock0PCF7931(uint8_t *Block) {
1426 // Assume RFU means 0 :)
1427 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1428 return 1;
1429 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1430 return 1;
1431 return 0;
1432}
1433
1434int IsBlock1PCF7931(uint8_t *Block) {
1435 // Assume RFU means 0 :)
1436 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1437 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1438 return 1;
1439
1440 return 0;
1441}
1442
1443#define ALLOC 16
1444
1445void ReadPCF7931() {
1446 uint8_t Blocks[8][17];
1447 uint8_t tmpBlocks[4][16];
1448 int i, j, ind, ind2, n;
1449 int num_blocks = 0;
1450 int max_blocks = 8;
1451 int ident = 0;
1452 int error = 0;
1453 int tries = 0;
1454
1455 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1456
1457 do {
1458 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1459 n = DemodPCF7931((uint8_t**)tmpBlocks);
1460 if(!n)
1461 error++;
1462 if(error==10 && num_blocks == 0) {
1463 Dbprintf("Error, no tag or bad tag");
1464 return;
1465 }
1466 else if (tries==20 || error==10) {
1467 Dbprintf("Error reading the tag");
1468 Dbprintf("Here is the partial content");
1469 goto end;
1470 }
1471
1472 for(i=0; i<n; i++)
1473 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1474 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1475 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1476 if(!ident) {
1477 for(i=0; i<n; i++) {
1478 if(IsBlock0PCF7931(tmpBlocks[i])) {
1479 // Found block 0 ?
1480 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1481 // Found block 1!
1482 // \o/
1483 ident = 1;
1484 memcpy(Blocks[0], tmpBlocks[i], 16);
1485 Blocks[0][ALLOC] = 1;
1486 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1487 Blocks[1][ALLOC] = 1;
1488 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1489 // Debug print
1490 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1491 num_blocks = 2;
1492 // Handle following blocks
1493 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1494 if(j==n) j=0;
1495 if(j==i) break;
1496 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1497 Blocks[ind2][ALLOC] = 1;
1498 }
1499 break;
1500 }
1501 }
1502 }
1503 }
1504 else {
1505 for(i=0; i<n; i++) { // Look for identical block in known blocks
1506 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1507 for(j=0; j<max_blocks; j++) {
1508 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1509 // Found an identical block
1510 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1511 if(ind2 < 0)
1512 ind2 = max_blocks;
1513 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1514 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1515 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1516 Blocks[ind2][ALLOC] = 1;
1517 num_blocks++;
1518 if(num_blocks == max_blocks) goto end;
1519 }
1520 }
1521 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1522 if(ind2 > max_blocks)
1523 ind2 = 0;
1524 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1525 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1526 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1527 Blocks[ind2][ALLOC] = 1;
1528 num_blocks++;
1529 if(num_blocks == max_blocks) goto end;
1530 }
1531 }
1532 }
1533 }
1534 }
1535 }
1536 }
1537 tries++;
1538 if (BUTTON_PRESS()) return;
1539 } while (num_blocks != max_blocks);
1540 end:
1541 Dbprintf("-----------------------------------------");
1542 Dbprintf("Memory content:");
1543 Dbprintf("-----------------------------------------");
1544 for(i=0; i<max_blocks; i++) {
1545 if(Blocks[i][ALLOC]==1)
1546 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1547 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1548 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1549 else
1550 Dbprintf("<missing block %d>", i);
1551 }
1552 Dbprintf("-----------------------------------------");
1553
1554 return ;
1555}
d16e0478 1556
1557
1558//-----------------------------------
1559// EM4469 / EM4305 routines
1560//-----------------------------------
1561#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1562#define FWD_CMD_WRITE 0xA
1563#define FWD_CMD_READ 0x9
1564#define FWD_CMD_DISABLE 0x5
1565
1566
1567uint8_t forwardLink_data[64]; //array of forwarded bits
1568uint8_t * forward_ptr; //ptr for forward message preparation
1569uint8_t fwd_bit_sz; //forwardlink bit counter
1570uint8_t * fwd_write_ptr; //forwardlink bit pointer
1571
1572//====================================================================
1573// prepares command bits
1574// see EM4469 spec
1575//====================================================================
1576//--------------------------------------------------------------------
1577uint8_t Prepare_Cmd( uint8_t cmd ) {
1578//--------------------------------------------------------------------
1579
1580 *forward_ptr++ = 0; //start bit
1581 *forward_ptr++ = 0; //second pause for 4050 code
1582
1583 *forward_ptr++ = cmd;
1584 cmd >>= 1;
1585 *forward_ptr++ = cmd;
1586 cmd >>= 1;
1587 *forward_ptr++ = cmd;
1588 cmd >>= 1;
1589 *forward_ptr++ = cmd;
1590
1591 return 6; //return number of emited bits
1592}
1593
1594//====================================================================
1595// prepares address bits
1596// see EM4469 spec
1597//====================================================================
1598
1599//--------------------------------------------------------------------
1600uint8_t Prepare_Addr( uint8_t addr ) {
1601//--------------------------------------------------------------------
1602
1603 register uint8_t line_parity;
1604
1605 uint8_t i;
1606 line_parity = 0;
1607 for(i=0;i<6;i++) {
1608 *forward_ptr++ = addr;
1609 line_parity ^= addr;
1610 addr >>= 1;
1611 }
1612
1613 *forward_ptr++ = (line_parity & 1);
1614
1615 return 7; //return number of emited bits
1616}
1617
1618//====================================================================
1619// prepares data bits intreleaved with parity bits
1620// see EM4469 spec
1621//====================================================================
1622
1623//--------------------------------------------------------------------
1624uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1625//--------------------------------------------------------------------
1626
1627 register uint8_t line_parity;
1628 register uint8_t column_parity;
1629 register uint8_t i, j;
1630 register uint16_t data;
1631
1632 data = data_low;
1633 column_parity = 0;
1634
1635 for(i=0; i<4; i++) {
1636 line_parity = 0;
1637 for(j=0; j<8; j++) {
1638 line_parity ^= data;
1639 column_parity ^= (data & 1) << j;
1640 *forward_ptr++ = data;
1641 data >>= 1;
1642 }
1643 *forward_ptr++ = line_parity;
1644 if(i == 1)
1645 data = data_hi;
1646 }
1647
1648 for(j=0; j<8; j++) {
1649 *forward_ptr++ = column_parity;
1650 column_parity >>= 1;
1651 }
1652 *forward_ptr = 0;
1653
1654 return 45; //return number of emited bits
1655}
1656
1657//====================================================================
1658// Forward Link send function
1659// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1660// fwd_bit_count set with number of bits to be sent
1661//====================================================================
1662void SendForward(uint8_t fwd_bit_count) {
1663
1664 fwd_write_ptr = forwardLink_data;
1665 fwd_bit_sz = fwd_bit_count;
1666
1667 LED_D_ON();
1668
1669 //Field on
1670 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1671 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
1672
1673 // Give it a bit of time for the resonant antenna to settle.
1674 // And for the tag to fully power up
1675 SpinDelay(150);
1676
1677 // force 1st mod pulse (start gap must be longer for 4305)
1678 fwd_bit_sz--; //prepare next bit modulation
1679 fwd_write_ptr++;
1680 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1681 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1682 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1683 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
1684 SpinDelayUs(16*8); //16 cycles on (8us each)
1685
1686 // now start writting
1687 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1688 if(((*fwd_write_ptr++) & 1) == 1)
1689 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1690 else {
1691 //These timings work for 4469/4269/4305 (with the 55*8 above)
1692 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1693 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1694 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1695 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
1696 SpinDelayUs(9*8); //16 cycles on (8us each)
1697 }
1698 }
1699}
1700
1701void Login (uint32_t Password) {
1702
1703 uint8_t fwd_bit_count;
1704
1705 forward_ptr = forwardLink_data;
1706 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1707 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1708
1709 SendForward(fwd_bit_count);
1710
1711 //Wait for command to complete
1712 SpinDelay(20);
1713
1714}
1715
1716void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1717
1718 uint8_t fwd_bit_count;
1719 uint8_t *dest = (uint8_t *)BigBuf;
1720 int m=0, i=0;
1721
1722 //If password mode do login
1723 if (PwdMode == 1) Login(Pwd);
1724
1725 forward_ptr = forwardLink_data;
1726 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1727 fwd_bit_count += Prepare_Addr( Address );
1728
1729 m = sizeof(BigBuf);
1730 // Clear destination buffer before sending the command
1731 memset(dest, 128, m);
1732 // Connect the A/D to the peak-detected low-frequency path.
1733 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1734 // Now set up the SSC to get the ADC samples that are now streaming at us.
1735 FpgaSetupSsc();
1736
1737 SendForward(fwd_bit_count);
1738
1739 // Now do the acquisition
1740 i = 0;
1741 for(;;) {
1742 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1743 AT91C_BASE_SSC->SSC_THR = 0x43;
1744 }
1745 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1746 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1747 i++;
1748 if (i >= m) break;
1749 }
1750 }
1751 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1752 LED_D_OFF();
1753}
1754
1755void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1756
1757 uint8_t fwd_bit_count;
1758
1759 //If password mode do login
1760 if (PwdMode == 1) Login(Pwd);
1761
1762 forward_ptr = forwardLink_data;
1763 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1764 fwd_bit_count += Prepare_Addr( Address );
1765 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1766
1767 SendForward(fwd_bit_count);
1768
1769 //Wait for write to complete
1770 SpinDelay(20);
1771 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1772 LED_D_OFF();
1773}
1774
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