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Add defines for reset type
[proxmark3-svn] / include / at91sam7s128.h
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6658905f 1//-----------------------------------------------------------------------------\r
2// Incomplete register definitions for the AT91SAM7S128 chip.\r
3// Jonathan Westhues, Jul 2005\r
4//-----------------------------------------------------------------------------\r
5\r
6#ifndef __AT91SAM7S128_H\r
7#define __AT91SAM7S128_H\r
8\r
9#define REG(x) (*(volatile unsigned long *)(x))\r
10\r
11//-------------\r
12// Peripheral IDs\r
13\r
14#define PERIPH_AIC_FIQ 0\r
15#define PERIPH_SYSIRQ 1\r
16#define PERIPH_PIOA 2\r
17#define PERIPH_ADC 4\r
18#define PERIPH_SPI 5\r
19#define PERIPH_US0 6\r
20#define PERIPH_US1 7\r
21#define PERIPH_SSC 8\r
22#define PERIPH_TWI 9\r
23#define PERIPH_PWMC 10\r
24#define PERIPH_UDP 11\r
25#define PERIPH_TC0 12\r
26#define PERIPH_TC1 13\r
27#define PERIPH_TC2 14\r
28#define PERIPH_AIC_IRQ0 30\r
29#define PERIPH_AIC_IRQ1 31\r
30\r
31//-------------\r
32// Reset Controller\r
33\r
34#define RSTC_BASE (0xfffffd00)\r
35\r
36#define RSTC_CONTROL REG(RSTC_BASE+0x00)\r
d5d42c0a 37#define RSTC_STATUS REG(RSTC_BASE+0x04)\r
6658905f 38\r
39#define RST_CONTROL_KEY (0xa5<<24)\r
40#define RST_CONTROL_PROCESSOR_RESET (1<<0)\r
d5d42c0a 41#define RST_STATUS_TYPE_MASK (7<<8)\r
42#define RST_STATUS_TYPE_POWERUP (0<<8)\r
43#define RST_STATUS_TYPE_WATCHDOG (2<<8)\r
44#define RST_STATUS_TYPE_SOFTWARE (3<<8)\r
45#define RST_STATUS_TYPE_USER (4<<8)\r
46#define RST_STATUS_TYPE_BROWNOUT (5<<8)\r
47\r
6658905f 48\r
49//-------------\r
50// PWM Controller\r
51\r
52#define PWM_BASE (0xfffcc000)\r
53\r
54#define PWM_MODE REG(PWM_BASE+0x00)\r
55#define PWM_ENABLE REG(PWM_BASE+0x04)\r
56#define PWM_DISABLE REG(PWM_BASE+0x08)\r
57#define PWM_STATUS REG(PWM_BASE+0x0c)\r
58#define PWM_INTERRUPT_ENABLE REG(PWM_BASE+0x10)\r
59#define PWM_INTERRUPT_DISABLE REG(PWM_BASE+0x14)\r
60#define PWM_INTERRUPT_MASK REG(PWM_BASE+0x18)\r
61#define PWM_INTERRUPT_STATUS REG(PWM_BASE+0x1c)\r
62#define PWM_CH_MODE(x) REG(PWM_BASE+0x200+((x)*0x20))\r
63#define PWM_CH_DUTY_CYCLE(x) REG(PWM_BASE+0x204+((x)*0x20))\r
64#define PWM_CH_PERIOD(x) REG(PWM_BASE+0x208+((x)*0x20))\r
65#define PWM_CH_COUNTER(x) REG(PWM_BASE+0x20c+((x)*0x20))\r
66#define PWM_CH_UPDATE(x) REG(PWM_BASE+0x210+((x)*0x20))\r
67\r
68#define PWM_MODE_DIVA(x) ((x)<<0)\r
69#define PWM_MODE_PREA(x) ((x)<<8)\r
70#define PWM_MODE_DIVB(x) ((x)<<16)\r
71#define PWM_MODE_PREB(x) ((x)<<24)\r
72\r
73#define PWM_CHANNEL(x) (1<<(x))\r
74\r
75#define PWM_CH_MODE_PRESCALER(x) ((x)<<0)\r
76#define PWM_CH_MODE_PERIOD_CENTER_ALIGNED (1<<8)\r
77#define PWM_CH_MODE_POLARITY_STARTS_HIGH (1<<9)\r
78#define PWM_CH_MODE_UPDATE_UPDATES_PERIOD (1<<10)\r
79\r
80//-------------\r
81// Debug Unit\r
82\r
83#define DBG_BASE (0xfffff200)\r
84\r
85#define DBGU_CR REG(DBG_BASE+0x0000)\r
86#define DBGU_MR REG(DBG_BASE+0x0004)\r
87#define DBGU_IER REG(DBG_BASE+0x0008)\r
88#define DBGU_IDR REG(DBG_BASE+0x000C)\r
89#define DBGU_IMR REG(DBG_BASE+0x0010)\r
90#define DBGU_SR REG(DBG_BASE+0x0014)\r
91#define DBGU_RHR REG(DBG_BASE+0x0018)\r
92#define DBGU_THR REG(DBG_BASE+0x001C)\r
93#define DBGU_BRGR REG(DBG_BASE+0x0020)\r
94#define DBGU_CIDR REG(DBG_BASE+0x0040)\r
95#define DBGU_EXID REG(DBG_BASE+0x0044)\r
96#define DBGU_FNR REG(DBG_BASE+0x0048)\r
97\r
98//-------------\r
99// Embedded Flash Controller\r
100\r
101#define MC_BASE (0xffffff00)\r
102\r
103#define MC_FLASH_MODE0 REG(MC_BASE+0x60)\r
104#define MC_FLASH_COMMAND REG(MC_BASE+0x64)\r
105#define MC_FLASH_STATUS REG(MC_BASE+0x68)\r
106#define MC_FLASH_MODE1 REG(MC_BASE+0x70)\r
107\r
108#define MC_FLASH_MODE_READY_INTERRUPT_ENABLE (1<<0)\r
109#define MC_FLASH_MODE_LOCK_INTERRUPT_ENABLE (1<<2)\r
110#define MC_FLASH_MODE_PROG_ERROR_INTERRUPT_ENABLE (1<<3)\r
111#define MC_FLASH_MODE_NO_ERASE_BEFORE_PROGRAMMING (1<<7)\r
112#define MC_FLASH_MODE_FLASH_WAIT_STATES(x) ((x)<<8)\r
113#define MC_FLASH_MODE_MASTER_CLK_IN_MHZ(x) ((x)<<16)\r
114\r
115#define MC_FLASH_COMMAND_FCMD(x) ((x)<<0)\r
116#define MC_FLASH_COMMAND_PAGEN(x) ((x)<<8)\r
117#define MC_FLASH_COMMAND_KEY ((0x5a)<<24)\r
118\r
119#define FCMD_NOP 0x0\r
120#define FCMD_WRITE_PAGE 0x1\r
121#define FCMD_SET_LOCK_BIT 0x2\r
122#define FCMD_WRITE_PAGE_LOCK 0x3\r
123#define FCMD_CLEAR_LOCK_BIT 0x4\r
124#define FCMD_ERASE_ALL 0x8\r
125#define FCMD_SET_GP_NVM_BIT 0xb\r
126#define FCMD_SET_SECURITY_BIT 0xf\r
127\r
128#define MC_FLASH_STATUS_READY (1<<0)\r
129#define MC_FLASH_STATUS_LOCK_ERROR (1<<2)\r
130#define MC_FLASH_STATUS_PROGRAMMING_ERROR (1<<3)\r
131#define MC_FLASH_STATUS_SECURITY_BIT_ACTIVE (1<<4)\r
132#define MC_FLASH_STATUS_GP_NVM_ACTIVE_0 (1<<8)\r
133#define MC_FLASH_STATUS_GP_NVM_ACTIVE_1 (1<<9)\r
134#define MC_FLASH_STATUS_LOCK_ACTIVE(x) (1<<((x)+16))\r
135\r
136#define FLASH_PAGE_SIZE_BYTES 256\r
137#define FLASH_PAGE_COUNT 512\r
138\r
139//-------------\r
140// Watchdog Timer - 12 bit down counter, uses slow clock divided by 128 as source\r
141\r
142#define WDT_BASE (0xfffffd40)\r
143\r
144#define WDT_CONTROL REG(WDT_BASE+0x00)\r
145#define WDT_MODE REG(WDT_BASE+0x04)\r
146#define WDT_STATUS REG(WDT_BASE+0x08)\r
147\r
148#define WDT_HIT() WDT_CONTROL = 0xa5000001\r
149\r
150#define WDT_MODE_COUNT(x) ((x)<<0)\r
151#define WDT_MODE_INTERRUPT_ON_EVENT (1<<12)\r
152#define WDT_MODE_RESET_ON_EVENT_ENABLE (1<<13)\r
153#define WDT_MODE_RESET_ON_EVENT (1<<14)\r
154#define WDT_MODE_WATCHDOG_DELTA(x) ((x)<<16)\r
155#define WDT_MODE_HALT_IN_DEBUG_MODE (1<<28)\r
156#define WDT_MODE_HALT_IN_IDLE_MODE (1<<29)\r
157#define WDT_MODE_DISABLE (1<<15)\r
158\r
159//-------------\r
160// Parallel Input/Output Controller\r
161\r
162#define PIO_BASE (0xfffff400)\r
163\r
164#define PIO_ENABLE REG(PIO_BASE+0x000)\r
165#define PIO_DISABLE REG(PIO_BASE+0x004)\r
166#define PIO_STATUS REG(PIO_BASE+0x008)\r
167#define PIO_OUTPUT_ENABLE REG(PIO_BASE+0x010)\r
168#define PIO_OUTPUT_DISABLE REG(PIO_BASE+0x014)\r
169#define PIO_OUTPUT_STATUS REG(PIO_BASE+0x018)\r
170#define PIO_GLITCH_ENABLE REG(PIO_BASE+0x020)\r
171#define PIO_GLITCH_DISABLE REG(PIO_BASE+0x024)\r
172#define PIO_GLITCH_STATUS REG(PIO_BASE+0x028)\r
173#define PIO_OUTPUT_DATA_SET REG(PIO_BASE+0x030)\r
174#define PIO_OUTPUT_DATA_CLEAR REG(PIO_BASE+0x034)\r
175#define PIO_OUTPUT_DATA_STATUS REG(PIO_BASE+0x038)\r
176#define PIO_PIN_DATA_STATUS REG(PIO_BASE+0x03c)\r
177#define PIO_OPEN_DRAIN_ENABLE REG(PIO_BASE+0x050)\r
178#define PIO_OPEN_DRAIN_DISABLE REG(PIO_BASE+0x054)\r
179#define PIO_OPEN_DRAIN_STATUS REG(PIO_BASE+0x058)\r
180#define PIO_NO_PULL_UP_ENABLE REG(PIO_BASE+0x060)\r
181#define PIO_NO_PULL_UP_DISABLE REG(PIO_BASE+0x064)\r
182#define PIO_NO_PULL_UP_STATUS REG(PIO_BASE+0x068)\r
183#define PIO_PERIPHERAL_A_SEL REG(PIO_BASE+0x070)\r
184#define PIO_PERIPHERAL_B_SEL REG(PIO_BASE+0x074)\r
185#define PIO_PERIPHERAL_WHICH REG(PIO_BASE+0x078)\r
186#define PIO_OUT_WRITE_ENABLE REG(PIO_BASE+0x0a0)\r
187#define PIO_OUT_WRITE_DISABLE REG(PIO_BASE+0x0a4)\r
188#define PIO_OUT_WRITE_STATUS REG(PIO_BASE+0x0a8)\r
189\r
190//-------------\r
191// USB Device Port\r
192\r
193#define UDP_BASE (0xfffb0000)\r
194\r
195#define UDP_FRAME_NUMBER REG(UDP_BASE+0x0000)\r
196#define UDP_GLOBAL_STATE REG(UDP_BASE+0x0004)\r
197#define UDP_FUNCTION_ADDR REG(UDP_BASE+0x0008)\r
198#define UDP_INTERRUPT_ENABLE REG(UDP_BASE+0x0010)\r
199#define UDP_INTERRUPT_DISABLE REG(UDP_BASE+0x0014)\r
200#define UDP_INTERRUPT_MASK REG(UDP_BASE+0x0018)\r
201#define UDP_INTERRUPT_STATUS REG(UDP_BASE+0x001c)\r
202#define UDP_INTERRUPT_CLEAR REG(UDP_BASE+0x0020)\r
203#define UDP_RESET_ENDPOINT REG(UDP_BASE+0x0028)\r
204#define UDP_ENDPOINT_CSR(x) REG(UDP_BASE+0x0030+((x)*4))\r
205#define UDP_ENDPOINT_FIFO(x) REG(UDP_BASE+0x0050+((x)*4))\r
206#define UDP_TRANSCEIVER_CTRL REG(UDP_BASE+0x0074)\r
207\r
208#define UDP_GLOBAL_STATE_ADDRESSED (1<<0)\r
209#define UDP_GLOBAL_STATE_CONFIGURED (1<<1)\r
210#define UDP_GLOBAL_STATE_SEND_RESUME_ENABLED (1<<2)\r
211#define UDP_GLOBAL_STATE_RESUME_RECEIVED (1<<3)\r
212#define UDP_GLOBAL_STATE_REMOTE_WAKE_UP_ENABLED (1<<4)\r
213\r
214#define UDP_FUNCTION_ADDR_ENABLED (1<<8)\r
215\r
216#define UDP_INTERRUPT_ENDPOINT(x) (1<<(x))\r
217#define UDP_INTERRUPT_SUSPEND (1<<8)\r
218#define UDP_INTERRUPT_RESUME (1<<9)\r
219#define UDP_INTERRUPT_EXTERNAL_RESUME (1<<10)\r
220#define UDP_INTERRUPT_SOF (1<<11)\r
221#define UDP_INTERRUPT_END_OF_BUS_RESET (1<<12)\r
222#define UDP_INTERRUPT_WAKEUP (1<<13)\r
223\r
224#define UDP_RESET_ENDPOINT_NUMBER(x) (1<<(x))\r
225\r
226#define UDP_CSR_TX_PACKET_ACKED (1<<0)\r
227#define UDP_CSR_RX_PACKET_RECEIVED_BANK_0 (1<<1)\r
228#define UDP_CSR_RX_HAVE_READ_SETUP_DATA (1<<2)\r
229#define UDP_CSR_STALL_SENT (1<<3)\r
230#define UDP_CSR_TX_PACKET (1<<4)\r
231#define UDP_CSR_FORCE_STALL (1<<5)\r
232#define UDP_CSR_RX_PACKET_RECEIVED_BANK_1 (1<<6)\r
233#define UDP_CSR_CONTROL_DATA_DIR (1<<7)\r
234#define UDP_CSR_EPTYPE_CONTROL (0<<8)\r
235#define UDP_CSR_EPTYPE_ISOCHRON_OUT (1<<8)\r
236#define UDP_CSR_EPTYPE_ISOCHRON_IN (5<<8)\r
237#define UDP_CSR_EPTYPE_BULK_OUT (2<<8)\r
238#define UDP_CSR_EPTYPE_BULK_IN (6<<8)\r
239#define UDP_CSR_EPTYPE_INTERRUPT_OUT (3<<8)\r
240#define UDP_CSR_EPTYPE_INTERRUPT_IN (7<<8)\r
241#define UDP_CSR_IS_DATA1 (1<<11)\r
242#define UDP_CSR_ENABLE_EP (1<<15)\r
243#define UDP_CSR_BYTES_RECEIVED(x) (((x) >> 16) & 0x7ff)\r
244\r
245#define UDP_TRANSCEIVER_CTRL_DISABLE (1<<8)\r
246\r
247//-------------\r
248// Power Management Controller\r
249\r
250#define PMC_BASE (0xfffffc00)\r
251\r
252#define PMC_SYS_CLK_ENABLE REG(PMC_BASE+0x0000)\r
253#define PMC_SYS_CLK_DISABLE REG(PMC_BASE+0x0004)\r
254#define PMC_SYS_CLK_STATUS REG(PMC_BASE+0x0008)\r
255#define PMC_PERIPHERAL_CLK_ENABLE REG(PMC_BASE+0x0010)\r
256#define PMC_PERIPHERAL_CLK_DISABLE REG(PMC_BASE+0x0014)\r
257#define PMC_PERIPHERAL_CLK_STATUS REG(PMC_BASE+0x0018)\r
258#define PMC_MAIN_OSCILLATOR REG(PMC_BASE+0x0020)\r
259#define PMC_MAIN_CLK_FREQUENCY REG(PMC_BASE+0x0024)\r
260#define PMC_PLL REG(PMC_BASE+0x002c)\r
261#define PMC_MASTER_CLK REG(PMC_BASE+0x0030)\r
262#define PMC_PROGRAMMABLE_CLK_0 REG(PMC_BASE+0x0040)\r
263#define PMC_PROGRAMMABLE_CLK_1 REG(PMC_BASE+0x0044)\r
264#define PMC_INTERRUPT_ENABLE REG(PMC_BASE+0x0060)\r
265#define PMC_INTERRUPT_DISABLE REG(PMC_BASE+0x0064)\r
266#define PMC_INTERRUPT_STATUS REG(PMC_BASE+0x0068)\r
267#define PMC_INTERRUPT_MASK REG(PMC_BASE+0x006c)\r
268\r
269#define PMC_SYS_CLK_PROCESSOR_CLK (1<<0)\r
270#define PMC_SYS_CLK_UDP_CLK (1<<7)\r
271#define PMC_SYS_CLK_PROGRAMMABLE_CLK_0 (1<<8)\r
272#define PMC_SYS_CLK_PROGRAMMABLE_CLK_1 (1<<9)\r
273#define PMC_SYS_CLK_PROGRAMMABLE_CLK_2 (1<<10)\r
274\r
275#define PMC_MAIN_OSCILLATOR_STABILIZED (1<<0)\r
276#define PMC_MAIN_OSCILLATOR_PLL_LOCK (1<<2)\r
277#define PMC_MAIN_OSCILLATOR_MCK_READY (1<<3)\r
278#define PMC_MAIN_OSCILLATOR_ENABLE (1<<0)\r
279#define PMC_MAIN_OSCILLATOR_BYPASS (1<<1)\r
280#define PMC_MAIN_OSCILLATOR_STARTUP_DELAY(x) ((x)<<8)\r
281\r
282#define PMC_PLL_DIVISOR(x) (x)\r
283#define PMC_PLL_COUNT_BEFORE_LOCK(x) ((x)<<8)\r
284#define PMC_PLL_FREQUENCY_RANGE(x) ((x)<<14)\r
285#define PMC_PLL_MULTIPLIER(x) (((x)-1)<<16)\r
286#define PMC_PLL_USB_DIVISOR(x) ((x)<<28)\r
287\r
288#define PMC_CLK_SELECTION_PLL_CLOCK (3<<0)\r
289#define PMC_CLK_SELECTION_MAIN_CLOCK (1<<0)\r
290#define PMC_CLK_SELECTION_SLOW_CLOCK (0<<0)\r
291#define PMC_CLK_PRESCALE_DIV_1 (0<<2)\r
292#define PMC_CLK_PRESCALE_DIV_2 (1<<2)\r
293#define PMC_CLK_PRESCALE_DIV_4 (2<<2)\r
294#define PMC_CLK_PRESCALE_DIV_8 (3<<2)\r
295#define PMC_CLK_PRESCALE_DIV_16 (4<<2)\r
296#define PMC_CLK_PRESCALE_DIV_32 (5<<2)\r
297#define PMC_CLK_PRESCALE_DIV_64 (6<<2)\r
298\r
299//-------------\r
300// Serial Peripheral Interface (SPI)\r
301\r
302#define SPI_BASE (0xfffe0000)\r
303\r
304#define SPI_CONTROL REG(SPI_BASE+0x00)\r
305#define SPI_MODE REG(SPI_BASE+0x04)\r
306#define SPI_RX_DATA REG(SPI_BASE+0x08)\r
307#define SPI_TX_DATA REG(SPI_BASE+0x0c)\r
308#define SPI_STATUS REG(SPI_BASE+0x10)\r
309#define SPI_INTERRUPT_ENABLE REG(SPI_BASE+0x14)\r
310#define SPI_INTERRUPT_DISABLE REG(SPI_BASE+0x18)\r
311#define SPI_INTERRUPT_MASK REG(SPI_BASE+0x1c)\r
312#define SPI_FOR_CHIPSEL_0 REG(SPI_BASE+0x30)\r
313#define SPI_FOR_CHIPSEL_1 REG(SPI_BASE+0x34)\r
314#define SPI_FOR_CHIPSEL_2 REG(SPI_BASE+0x38)\r
315#define SPI_FOR_CHIPSEL_3 REG(SPI_BASE+0x3c)\r
316\r
317#define SPI_CONTROL_ENABLE (1<<0)\r
318#define SPI_CONTROL_DISABLE (1<<1)\r
319#define SPI_CONTROL_RESET (1<<7)\r
320#define SPI_CONTROL_LAST_TRANSFER (1<<24)\r
321\r
322#define SPI_MODE_MASTER (1<<0)\r
323#define SPI_MODE_VARIABLE_CHIPSEL (1<<1)\r
324#define SPI_MODE_CHIPSELS_DECODED (1<<2)\r
325#define SPI_MODE_USE_DIVIDED_CLOCK (1<<3)\r
326#define SPI_MODE_MODE_FAULT_DETECTION_OFF (1<<4)\r
327#define SPI_MODE_LOOPBACK (1<<7)\r
328#define SPI_MODE_CHIPSEL(x) ((x)<<16)\r
329#define SPI_MODE_DELAY_BETWEEN_CHIPSELS(x) ((x)<<24)\r
330\r
331#define SPI_RX_DATA_CHIPSEL(x) (((x)>>16)&0xf)\r
332\r
333#define SPI_TX_DATA_CHIPSEL(x) ((x)<<16)\r
334#define SPI_TX_DATA_LAST_TRANSFER (1<<24)\r
335\r
336#define SPI_STATUS_RECEIVE_FULL (1<<0)\r
337#define SPI_STATUS_TRANSMIT_EMPTY (1<<1)\r
338#define SPI_STATUS_MODE_FAULT (1<<2)\r
339#define SPI_STATUS_OVERRUN (1<<3)\r
340#define SPI_STATUS_END_OF_RX_BUFFER (1<<4)\r
341#define SPI_STATUS_END_OF_TX_BUFFER (1<<5)\r
342#define SPI_STATUS_RX_BUFFER_FULL (1<<6)\r
343#define SPI_STATUS_TX_BUFFER_EMPTY (1<<7)\r
344#define SPI_STATUS_NSS_RISING_DETECTED (1<<8)\r
345#define SPI_STATUS_TX_EMPTY (1<<9)\r
346#define SPI_STATUS_SPI_ENABLED (1<<16)\r
347\r
348#define SPI_FOR_CHIPSEL_INACTIVE_CLK_1 (1<<0)\r
349#define SPI_FOR_CHIPSEL_PHASE (1<<1)\r
350#define SPI_FOR_CHIPSEL_LEAVE_CHIPSEL_LOW (1<<3)\r
351#define SPI_FOR_CHIPSEL_BITS_IN_WORD(x) ((x)<<4)\r
352#define SPI_FOR_CHIPSEL_DIVISOR(x) ((x)<<8)\r
353#define SPI_FOR_CHIPSEL_DELAY_BEFORE_CLK(x) ((x)<<16)\r
354#define SPI_FOR_CHIPSEL_INTERWORD_DELAY(x) ((x)<<24)\r
355\r
356//-------------\r
357// Analog to Digital Converter\r
358\r
359#define ADC_BASE (0xfffd8000)\r
360\r
361#define ADC_CONTROL REG(ADC_BASE+0x00)\r
362#define ADC_MODE REG(ADC_BASE+0x04)\r
363#define ADC_CHANNEL_ENABLE REG(ADC_BASE+0x10)\r
364#define ADC_CHANNEL_DISABLE REG(ADC_BASE+0x14)\r
365#define ADC_CHANNEL_STATUS REG(ADC_BASE+0x18)\r
366#define ADC_STATUS REG(ADC_BASE+0x1c)\r
367#define ADC_LAST_CONVERTED_DATA REG(ADC_BASE+0x20)\r
368#define ADC_INTERRUPT_ENABLE REG(ADC_BASE+0x24)\r
369#define ADC_INTERRUPT_DISABLE REG(ADC_BASE+0x28)\r
370#define ADC_INTERRUPT_MASK REG(ADC_BASE+0x2c)\r
371#define ADC_CHANNEL_DATA(x) REG(ADC_BASE+0x30+(4*(x)))\r
372\r
373#define ADC_CONTROL_RESET (1<<0)\r
374#define ADC_CONTROL_START (1<<1)\r
375\r
376#define ADC_MODE_HW_TRIGGERS_ENABLED (1<<0)\r
377#define ADC_MODE_8_BIT_RESOLUTION (1<<4)\r
378#define ADC_MODE_SLEEP (1<<5)\r
379#define ADC_MODE_PRESCALE(x) ((x)<<8)\r
380#define ADC_MODE_STARTUP_TIME(x) ((x)<<16)\r
381#define ADC_MODE_SAMPLE_HOLD_TIME(x) ((x)<<24)\r
382\r
383#define ADC_CHANNEL(x) (1<<(x))\r
384\r
385#define ADC_END_OF_CONVERSION(x) (1<<(x))\r
386#define ADC_OVERRUN_ERROR(x) (1<<(8+(x)))\r
387#define ADC_DATA_READY (1<<16)\r
388#define ADC_GENERAL_OVERRUN (1<<17)\r
389#define ADC_END_OF_RX_BUFFER (1<<18)\r
390#define ADC_RX_BUFFER_FULL (1<<19)\r
391\r
846225d5 392#define ADC_CHAN_LF 4\r
393#define ADC_CHAN_HF 5\r
6658905f 394//-------------\r
395// Synchronous Serial Controller\r
396\r
397#define SSC_BASE (0xfffd4000)\r
398\r
399#define SSC_CONTROL REG(SSC_BASE+0x00)\r
400#define SSC_CLOCK_DIVISOR REG(SSC_BASE+0x04)\r
401#define SSC_RECEIVE_CLOCK_MODE REG(SSC_BASE+0x10)\r
402#define SSC_RECEIVE_FRAME_MODE REG(SSC_BASE+0x14)\r
403#define SSC_TRANSMIT_CLOCK_MODE REG(SSC_BASE+0x18)\r
404#define SSC_TRANSMIT_FRAME_MODE REG(SSC_BASE+0x1c)\r
405#define SSC_RECEIVE_HOLDING REG(SSC_BASE+0x20)\r
406#define SSC_TRANSMIT_HOLDING REG(SSC_BASE+0x24)\r
407#define SSC_RECEIVE_SYNC_HOLDING REG(SSC_BASE+0x30)\r
408#define SSC_TRANSMIT_SYNC_HOLDING REG(SSC_BASE+0x34)\r
409#define SSC_STATUS REG(SSC_BASE+0x40)\r
410#define SSC_INTERRUPT_ENABLE REG(SSC_BASE+0x44)\r
411#define SSC_INTERRUPT_DISABLE REG(SSC_BASE+0x48)\r
412#define SSC_INTERRUPT_MASK REG(SSC_BASE+0x4c)\r
413\r
414#define SSC_CONTROL_RX_ENABLE (1<<0)\r
415#define SSC_CONTROL_RX_DISABLE (1<<1)\r
416#define SSC_CONTROL_TX_ENABLE (1<<8)\r
417#define SSC_CONTROL_TX_DISABLE (1<<9)\r
418#define SSC_CONTROL_RESET (1<<15)\r
419\r
420#define SSC_CLOCK_MODE_SELECT(x) ((x)<<0)\r
421#define SSC_CLOCK_MODE_OUTPUT(x) ((x)<<2)\r
422#define SSC_CLOCK_MODE_INVERT (1<<5)\r
423#define SSC_CLOCK_MODE_START(x) ((x)<<8)\r
424#define SSC_CLOCK_MODE_START_DELAY(x) ((x)<<16)\r
425#define SSC_CLOCK_MODE_FRAME_PERIOD(x) ((x)<<24)\r
426\r
427#define SSC_FRAME_MODE_BITS_IN_WORD(x) (((x)-1)<<0)\r
428#define SSC_FRAME_MODE_LOOPBACK (1<<5) // for RX\r
429#define SSC_FRAME_MODE_DEFAULT_IS_1 (1<<5) // for TX\r
430#define SSC_FRAME_MODE_MSB_FIRST (1<<7)\r
431#define SSC_FRAME_MODE_WORDS_PER_TRANSFER(x) ((x)<<8)\r
432#define SSC_FRAME_MODE_FRAME_SYNC_LEN(x) ((x)<<16)\r
433#define SSC_FRAME_MODE_FRAME_SYNC_TYPE(x) ((x)<<20)\r
434#define SSC_FRAME_MODE_SYNC_DATA_ENABLE (1<<23) // for TX only\r
435#define SSC_FRAME_MODE_NEGATIVE_EDGE (1<<24)\r
436\r
437#define SSC_STATUS_TX_READY (1<<0)\r
438#define SSC_STATUS_TX_EMPTY (1<<1)\r
439#define SSC_STATUS_TX_ENDED (1<<2)\r
440#define SSC_STATUS_TX_BUF_EMPTY (1<<3)\r
441#define SSC_STATUS_RX_READY (1<<4)\r
442#define SSC_STATUS_RX_OVERRUN (1<<5)\r
443#define SSC_STATUS_RX_ENDED (1<<6)\r
444#define SSC_STATUS_RX_BUF_FULL (1<<7)\r
445#define SSC_STATUS_TX_SYNC_OCCURRED (1<<10)\r
446#define SSC_STATUS_RX_SYNC_OCCURRED (1<<11)\r
447#define SSC_STATUS_TX_ENABLED (1<<16)\r
448#define SSC_STATUS_RX_ENABLED (1<<17)\r
449\r
450//-------------\r
451// Peripheral DMA Controller\r
452//\r
453// There is one set of registers for every peripheral that supports DMA.\r
454\r
455#define PDC_RX_POINTER(x) REG((x)+0x100)\r
456#define PDC_RX_COUNTER(x) REG((x)+0x104)\r
457#define PDC_TX_POINTER(x) REG((x)+0x108)\r
458#define PDC_TX_COUNTER(x) REG((x)+0x10c)\r
459#define PDC_RX_NEXT_POINTER(x) REG((x)+0x110)\r
460#define PDC_RX_NEXT_COUNTER(x) REG((x)+0x114)\r
461#define PDC_TX_NEXT_POINTER(x) REG((x)+0x118)\r
462#define PDC_TX_NEXT_COUNTER(x) REG((x)+0x11c)\r
463#define PDC_CONTROL(x) REG((x)+0x120)\r
464#define PDC_STATUS(x) REG((x)+0x124)\r
465\r
466#define PDC_RX_ENABLE (1<<0)\r
467#define PDC_RX_DISABLE (1<<1)\r
468#define PDC_TX_ENABLE (1<<8)\r
469#define PDC_TX_DISABLE (1<<9)\r
470\r
aae8787c 471//-------------\r
472// Timer/Counter base\r
473\r
474#define TC_BASE (0xfffa0000)\r
475\r
476#define TC_BCR REG(TC_BASE+0xC0)\r
477#define TC_BMR REG(TC_BASE+0xC4)\r
478\r
479#define TC_BCR_SYNC (1<<0)\r
480\r
481#define TC_CCR_CLKEN (1<<0)\r
482#define TC_CCR_CLKDIS (1<<1)\r
483#define TC_CCR_SWTRG (1<<2)\r
484\r
485#define TC_CMR_TCCLKS (7<<0)\r
486#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0<<0)\r
487#define TC_CMR_TCCLKS_TIMER_CLOCK2 (1<<0)\r
488#define TC_CMR_TCCLKS_TIMER_CLOCK3 (2<<0)\r
489#define TC_CMR_TCCLKS_TIMER_CLOCK4 (3<<0)\r
490#define TC_CMR_TCCLKS_TIMER_CLOCK5 (4<<0)\r
491#define TC_CMR_TCCLKS_XC0 (5<<0)\r
492#define TC_CMR_TCCLKS_XC1 (6<<0)\r
493#define TC_CMR_TCCLKS_XC2 (7<<0)\r
494#define TC_CMR_CLKI (1<<3)\r
495#define TC_CMR_BURST (3<<4)\r
496#define TC_CMR_BURST_XC0 (1<<4)\r
497#define TC_CMR_BURST_XC1 (2<<4)\r
498#define TC_CMR_BURST_XC2 (3<<4)\r
499#define TC_CMR_LDBSTOP (1<<6)\r
500#define TC_CMR_CPCSTOP (1<<6)\r
501#define TC_CMR_LDBDIS (1<<7)\r
502#define TC_CMR_CPCDIS (1<<7)\r
503#define TC_CMR_ETRGEDG (3<<8)\r
504#define TC_CMR_ETRGEDG_NONE (0<<8)\r
505#define TC_CMR_ETRGEDG_RISING (1<<8)\r
506#define TC_CMR_ETRGEDG_FALLING (2<<8)\r
507#define TC_CMR_ETRGEDG_EACH (3<<8)\r
508#define TC_CMR_EEVTEDG (3<<8)\r
509#define TC_CMR_EEVTEDG_NONE (0<<8)\r
510#define TC_CMR_EEVTEDG_RISING (1<<8)\r
511#define TC_CMR_EEVTEDG_FALLING (2<<8)\r
512#define TC_CMR_EEVTEDG_EACH (3<<8)\r
513#define TC_CMR_ABETRG (1<<10)\r
514#define TC_CMR_EEVT (3<<10)\r
515#define TC_CMR_EEVT_TIOB (0<<10)\r
516#define TC_CMR_EEVT_XC0 (1<<10)\r
517#define TC_CMR_EEVT_XC1 (2<<10)\r
518#define TC_CMR_EEVT_XC2 (3<<10)\r
519#define TC_CMR_ENETRG (1<<12)\r
520#define TC_CMR_WAVSEL (3<<13)\r
521#define TC_CMR_WAVSEL_UP (0<<13)\r
522#define TC_CMR_WAVSEL_UP_AUTO (2<<13)\r
523#define TC_CMR_WAVSEL_UPDOWN (1<<13)\r
524#define TC_CMR_WAVSEL_UPDOWN_AUTO (3<<13)\r
525#define TC_CMR_CPCTRG (1<<14)\r
526#define TC_CMR_WAVE (1<<15)\r
527#define TC_CMR_LDRA (3<<16)\r
528#define TC_CMR_LDRA_NONE (0<<16)\r
529#define TC_CMR_LDRA_RISING (1<<16)\r
530#define TC_CMR_LDRA_FALLING (2<<16)\r
531#define TC_CMR_LDRA_EACH (3<<16)\r
532#define TC_CMR_ACPA (3<<16)\r
533#define TC_CMR_ACPA_NONE (0<<16)\r
534#define TC_CMR_ACPA_SET (1<<16)\r
535#define TC_CMR_ACPA_CLEAR (2<<16)\r
536#define TC_CMR_ACPA_TOGGLE (3<<16)\r
537#define TC_CMR_LDRB (3<<18)\r
538#define TC_CMR_LDRB_NONE (0<<18)\r
539#define TC_CMR_LDRB_RISING (1<<18)\r
540#define TC_CMR_LDRB_FALLING (2<<18)\r
541#define TC_CMR_LDRB_EACH (3<<18)\r
542#define TC_CMR_ACPC (3<<18)\r
543#define TC_CMR_ACPC_NONE (0<<18)\r
544#define TC_CMR_ACPC_SET (1<<18)\r
545#define TC_CMR_ACPC_CLEAR (2<<18)\r
546#define TC_CMR_ACPC_TOGGLE (3<<18)\r
547#define TC_CMR_AEEVT (3<<20)\r
548#define TC_CMR_AEEVT_NONE (0<<20)\r
549#define TC_CMR_AEEVT_SET (1<<20)\r
550#define TC_CMR_AEEVT_CLEAR (2<<20)\r
551#define TC_CMR_AEEVT_TOGGLE (3<<20)\r
552#define TC_CMR_ASWTRG (3<<22)\r
553#define TC_CMR_ASWTRG_NONE (0<<22)\r
554#define TC_CMR_ASWTRG_SET (1<<22)\r
555#define TC_CMR_ASWTRG_CLEAR (2<<22)\r
556#define TC_CMR_ASWTRG_TOGGLE (3<<22)\r
557#define TC_CMR_BCPB (3<<24)\r
558#define TC_CMR_BCPB_NONE (0<<24)\r
559#define TC_CMR_BCPB_SET (1<<24)\r
560#define TC_CMR_BCPB_CLEAR (2<<24)\r
561#define TC_CMR_BCPB_TOGGLE (3<<24)\r
562#define TC_CMR_BCPC (3<<26)\r
563#define TC_CMR_BCPC_NONE (0<<26)\r
564#define TC_CMR_BCPC_SET (1<<26)\r
565#define TC_CMR_BCPC_CLEAR (2<<26)\r
566#define TC_CMR_BCPC_TOGGLE (3<<26)\r
567#define TC_CMR_BEEVT (3<<28)\r
568#define TC_CMR_BEEVT_NONE (0<<28)\r
569#define TC_CMR_BEEVT_SET (1<<28)\r
570#define TC_CMR_BEEVT_CLEAR (2<<28)\r
571#define TC_CMR_BEEVT_TOGGLE (3<<28)\r
572#define TC_CMR_BSWTRG (3<<30)\r
573#define TC_CMR_BSWTRG_NONE (0<<30)\r
574#define TC_CMR_BSWTRG_SET (1<<30)\r
575#define TC_CMR_BSWTRG_CLEAR (2<<30)\r
576#define TC_CMR_BSWTRG_TOGGLE (3<<30)\r
577\r
578#define TC_SR_COVFS (1<<0)\r
579#define TC_SR_LOVFS (1<<1)\r
580#define TC_SR_CPAS (1<<2)\r
581#define TC_SR_CPBS (1<<3)\r
582#define TC_SR_CPCS (1<<4)\r
583#define TC_SR_LDRAS (1<<5)\r
584#define TC_SR_LDRBS (1<<6)\r
585#define TC_SR_ETRGS (1<<7)\r
586#define TC_SR_CLKSTA (1<<16)\r
587#define TC_SR_MTIOA (1<<17)\r
588#define TC_SR_MTIOB (1<<18)\r
589\r
590//-------------\r
591// Timer/Counter 0\r
592\r
593#define TC0_BASE (TC_BASE+0x40*0)\r
594\r
595#define TC0_CCR REG(TC0_BASE+0x00)\r
596#define TC0_CMR REG(TC0_BASE+0x04)\r
597#define TC0_CV REG(TC0_BASE+0x10)\r
598#define TC0_RA REG(TC0_BASE+0x14)\r
599#define TC0_RB REG(TC0_BASE+0x18)\r
600#define TC0_RC REG(TC0_BASE+0x1C)\r
601#define TC0_SR REG(TC0_BASE+0x20)\r
602#define TC0_IER REG(TC0_BASE+0x24)\r
603#define TC0_IDR REG(TC0_BASE+0x28)\r
604#define TC0_IMR REG(TC0_BASE+0x2C)\r
605\r
606//-------------\r
607// Timer/Counter 1\r
608\r
609#define TC1_BASE (TC_BASE+0x40*1)\r
610\r
611#define TC1_CCR REG(TC1_BASE+0x00)\r
612#define TC1_CMR REG(TC1_BASE+0x04)\r
613#define TC1_CV REG(TC1_BASE+0x10)\r
614#define TC1_RA REG(TC1_BASE+0x14)\r
615#define TC1_RB REG(TC1_BASE+0x18)\r
616#define TC1_RC REG(TC1_BASE+0x1C)\r
617#define TC1_SR REG(TC1_BASE+0x20)\r
618#define TC1_IER REG(TC1_BASE+0x24)\r
619#define TC1_IDR REG(TC1_BASE+0x28)\r
620#define TC1_IMR REG(TC1_BASE+0x2C)\r
621\r
622//-------------\r
623// Timer/Counter 2\r
624\r
625#define TC2_BASE (TC_BASE+0x40*2)\r
626\r
627#define TC2_CCR REG(TC2_BASE+0x00)\r
628#define TC2_CMR REG(TC2_BASE+0x04)\r
629#define TC2_CV REG(TC2_BASE+0x10)\r
630#define TC2_RA REG(TC2_BASE+0x14)\r
631#define TC2_RB REG(TC2_BASE+0x18)\r
632#define TC2_RC REG(TC2_BASE+0x1C)\r
633#define TC2_SR REG(TC2_BASE+0x20)\r
634#define TC2_IER REG(TC2_BASE+0x24)\r
635#define TC2_IDR REG(TC2_BASE+0x28)\r
636#define TC2_IMR REG(TC2_BASE+0x2C)\r
637\r
638\r
6658905f 639#endif\r
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