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e09f21fa | 1 | //----------------------------------------------------------------------------- |
2 | // This code is licensed to you under the terms of the GNU GPL, version 2 or, | |
3 | // at your option, any later version. See the LICENSE.txt file for the text of | |
4 | // the license. | |
5 | //----------------------------------------------------------------------------- | |
6 | // Miscellaneous routines for low frequency tag operations. | |
7 | // Tags supported here so far are Texas Instruments (TI), HID | |
8 | // Also routines for raw mode reading/simulating of LF waveform | |
9 | //----------------------------------------------------------------------------- | |
10 | ||
11 | #include "proxmark3.h" | |
12 | #include "apps.h" | |
13 | #include "util.h" | |
14 | #include "hitag2.h" | |
15 | #include "crc16.h" | |
16 | #include "string.h" | |
17 | #include "lfdemod.h" | |
18 | #include "lfsampling.h" | |
1d0ccbe0 | 19 | #include "protocols.h" |
c0f15a05 | 20 | #include "usb_cdc.h" // for usb_poll_validate_length |
e09f21fa | 21 | |
f121b478 | 22 | #ifndef SHORT_COIL |
23 | # define SHORT_COIL() LOW(GPIO_SSC_DOUT) | |
24 | #endif | |
25 | #ifndef OPEN_COIL | |
26 | # define OPEN_COIL() HIGH(GPIO_SSC_DOUT) | |
27 | #endif | |
28 | ||
e09f21fa | 29 | /** |
30 | * Function to do a modulation and then get samples. | |
31 | * @param delay_off | |
95522869 | 32 | * @param periods 0xFFFF0000 is period_0, 0x0000FFFF is period_1 |
33 | * @param useHighFreg | |
e09f21fa | 34 | * @param command |
35 | */ | |
d0724780 | 36 | void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint32_t useHighFreq, uint8_t *command) |
e09f21fa | 37 | { |
d0724780 | 38 | /* Make sure the tag is reset */ |
39 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); | |
40 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
41 | SpinDelay(200); | |
e09f21fa | 42 | |
d0724780 | 43 | uint16_t period_0 = periods >> 16; |
44 | uint16_t period_1 = periods & 0xFFFF; | |
45 | ||
46 | // 95 == 125 KHz 88 == 124.8 KHz | |
95522869 | 47 | int divisor_used = (useHighFreq) ? 88 : 95; |
e09f21fa | 48 | sample_config sc = { 0,0,1, divisor_used, 0}; |
49 | setSamplingConfig(&sc); | |
d0724780 | 50 | |
c0f15a05 | 51 | //clear read buffer |
52 | BigBuf_Clear_keep_EM(); | |
e09f21fa | 53 | |
e09f21fa | 54 | LFSetupFPGAForADC(sc.divisor, 1); |
55 | ||
56 | // And a little more time for the tag to fully power up | |
d0724780 | 57 | SpinDelay(50); |
e09f21fa | 58 | |
e0165dcf | 59 | // now modulate the reader field |
60 | while(*command != '\0' && *command != ' ') { | |
61 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
62 | LED_D_OFF(); | |
63 | SpinDelayUs(delay_off); | |
e09f21fa | 64 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor); |
65 | ||
e0165dcf | 66 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
67 | LED_D_ON(); | |
68 | if(*(command++) == '0') | |
b4a6775b | 69 | SpinDelayUs(period_0); // ICEMAN: problem with (us) clock is 21.3us increments |
e0165dcf | 70 | else |
b4a6775b | 71 | SpinDelayUs(period_1); // ICEMAN: problem with (us) clock is 21.3us increments |
e0165dcf | 72 | } |
73 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
74 | LED_D_OFF(); | |
b4a6775b | 75 | SpinDelayUs(delay_off); // ICEMAN: problem with (us) clock is 21.3us increments |
e09f21fa | 76 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor); |
e0165dcf | 77 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
e09f21fa | 78 | |
e0165dcf | 79 | // now do the read |
e09f21fa | 80 | DoAcquisition_config(false); |
81 | } | |
82 | ||
e09f21fa | 83 | /* blank r/w tag data stream |
84 | ...0000000000000000 01111111 | |
85 | 1010101010101010101010101010101010101010101010101010101010101010 | |
86 | 0011010010100001 | |
87 | 01111111 | |
88 | 101010101010101[0]000... | |
89 | ||
90 | [5555fe852c5555555555555555fe0000] | |
91 | */ | |
92 | void ReadTItag(void) | |
93 | { | |
e0165dcf | 94 | // some hardcoded initial params |
95 | // when we read a TI tag we sample the zerocross line at 2Mhz | |
96 | // TI tags modulate a 1 as 16 cycles of 123.2Khz | |
97 | // TI tags modulate a 0 as 16 cycles of 134.2Khz | |
0de8e387 | 98 | #define FSAMPLE 2000000 |
99 | #define FREQLO 123200 | |
100 | #define FREQHI 134200 | |
e09f21fa | 101 | |
e0165dcf | 102 | signed char *dest = (signed char *)BigBuf_get_addr(); |
103 | uint16_t n = BigBuf_max_traceLen(); | |
104 | // 128 bit shift register [shift3:shift2:shift1:shift0] | |
105 | uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0; | |
106 | ||
107 | int i, cycles=0, samples=0; | |
108 | // how many sample points fit in 16 cycles of each frequency | |
109 | uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI; | |
110 | // when to tell if we're close enough to one freq or another | |
111 | uint32_t threshold = (sampleslo - sampleshi + 1)>>1; | |
112 | ||
113 | // TI tags charge at 134.2Khz | |
114 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); | |
115 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz | |
116 | ||
117 | // Place FPGA in passthrough mode, in this mode the CROSS_LO line | |
118 | // connects to SSP_DIN and the SSP_DOUT logic level controls | |
119 | // whether we're modulating the antenna (high) | |
120 | // or listening to the antenna (low) | |
121 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); | |
122 | ||
123 | // get TI tag data into the buffer | |
124 | AcquireTiType(); | |
125 | ||
126 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
127 | ||
128 | for (i=0; i<n-1; i++) { | |
129 | // count cycles by looking for lo to hi zero crossings | |
130 | if ( (dest[i]<0) && (dest[i+1]>0) ) { | |
131 | cycles++; | |
132 | // after 16 cycles, measure the frequency | |
133 | if (cycles>15) { | |
134 | cycles=0; | |
135 | samples=i-samples; // number of samples in these 16 cycles | |
136 | ||
137 | // TI bits are coming to us lsb first so shift them | |
138 | // right through our 128 bit right shift register | |
139 | shift0 = (shift0>>1) | (shift1 << 31); | |
140 | shift1 = (shift1>>1) | (shift2 << 31); | |
141 | shift2 = (shift2>>1) | (shift3 << 31); | |
142 | shift3 >>= 1; | |
143 | ||
144 | // check if the cycles fall close to the number | |
145 | // expected for either the low or high frequency | |
146 | if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) { | |
147 | // low frequency represents a 1 | |
148 | shift3 |= (1<<31); | |
149 | } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) { | |
150 | // high frequency represents a 0 | |
151 | } else { | |
152 | // probably detected a gay waveform or noise | |
153 | // use this as gaydar or discard shift register and start again | |
154 | shift3 = shift2 = shift1 = shift0 = 0; | |
155 | } | |
156 | samples = i; | |
157 | ||
158 | // for each bit we receive, test if we've detected a valid tag | |
159 | ||
160 | // if we see 17 zeroes followed by 6 ones, we might have a tag | |
161 | // remember the bits are backwards | |
162 | if ( ((shift0 & 0x7fffff) == 0x7e0000) ) { | |
163 | // if start and end bytes match, we have a tag so break out of the loop | |
164 | if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) { | |
165 | cycles = 0xF0B; //use this as a flag (ugly but whatever) | |
166 | break; | |
167 | } | |
168 | } | |
169 | } | |
170 | } | |
171 | } | |
172 | ||
173 | // if flag is set we have a tag | |
174 | if (cycles!=0xF0B) { | |
175 | DbpString("Info: No valid tag detected."); | |
176 | } else { | |
177 | // put 64 bit data into shift1 and shift0 | |
178 | shift0 = (shift0>>24) | (shift1 << 8); | |
179 | shift1 = (shift1>>24) | (shift2 << 8); | |
180 | ||
181 | // align 16 bit crc into lower half of shift2 | |
182 | shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff; | |
183 | ||
184 | // if r/w tag, check ident match | |
e09f21fa | 185 | if (shift3 & (1<<15) ) { |
e0165dcf | 186 | DbpString("Info: TI tag is rewriteable"); |
187 | // only 15 bits compare, last bit of ident is not valid | |
e09f21fa | 188 | if (((shift3 >> 16) ^ shift0) & 0x7fff ) { |
e0165dcf | 189 | DbpString("Error: Ident mismatch!"); |
190 | } else { | |
191 | DbpString("Info: TI tag ident is valid"); | |
192 | } | |
193 | } else { | |
194 | DbpString("Info: TI tag is readonly"); | |
195 | } | |
196 | ||
197 | // WARNING the order of the bytes in which we calc crc below needs checking | |
198 | // i'm 99% sure the crc algorithm is correct, but it may need to eat the | |
199 | // bytes in reverse or something | |
200 | // calculate CRC | |
201 | uint32_t crc=0; | |
202 | ||
203 | crc = update_crc16(crc, (shift0)&0xff); | |
204 | crc = update_crc16(crc, (shift0>>8)&0xff); | |
205 | crc = update_crc16(crc, (shift0>>16)&0xff); | |
206 | crc = update_crc16(crc, (shift0>>24)&0xff); | |
207 | crc = update_crc16(crc, (shift1)&0xff); | |
208 | crc = update_crc16(crc, (shift1>>8)&0xff); | |
209 | crc = update_crc16(crc, (shift1>>16)&0xff); | |
210 | crc = update_crc16(crc, (shift1>>24)&0xff); | |
211 | ||
1a570b0a | 212 | Dbprintf("Info: Tag data: %x%08x, crc=%x", (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF); |
e0165dcf | 213 | if (crc != (shift2&0xffff)) { |
214 | Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc); | |
215 | } else { | |
216 | DbpString("Info: CRC is good"); | |
217 | } | |
218 | } | |
e09f21fa | 219 | } |
220 | ||
221 | void WriteTIbyte(uint8_t b) | |
222 | { | |
e0165dcf | 223 | int i = 0; |
224 | ||
225 | // modulate 8 bits out to the antenna | |
226 | for (i=0; i<8; i++) | |
227 | { | |
228 | if (b&(1<<i)) { | |
229 | // stop modulating antenna | |
230 | LOW(GPIO_SSC_DOUT); | |
b4a6775b | 231 | SpinDelayUs(1000); // ICEMAN: problem with (us) clock is 21.3us increments |
e0165dcf | 232 | // modulate antenna |
233 | HIGH(GPIO_SSC_DOUT); | |
b4a6775b | 234 | SpinDelayUs(1000); // ICEMAN: problem with (us) clock is 21.3us increments |
e0165dcf | 235 | } else { |
236 | // stop modulating antenna | |
237 | LOW(GPIO_SSC_DOUT); | |
b4a6775b | 238 | SpinDelayUs(300); // ICEMAN: problem with (us) clock is 21.3us increments |
e0165dcf | 239 | // modulate antenna |
240 | HIGH(GPIO_SSC_DOUT); | |
b4a6775b | 241 | SpinDelayUs(1700); // ICEMAN: problem with (us) clock is 21.3us increments |
e0165dcf | 242 | } |
243 | } | |
e09f21fa | 244 | } |
245 | ||
246 | void AcquireTiType(void) | |
247 | { | |
e0165dcf | 248 | int i, j, n; |
249 | // tag transmission is <20ms, sampling at 2M gives us 40K samples max | |
250 | // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t | |
a739812e | 251 | #define TIBUFLEN 1250 |
e09f21fa | 252 | |
e0165dcf | 253 | // clear buffer |
a739812e | 254 | uint32_t *buf = (uint32_t *)BigBuf_get_addr(); |
255 | ||
256 | //clear buffer now so it does not interfere with timing later | |
257 | BigBuf_Clear_ext(false); | |
e0165dcf | 258 | |
259 | // Set up the synchronous serial port | |
260 | AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN; | |
261 | AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN; | |
262 | ||
263 | // steal this pin from the SSP and use it to control the modulation | |
264 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; | |
265 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; | |
266 | ||
267 | AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST; | |
268 | AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN; | |
269 | ||
270 | // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long | |
271 | // 48/2 = 24 MHz clock must be divided by 12 | |
272 | AT91C_BASE_SSC->SSC_CMR = 12; | |
273 | ||
274 | AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0); | |
275 | AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF; | |
276 | AT91C_BASE_SSC->SSC_TCMR = 0; | |
277 | AT91C_BASE_SSC->SSC_TFMR = 0; | |
c5e8b916 | 278 | // iceman, FpgaSetupSsc() ?? the code above? can it be replaced? |
e0165dcf | 279 | LED_D_ON(); |
280 | ||
281 | // modulate antenna | |
282 | HIGH(GPIO_SSC_DOUT); | |
283 | ||
284 | // Charge TI tag for 50ms. | |
285 | SpinDelay(50); | |
286 | ||
287 | // stop modulating antenna and listen | |
288 | LOW(GPIO_SSC_DOUT); | |
289 | ||
290 | LED_D_OFF(); | |
291 | ||
292 | i = 0; | |
293 | for(;;) { | |
294 | if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { | |
a739812e | 295 | buf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer |
e0165dcf | 296 | i++; if(i >= TIBUFLEN) break; |
297 | } | |
298 | WDT_HIT(); | |
299 | } | |
300 | ||
301 | // return stolen pin to SSP | |
302 | AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT; | |
303 | AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT; | |
304 | ||
305 | char *dest = (char *)BigBuf_get_addr(); | |
a739812e | 306 | n = TIBUFLEN * 32; |
307 | ||
e0165dcf | 308 | // unpack buffer |
a739812e | 309 | for (i = TIBUFLEN-1; i >= 0; i--) { |
310 | for (j = 0; j < 32; j++) { | |
311 | if(buf[i] & (1 << j)) { | |
e0165dcf | 312 | dest[--n] = 1; |
313 | } else { | |
314 | dest[--n] = -1; | |
315 | } | |
316 | } | |
317 | } | |
e09f21fa | 318 | } |
319 | ||
320 | // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc | |
321 | // if crc provided, it will be written with the data verbatim (even if bogus) | |
322 | // if not provided a valid crc will be computed from the data and written. | |
323 | void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc) | |
324 | { | |
e0165dcf | 325 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
326 | if(crc == 0) { | |
327 | crc = update_crc16(crc, (idlo)&0xff); | |
328 | crc = update_crc16(crc, (idlo>>8)&0xff); | |
329 | crc = update_crc16(crc, (idlo>>16)&0xff); | |
330 | crc = update_crc16(crc, (idlo>>24)&0xff); | |
331 | crc = update_crc16(crc, (idhi)&0xff); | |
332 | crc = update_crc16(crc, (idhi>>8)&0xff); | |
333 | crc = update_crc16(crc, (idhi>>16)&0xff); | |
334 | crc = update_crc16(crc, (idhi>>24)&0xff); | |
335 | } | |
a739812e | 336 | Dbprintf("Writing to tag: %x%08x, crc=%x", (unsigned int) idhi, (unsigned int) idlo, crc); |
e0165dcf | 337 | |
338 | // TI tags charge at 134.2Khz | |
339 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz | |
340 | // Place FPGA in passthrough mode, in this mode the CROSS_LO line | |
341 | // connects to SSP_DIN and the SSP_DOUT logic level controls | |
342 | // whether we're modulating the antenna (high) | |
343 | // or listening to the antenna (low) | |
344 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); | |
345 | LED_A_ON(); | |
346 | ||
347 | // steal this pin from the SSP and use it to control the modulation | |
348 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; | |
349 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; | |
350 | ||
351 | // writing algorithm: | |
352 | // a high bit consists of a field off for 1ms and field on for 1ms | |
353 | // a low bit consists of a field off for 0.3ms and field on for 1.7ms | |
354 | // initiate a charge time of 50ms (field on) then immediately start writing bits | |
355 | // start by writing 0xBB (keyword) and 0xEB (password) | |
356 | // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer) | |
357 | // finally end with 0x0300 (write frame) | |
1a570b0a | 358 | // all data is sent lsb first |
e0165dcf | 359 | // finish with 15ms programming time |
360 | ||
361 | // modulate antenna | |
362 | HIGH(GPIO_SSC_DOUT); | |
363 | SpinDelay(50); // charge time | |
364 | ||
365 | WriteTIbyte(0xbb); // keyword | |
366 | WriteTIbyte(0xeb); // password | |
367 | WriteTIbyte( (idlo )&0xff ); | |
368 | WriteTIbyte( (idlo>>8 )&0xff ); | |
369 | WriteTIbyte( (idlo>>16)&0xff ); | |
370 | WriteTIbyte( (idlo>>24)&0xff ); | |
371 | WriteTIbyte( (idhi )&0xff ); | |
372 | WriteTIbyte( (idhi>>8 )&0xff ); | |
373 | WriteTIbyte( (idhi>>16)&0xff ); | |
374 | WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo | |
375 | WriteTIbyte( (crc )&0xff ); // crc lo | |
376 | WriteTIbyte( (crc>>8 )&0xff ); // crc hi | |
377 | WriteTIbyte(0x00); // write frame lo | |
378 | WriteTIbyte(0x03); // write frame hi | |
379 | HIGH(GPIO_SSC_DOUT); | |
380 | SpinDelay(50); // programming time | |
381 | ||
382 | LED_A_OFF(); | |
383 | ||
384 | // get TI tag data into the buffer | |
385 | AcquireTiType(); | |
386 | ||
387 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
6c68b84a | 388 | DbpString("Now use `lf ti read` to check"); |
e09f21fa | 389 | } |
390 | ||
cd073027 | 391 | void SimulateTagLowFrequency(int period, int gap, int ledcontrol) |
e09f21fa | 392 | { |
f121b478 | 393 | int i = 0; |
e0165dcf | 394 | uint8_t *tab = BigBuf_get_addr(); |
e09f21fa | 395 | |
f121b478 | 396 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD); |
e09f21fa | 397 | |
e0165dcf | 398 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK; |
e0165dcf | 399 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; |
400 | AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK; | |
e09f21fa | 401 | |
e0165dcf | 402 | for(;;) { |
f121b478 | 403 | WDT_HIT(); |
404 | ||
405 | if (ledcontrol) LED_D_ON(); | |
406 | ||
e0165dcf | 407 | //wait until SSC_CLK goes HIGH |
408 | while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) { | |
e0165dcf | 409 | WDT_HIT(); |
f121b478 | 410 | if ( usb_poll_validate_length() || BUTTON_PRESS() ) { |
411 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
412 | LED_D_OFF(); | |
413 | return; | |
414 | } | |
e0165dcf | 415 | } |
f121b478 | 416 | |
e0165dcf | 417 | if(tab[i]) |
418 | OPEN_COIL(); | |
419 | else | |
420 | SHORT_COIL(); | |
421 | ||
a739812e | 422 | if (ledcontrol) LED_D_OFF(); |
423 | ||
e0165dcf | 424 | //wait until SSC_CLK goes LOW |
425 | while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) { | |
e0165dcf | 426 | WDT_HIT(); |
f121b478 | 427 | if ( usb_poll_validate_length() || BUTTON_PRESS() ) { |
428 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
429 | LED_D_OFF(); | |
430 | return; | |
431 | } | |
e0165dcf | 432 | } |
433 | ||
434 | i++; | |
435 | if(i == period) { | |
e0165dcf | 436 | i = 0; |
437 | if (gap) { | |
f121b478 | 438 | WDT_HIT(); |
e0165dcf | 439 | SHORT_COIL(); |
b4a6775b | 440 | SpinDelayUs(gap); // ICEMAN: problem with (us) clock is 21.3us increments |
e0165dcf | 441 | } |
442 | } | |
443 | } | |
e09f21fa | 444 | } |
445 | ||
e09f21fa | 446 | #define DEBUG_FRAME_CONTENTS 1 |
447 | void SimulateTagLowFrequencyBidir(int divisor, int t0) | |
448 | { | |
449 | } | |
450 | ||
451 | // compose fc/8 fc/10 waveform (FSK2) | |
452 | static void fc(int c, int *n) | |
453 | { | |
e0165dcf | 454 | uint8_t *dest = BigBuf_get_addr(); |
455 | int idx; | |
456 | ||
457 | // for when we want an fc8 pattern every 4 logical bits | |
458 | if(c==0) { | |
459 | dest[((*n)++)]=1; | |
460 | dest[((*n)++)]=1; | |
461 | dest[((*n)++)]=1; | |
462 | dest[((*n)++)]=1; | |
463 | dest[((*n)++)]=0; | |
464 | dest[((*n)++)]=0; | |
465 | dest[((*n)++)]=0; | |
466 | dest[((*n)++)]=0; | |
467 | } | |
468 | ||
469 | // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples | |
470 | if(c==8) { | |
471 | for (idx=0; idx<6; idx++) { | |
472 | dest[((*n)++)]=1; | |
473 | dest[((*n)++)]=1; | |
474 | dest[((*n)++)]=1; | |
475 | dest[((*n)++)]=1; | |
476 | dest[((*n)++)]=0; | |
477 | dest[((*n)++)]=0; | |
478 | dest[((*n)++)]=0; | |
479 | dest[((*n)++)]=0; | |
480 | } | |
481 | } | |
482 | ||
483 | // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples | |
484 | if(c==10) { | |
485 | for (idx=0; idx<5; idx++) { | |
486 | dest[((*n)++)]=1; | |
487 | dest[((*n)++)]=1; | |
488 | dest[((*n)++)]=1; | |
489 | dest[((*n)++)]=1; | |
490 | dest[((*n)++)]=1; | |
491 | dest[((*n)++)]=0; | |
492 | dest[((*n)++)]=0; | |
493 | dest[((*n)++)]=0; | |
494 | dest[((*n)++)]=0; | |
495 | dest[((*n)++)]=0; | |
496 | } | |
497 | } | |
e09f21fa | 498 | } |
499 | // compose fc/X fc/Y waveform (FSKx) | |
712ebfa6 | 500 | static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt) |
e09f21fa | 501 | { |
e0165dcf | 502 | uint8_t *dest = BigBuf_get_addr(); |
503 | uint8_t halfFC = fc/2; | |
504 | uint8_t wavesPerClock = clock/fc; | |
505 | uint8_t mod = clock % fc; //modifier | |
506 | uint8_t modAdj = fc/mod; //how often to apply modifier | |
507 | bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE; | |
508 | // loop through clock - step field clock | |
509 | for (uint8_t idx=0; idx < wavesPerClock; idx++){ | |
510 | // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave) | |
511 | memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here | |
512 | memset(dest+(*n)+(fc-halfFC), 1, halfFC); | |
513 | *n += fc; | |
514 | } | |
515 | if (mod>0) (*modCnt)++; | |
516 | if ((mod>0) && modAdjOk){ //fsk2 | |
517 | if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave | |
518 | memset(dest+(*n), 0, fc-halfFC); | |
519 | memset(dest+(*n)+(fc-halfFC), 1, halfFC); | |
520 | *n += fc; | |
521 | } | |
522 | } | |
523 | if (mod>0 && !modAdjOk){ //fsk1 | |
524 | memset(dest+(*n), 0, mod-(mod/2)); | |
525 | memset(dest+(*n)+(mod-(mod/2)), 1, mod/2); | |
526 | *n += mod; | |
527 | } | |
e09f21fa | 528 | } |
529 | ||
530 | // prepare a waveform pattern in the buffer based on the ID given then | |
531 | // simulate a HID tag until the button is pressed | |
532 | void CmdHIDsimTAG(int hi, int lo, int ledcontrol) | |
533 | { | |
f121b478 | 534 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
535 | set_tracing(FALSE); | |
536 | ||
537 | int n = 0, i = 0; | |
e0165dcf | 538 | /* |
539 | HID tag bitstream format | |
540 | The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits | |
541 | A 1 bit is represented as 6 fc8 and 5 fc10 patterns | |
542 | A 0 bit is represented as 5 fc10 and 6 fc8 patterns | |
543 | A fc8 is inserted before every 4 bits | |
544 | A special start of frame pattern is used consisting a0b0 where a and b are neither 0 | |
545 | nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10) | |
546 | */ | |
547 | ||
f121b478 | 548 | if (hi > 0xFFF) { |
e0165dcf | 549 | DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags"); |
550 | return; | |
551 | } | |
552 | fc(0,&n); | |
553 | // special start of frame marker containing invalid bit sequences | |
554 | fc(8, &n); fc(8, &n); // invalid | |
555 | fc(8, &n); fc(10, &n); // logical 0 | |
556 | fc(10, &n); fc(10, &n); // invalid | |
557 | fc(8, &n); fc(10, &n); // logical 0 | |
558 | ||
559 | WDT_HIT(); | |
560 | // manchester encode bits 43 to 32 | |
561 | for (i=11; i>=0; i--) { | |
562 | if ((i%4)==3) fc(0,&n); | |
563 | if ((hi>>i)&1) { | |
564 | fc(10, &n); fc(8, &n); // low-high transition | |
565 | } else { | |
566 | fc(8, &n); fc(10, &n); // high-low transition | |
567 | } | |
568 | } | |
569 | ||
570 | WDT_HIT(); | |
571 | // manchester encode bits 31 to 0 | |
572 | for (i=31; i>=0; i--) { | |
573 | if ((i%4)==3) fc(0,&n); | |
574 | if ((lo>>i)&1) { | |
575 | fc(10, &n); fc(8, &n); // low-high transition | |
576 | } else { | |
577 | fc(8, &n); fc(10, &n); // high-low transition | |
578 | } | |
579 | } | |
f121b478 | 580 | WDT_HIT(); |
581 | ||
a739812e | 582 | if (ledcontrol) LED_A_ON(); |
e0165dcf | 583 | SimulateTagLowFrequency(n, 0, ledcontrol); |
a739812e | 584 | if (ledcontrol) LED_A_OFF(); |
e09f21fa | 585 | } |
586 | ||
587 | // prepare a waveform pattern in the buffer based on the ID given then | |
588 | // simulate a FSK tag until the button is pressed | |
589 | // arg1 contains fcHigh and fcLow, arg2 contains invert and clock | |
590 | void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream) | |
591 | { | |
f121b478 | 592 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
593 | ||
594 | // free eventually allocated BigBuf memory | |
595 | BigBuf_free(); BigBuf_Clear_ext(false); | |
596 | clear_trace(); | |
597 | set_tracing(FALSE); | |
598 | ||
599 | int ledcontrol = 1, n = 0, i = 0; | |
e0165dcf | 600 | uint8_t fcHigh = arg1 >> 8; |
601 | uint8_t fcLow = arg1 & 0xFF; | |
602 | uint16_t modCnt = 0; | |
603 | uint8_t clk = arg2 & 0xFF; | |
604 | uint8_t invert = (arg2 >> 8) & 1; | |
605 | ||
606 | for (i=0; i<size; i++){ | |
f121b478 | 607 | |
608 | if (BitStream[i] == invert) | |
e0165dcf | 609 | fcAll(fcLow, &n, clk, &modCnt); |
f121b478 | 610 | else |
e0165dcf | 611 | fcAll(fcHigh, &n, clk, &modCnt); |
e0165dcf | 612 | } |
f121b478 | 613 | WDT_HIT(); |
614 | ||
615 | Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d", fcHigh, fcLow, clk, invert, n); | |
e0165dcf | 616 | |
508b37ba | 617 | if (ledcontrol) LED_A_ON(); |
e0165dcf | 618 | SimulateTagLowFrequency(n, 0, ledcontrol); |
508b37ba | 619 | if (ledcontrol) LED_A_OFF(); |
e09f21fa | 620 | } |
621 | ||
622 | // compose ask waveform for one bit(ASK) | |
e0165dcf | 623 | static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester) |
e09f21fa | 624 | { |
e0165dcf | 625 | uint8_t *dest = BigBuf_get_addr(); |
626 | uint8_t halfClk = clock/2; | |
627 | // c = current bit 1 or 0 | |
628 | if (manchester==1){ | |
629 | memset(dest+(*n), c, halfClk); | |
630 | memset(dest+(*n) + halfClk, c^1, halfClk); | |
631 | } else { | |
632 | memset(dest+(*n), c, clock); | |
633 | } | |
634 | *n += clock; | |
e09f21fa | 635 | } |
636 | ||
b41534d1 | 637 | static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase) |
638 | { | |
e0165dcf | 639 | uint8_t *dest = BigBuf_get_addr(); |
640 | uint8_t halfClk = clock/2; | |
641 | if (c){ | |
642 | memset(dest+(*n), c ^ 1 ^ *phase, halfClk); | |
643 | memset(dest+(*n) + halfClk, c ^ *phase, halfClk); | |
644 | } else { | |
645 | memset(dest+(*n), c ^ *phase, clock); | |
646 | *phase ^= 1; | |
647 | } | |
c728b2b4 | 648 | *n += clock; |
b41534d1 | 649 | } |
650 | ||
6c68b84a | 651 | static void stAskSimBit(int *n, uint8_t clock) { |
652 | uint8_t *dest = BigBuf_get_addr(); | |
653 | uint8_t halfClk = clock/2; | |
654 | //ST = .5 high .5 low 1.5 high .5 low 1 high | |
655 | memset(dest+(*n), 1, halfClk); | |
656 | memset(dest+(*n) + halfClk, 0, halfClk); | |
657 | memset(dest+(*n) + clock, 1, clock + halfClk); | |
658 | memset(dest+(*n) + clock*2 + halfClk, 0, halfClk); | |
659 | memset(dest+(*n) + clock*3, 1, clock); | |
660 | *n += clock*4; | |
661 | } | |
662 | ||
e09f21fa | 663 | // args clock, ask/man or askraw, invert, transmission separator |
664 | void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream) | |
665 | { | |
f121b478 | 666 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
667 | set_tracing(FALSE); | |
668 | ||
669 | int ledcontrol = 1, n = 0, i = 0; | |
e0165dcf | 670 | uint8_t clk = (arg1 >> 8) & 0xFF; |
2b3af97d | 671 | uint8_t encoding = arg1 & 0xFF; |
e0165dcf | 672 | uint8_t separator = arg2 & 1; |
673 | uint8_t invert = (arg2 >> 8) & 1; | |
674 | ||
f121b478 | 675 | if (encoding == 2){ //biphase |
676 | uint8_t phase = 0; | |
e0165dcf | 677 | for (i=0; i<size; i++){ |
678 | biphaseSimBit(BitStream[i]^invert, &n, clk, &phase); | |
679 | } | |
f121b478 | 680 | if (phase == 1) { //run a second set inverted to keep phase in check |
e0165dcf | 681 | for (i=0; i<size; i++){ |
682 | biphaseSimBit(BitStream[i]^invert, &n, clk, &phase); | |
683 | } | |
684 | } | |
685 | } else { // ask/manchester || ask/raw | |
686 | for (i=0; i<size; i++){ | |
687 | askSimBit(BitStream[i]^invert, &n, clk, encoding); | |
688 | } | |
689 | if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase) | |
690 | for (i=0; i<size; i++){ | |
691 | askSimBit(BitStream[i]^invert^1, &n, clk, encoding); | |
692 | } | |
693 | } | |
694 | } | |
6c68b84a | 695 | if (separator==1 && encoding == 1) |
696 | stAskSimBit(&n, clk); | |
697 | else if (separator==1) | |
698 | Dbprintf("sorry but separator option not yet available"); | |
e0165dcf | 699 | |
f121b478 | 700 | WDT_HIT(); |
701 | ||
e0165dcf | 702 | Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n); |
e0165dcf | 703 | |
a739812e | 704 | if (ledcontrol) LED_A_ON(); |
e0165dcf | 705 | SimulateTagLowFrequency(n, 0, ledcontrol); |
a739812e | 706 | if (ledcontrol) LED_A_OFF(); |
e09f21fa | 707 | } |
708 | ||
709 | //carrier can be 2,4 or 8 | |
710 | static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg) | |
711 | { | |
e0165dcf | 712 | uint8_t *dest = BigBuf_get_addr(); |
713 | uint8_t halfWave = waveLen/2; | |
714 | //uint8_t idx; | |
715 | int i = 0; | |
716 | if (phaseChg){ | |
717 | // write phase change | |
718 | memset(dest+(*n), *curPhase^1, halfWave); | |
719 | memset(dest+(*n) + halfWave, *curPhase, halfWave); | |
720 | *n += waveLen; | |
721 | *curPhase ^= 1; | |
722 | i += waveLen; | |
723 | } | |
724 | //write each normal clock wave for the clock duration | |
725 | for (; i < clk; i+=waveLen){ | |
726 | memset(dest+(*n), *curPhase, halfWave); | |
727 | memset(dest+(*n) + halfWave, *curPhase^1, halfWave); | |
728 | *n += waveLen; | |
729 | } | |
e09f21fa | 730 | } |
731 | ||
732 | // args clock, carrier, invert, | |
733 | void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream) | |
734 | { | |
f121b478 | 735 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
736 | set_tracing(FALSE); | |
737 | ||
738 | int ledcontrol = 1, n = 0, i = 0; | |
e0165dcf | 739 | uint8_t clk = arg1 >> 8; |
740 | uint8_t carrier = arg1 & 0xFF; | |
741 | uint8_t invert = arg2 & 0xFF; | |
742 | uint8_t curPhase = 0; | |
743 | for (i=0; i<size; i++){ | |
744 | if (BitStream[i] == curPhase){ | |
745 | pskSimBit(carrier, &n, clk, &curPhase, FALSE); | |
746 | } else { | |
747 | pskSimBit(carrier, &n, clk, &curPhase, TRUE); | |
748 | } | |
749 | } | |
f121b478 | 750 | |
751 | WDT_HIT(); | |
752 | ||
e0165dcf | 753 | Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n); |
e0165dcf | 754 | |
a739812e | 755 | if (ledcontrol) LED_A_ON(); |
e0165dcf | 756 | SimulateTagLowFrequency(n, 0, ledcontrol); |
a739812e | 757 | if (ledcontrol) LED_A_OFF(); |
e09f21fa | 758 | } |
759 | ||
760 | // loop to get raw HID waveform then FSK demodulate the TAG ID from it | |
761 | void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol) | |
762 | { | |
e0165dcf | 763 | uint8_t *dest = BigBuf_get_addr(); |
e0165dcf | 764 | size_t size = 0; |
765 | uint32_t hi2=0, hi=0, lo=0; | |
766 | int idx=0; | |
767 | // Configure to go in 125Khz listen mode | |
768 | LFSetupFPGAForADC(95, true); | |
e09f21fa | 769 | |
c0f15a05 | 770 | //clear read buffer |
771 | BigBuf_Clear_keep_EM(); | |
772 | ||
6427695b | 773 | while(!BUTTON_PRESS() && !usb_poll_validate_length()) { |
e09f21fa | 774 | |
e0165dcf | 775 | WDT_HIT(); |
776 | if (ledcontrol) LED_A_ON(); | |
e09f21fa | 777 | |
778 | DoAcquisition_default(-1,true); | |
779 | // FSK demodulator | |
b8f705e7 | 780 | size = 50*128*2; //big enough to catch 2 sequences of largest format |
e09f21fa | 781 | idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo); |
e0165dcf | 782 | |
b8f705e7 | 783 | if (idx>0 && lo>0 && (size==96 || size==192)){ |
784 | // go over previously decoded manchester data and decode into usable tag ID | |
785 | if (hi2 != 0){ //extra large HID tags 88/192 bits | |
e0165dcf | 786 | Dbprintf("TAG ID: %x%08x%08x (%d)", |
a739812e | 787 | (unsigned int) hi2, |
788 | (unsigned int) hi, | |
789 | (unsigned int) lo, | |
790 | (unsigned int) (lo>>1) & 0xFFFF | |
791 | ); | |
614da335 | 792 | } else { //standard HID tags 44/96 bits |
e0165dcf | 793 | uint8_t bitlen = 0; |
794 | uint32_t fc = 0; | |
795 | uint32_t cardnum = 0; | |
a739812e | 796 | |
e09f21fa | 797 | if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used |
e0165dcf | 798 | uint32_t lo2=0; |
799 | lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit | |
800 | uint8_t idx3 = 1; | |
e09f21fa | 801 | while(lo2 > 1){ //find last bit set to 1 (format len bit) |
802 | lo2=lo2 >> 1; | |
e0165dcf | 803 | idx3++; |
804 | } | |
e09f21fa | 805 | bitlen = idx3+19; |
e0165dcf | 806 | fc =0; |
807 | cardnum=0; | |
e09f21fa | 808 | if(bitlen == 26){ |
e0165dcf | 809 | cardnum = (lo>>1)&0xFFFF; |
810 | fc = (lo>>17)&0xFF; | |
811 | } | |
e09f21fa | 812 | if(bitlen == 37){ |
e0165dcf | 813 | cardnum = (lo>>1)&0x7FFFF; |
814 | fc = ((hi&0xF)<<12)|(lo>>20); | |
815 | } | |
e09f21fa | 816 | if(bitlen == 34){ |
e0165dcf | 817 | cardnum = (lo>>1)&0xFFFF; |
818 | fc= ((hi&1)<<15)|(lo>>17); | |
819 | } | |
e09f21fa | 820 | if(bitlen == 35){ |
e0165dcf | 821 | cardnum = (lo>>1)&0xFFFFF; |
822 | fc = ((hi&1)<<11)|(lo>>21); | |
823 | } | |
824 | } | |
825 | else { //if bit 38 is not set then 37 bit format is used | |
826 | bitlen= 37; | |
827 | fc =0; | |
828 | cardnum=0; | |
829 | if(bitlen==37){ | |
830 | cardnum = (lo>>1)&0x7FFFF; | |
831 | fc = ((hi&0xF)<<12)|(lo>>20); | |
832 | } | |
833 | } | |
e0165dcf | 834 | Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d", |
a739812e | 835 | (unsigned int) hi, |
836 | (unsigned int) lo, | |
837 | (unsigned int) (lo>>1) & 0xFFFF, | |
838 | (unsigned int) bitlen, | |
839 | (unsigned int) fc, | |
840 | (unsigned int) cardnum); | |
e0165dcf | 841 | } |
842 | if (findone){ | |
843 | if (ledcontrol) LED_A_OFF(); | |
844 | *high = hi; | |
845 | *low = lo; | |
846 | return; | |
847 | } | |
848 | // reset | |
e0165dcf | 849 | } |
b8f705e7 | 850 | hi2 = hi = lo = idx = 0; |
e0165dcf | 851 | WDT_HIT(); |
852 | } | |
853 | DbpString("Stopped"); | |
854 | if (ledcontrol) LED_A_OFF(); | |
e09f21fa | 855 | } |
856 | ||
db25599d | 857 | // loop to get raw HID waveform then FSK demodulate the TAG ID from it |
858 | void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol) | |
859 | { | |
860 | uint8_t *dest = BigBuf_get_addr(); | |
db25599d | 861 | size_t size; |
862 | int idx=0; | |
c0f15a05 | 863 | //clear read buffer |
864 | BigBuf_Clear_keep_EM(); | |
db25599d | 865 | // Configure to go in 125Khz listen mode |
866 | LFSetupFPGAForADC(95, true); | |
867 | ||
6427695b | 868 | while(!BUTTON_PRESS() && !usb_poll_validate_length()) { |
db25599d | 869 | |
870 | WDT_HIT(); | |
871 | if (ledcontrol) LED_A_ON(); | |
872 | ||
873 | DoAcquisition_default(-1,true); | |
874 | // FSK demodulator | |
db25599d | 875 | size = 50*128*2; //big enough to catch 2 sequences of largest format |
876 | idx = AWIDdemodFSK(dest, &size); | |
877 | ||
a126332a | 878 | if (idx<=0 || size!=96) continue; |
db25599d | 879 | // Index map |
880 | // 0 10 20 30 40 50 60 | |
881 | // | | | | | | | | |
882 | // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96 | |
883 | // ----------------------------------------------------------------------------- | |
884 | // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1 | |
885 | // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96 | |
886 | // |---26 bit---| |-----117----||-------------142-------------| | |
887 | // b = format bit len, o = odd parity of last 3 bits | |
888 | // f = facility code, c = card number | |
889 | // w = wiegand parity | |
890 | // (26 bit format shown) | |
891 | ||
892 | //get raw ID before removing parities | |
893 | uint32_t rawLo = bytebits_to_byte(dest+idx+64,32); | |
894 | uint32_t rawHi = bytebits_to_byte(dest+idx+32,32); | |
895 | uint32_t rawHi2 = bytebits_to_byte(dest+idx,32); | |
896 | ||
897 | size = removeParity(dest, idx+8, 4, 1, 88); | |
a126332a | 898 | if (size != 66) continue; |
db25599d | 899 | |
900 | // Index map | |
901 | // 0 10 20 30 40 50 60 | |
902 | // | | | | | | | | |
903 | // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456 | |
904 | // ----------------------------------------------------------------------------- | |
905 | // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000 | |
906 | // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx | |
907 | // |26 bit| |-117--| |-----142------| | |
c5e8b916 | 908 | // |
909 | // 00110010 0 0000011111010000000000000001000100101000100001111 0 00000000 | |
910 | // bbbbbbbb w ffffffffffffffffccccccccccccccccccccccccccccccccc w xxxxxxxx | |
911 | // |50 bit| |----4000------||-----------2248975-------------| | |
912 | // | |
db25599d | 913 | // b = format bit len, o = odd parity of last 3 bits |
914 | // f = facility code, c = card number | |
915 | // w = wiegand parity | |
db25599d | 916 | |
917 | uint32_t fc = 0; | |
918 | uint32_t cardnum = 0; | |
919 | uint32_t code1 = 0; | |
920 | uint32_t code2 = 0; | |
921 | uint8_t fmtLen = bytebits_to_byte(dest,8); | |
c5e8b916 | 922 | switch(fmtLen) { |
923 | case 26: | |
924 | fc = bytebits_to_byte(dest + 9, 8); | |
925 | cardnum = bytebits_to_byte(dest + 17, 16); | |
926 | code1 = bytebits_to_byte(dest + 8,fmtLen); | |
6a4271d1 | 927 | Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo); |
c5e8b916 | 928 | break; |
929 | case 50: | |
930 | fc = bytebits_to_byte(dest + 9, 16); | |
931 | cardnum = bytebits_to_byte(dest + 25, 32); | |
932 | code1 = bytebits_to_byte(dest + 8, (fmtLen-32) ); | |
933 | code2 = bytebits_to_byte(dest + 8 + (fmtLen-32), 32); | |
6a4271d1 | 934 | Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, code2, rawHi2, rawHi, rawLo); |
c5e8b916 | 935 | break; |
936 | default: | |
937 | if (fmtLen > 32 ) { | |
938 | cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16); | |
939 | code1 = bytebits_to_byte(dest+8,fmtLen-32); | |
940 | code2 = bytebits_to_byte(dest+8+(fmtLen-32),32); | |
6a4271d1 | 941 | Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo); |
c5e8b916 | 942 | } else { |
943 | cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16); | |
944 | code1 = bytebits_to_byte(dest+8,fmtLen); | |
6a4271d1 | 945 | Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo); |
c5e8b916 | 946 | } |
947 | break; | |
db25599d | 948 | } |
949 | if (findone){ | |
950 | if (ledcontrol) LED_A_OFF(); | |
951 | return; | |
952 | } | |
db25599d | 953 | idx = 0; |
954 | WDT_HIT(); | |
955 | } | |
956 | DbpString("Stopped"); | |
957 | if (ledcontrol) LED_A_OFF(); | |
958 | } | |
959 | ||
e09f21fa | 960 | void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol) |
961 | { | |
e0165dcf | 962 | uint8_t *dest = BigBuf_get_addr(); |
963 | ||
964 | size_t size=0, idx=0; | |
965 | int clk=0, invert=0, errCnt=0, maxErr=20; | |
966 | uint32_t hi=0; | |
967 | uint64_t lo=0; | |
c0f15a05 | 968 | //clear read buffer |
969 | BigBuf_Clear_keep_EM(); | |
e0165dcf | 970 | // Configure to go in 125Khz listen mode |
971 | LFSetupFPGAForADC(95, true); | |
972 | ||
6427695b | 973 | while(!BUTTON_PRESS() && !usb_poll_validate_length()) { |
e0165dcf | 974 | |
975 | WDT_HIT(); | |
976 | if (ledcontrol) LED_A_ON(); | |
977 | ||
978 | DoAcquisition_default(-1,true); | |
979 | size = BigBuf_max_traceLen(); | |
e0165dcf | 980 | //askdemod and manchester decode |
b8f705e7 | 981 | if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format |
fef74fdc | 982 | errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1); |
e0165dcf | 983 | WDT_HIT(); |
984 | ||
b8f705e7 | 985 | if (errCnt<0) continue; |
986 | ||
e0165dcf | 987 | errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo); |
e0165dcf | 988 | if (errCnt){ |
989 | if (size>64){ | |
990 | Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)", | |
991 | hi, | |
992 | (uint32_t)(lo>>32), | |
993 | (uint32_t)lo, | |
994 | (uint32_t)(lo&0xFFFF), | |
995 | (uint32_t)((lo>>16LL) & 0xFF), | |
996 | (uint32_t)(lo & 0xFFFFFF)); | |
997 | } else { | |
998 | Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)", | |
999 | (uint32_t)(lo>>32), | |
1000 | (uint32_t)lo, | |
1001 | (uint32_t)(lo&0xFFFF), | |
1002 | (uint32_t)((lo>>16LL) & 0xFF), | |
1003 | (uint32_t)(lo & 0xFFFFFF)); | |
1004 | } | |
b8f705e7 | 1005 | |
e0165dcf | 1006 | if (findone){ |
1007 | if (ledcontrol) LED_A_OFF(); | |
1008 | *high=lo>>32; | |
1009 | *low=lo & 0xFFFFFFFF; | |
1010 | return; | |
1011 | } | |
e0165dcf | 1012 | } |
1013 | WDT_HIT(); | |
b8f705e7 | 1014 | hi = lo = size = idx = 0; |
1015 | clk = invert = errCnt = 0; | |
e0165dcf | 1016 | } |
1017 | DbpString("Stopped"); | |
1018 | if (ledcontrol) LED_A_OFF(); | |
e09f21fa | 1019 | } |
1020 | ||
1021 | void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol) | |
1022 | { | |
e0165dcf | 1023 | uint8_t *dest = BigBuf_get_addr(); |
1024 | int idx=0; | |
1025 | uint32_t code=0, code2=0; | |
1026 | uint8_t version=0; | |
1027 | uint8_t facilitycode=0; | |
1028 | uint16_t number=0; | |
b8f705e7 | 1029 | uint8_t crc = 0; |
1030 | uint16_t calccrc = 0; | |
c0f15a05 | 1031 | |
1032 | //clear read buffer | |
1033 | BigBuf_Clear_keep_EM(); | |
1034 | ||
118bf0c2 | 1035 | // Configure to go in 125Khz listen mode |
e0165dcf | 1036 | LFSetupFPGAForADC(95, true); |
1037 | ||
6427695b | 1038 | while(!BUTTON_PRESS() && !usb_poll_validate_length()) { |
e0165dcf | 1039 | WDT_HIT(); |
1040 | if (ledcontrol) LED_A_ON(); | |
e09f21fa | 1041 | DoAcquisition_default(-1,true); |
1042 | //fskdemod and get start index | |
e0165dcf | 1043 | WDT_HIT(); |
1044 | idx = IOdemodFSK(dest, BigBuf_max_traceLen()); | |
b8f705e7 | 1045 | if (idx<0) continue; |
e0165dcf | 1046 | //valid tag found |
1047 | ||
1048 | //Index map | |
1049 | //0 10 20 30 40 50 60 | |
1050 | //| | | | | | | | |
1051 | //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23 | |
1052 | //----------------------------------------------------------------------------- | |
b8f705e7 | 1053 | //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11 |
e0165dcf | 1054 | // |
b8f705e7 | 1055 | //Checksum: |
1056 | //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11 | |
1057 | //preamble F0 E0 01 03 B6 75 | |
1058 | // How to calc checksum, | |
1059 | // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6 | |
1060 | // F0 + E0 + 01 + 03 + B6 = 28A | |
1061 | // 28A & FF = 8A | |
1062 | // FF - 8A = 75 | |
1063 | // Checksum: 0x75 | |
e0165dcf | 1064 | //XSF(version)facility:codeone+codetwo |
1065 | //Handle the data | |
1066 | if(findone){ //only print binary if we are doing one | |
1067 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]); | |
1068 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]); | |
1069 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]); | |
1070 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]); | |
1071 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]); | |
1072 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]); | |
1073 | Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]); | |
1074 | } | |
1075 | code = bytebits_to_byte(dest+idx,32); | |
1076 | code2 = bytebits_to_byte(dest+idx+32,32); | |
1077 | version = bytebits_to_byte(dest+idx+27,8); //14,4 | |
a739812e | 1078 | facilitycode = bytebits_to_byte(dest+idx+18,8); |
e0165dcf | 1079 | number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9 |
1080 | ||
b8f705e7 | 1081 | crc = bytebits_to_byte(dest+idx+54,8); |
1082 | for (uint8_t i=1; i<6; ++i) | |
1083 | calccrc += bytebits_to_byte(dest+idx+9*i,8); | |
1084 | calccrc &= 0xff; | |
1085 | calccrc = 0xff - calccrc; | |
1086 | ||
1087 | char *crcStr = (crc == calccrc) ? "ok":"!crc"; | |
1088 | ||
1089 | Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr); | |
e0165dcf | 1090 | // if we're only looking for one tag |
1091 | if (findone){ | |
1092 | if (ledcontrol) LED_A_OFF(); | |
e0165dcf | 1093 | *high=code; |
1094 | *low=code2; | |
1095 | return; | |
1096 | } | |
1097 | code=code2=0; | |
1098 | version=facilitycode=0; | |
1099 | number=0; | |
1100 | idx=0; | |
b8f705e7 | 1101 | |
e0165dcf | 1102 | WDT_HIT(); |
1103 | } | |
1104 | DbpString("Stopped"); | |
1105 | if (ledcontrol) LED_A_OFF(); | |
e09f21fa | 1106 | } |
1107 | ||
1108 | /*------------------------------ | |
94422fa2 | 1109 | * T5555/T5557/T5567/T5577 routines |
e09f21fa | 1110 | *------------------------------ |
1d0ccbe0 | 1111 | * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h |
1112 | * | |
1113 | * Relevant communication times in microsecond | |
e09f21fa | 1114 | * To compensate antenna falling times shorten the write times |
1115 | * and enlarge the gap ones. | |
6a09bea4 | 1116 | * Q5 tags seems to have issues when these values changes. |
e09f21fa | 1117 | */ |
0de8e387 | 1118 | |
b4a6775b | 1119 | #define START_GAP 50*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc) |
4a3f1a37 | 1120 | #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc) |
8ce3e4b4 | 1121 | #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc) |
4a3f1a37 | 1122 | #define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550 |
6426f6ba | 1123 | #define READ_GAP 15*8 |
b8f705e7 | 1124 | |
1125 | // VALUES TAKEN FROM EM4x function: SendForward | |
1126 | // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle) | |
1127 | // WRITE_GAP = 128; (16*8) | |
1128 | // WRITE_1 = 256 32*8; (32*8) | |
1129 | ||
1130 | // These timings work for 4469/4269/4305 (with the 55*8 above) | |
1131 | // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8); | |
1132 | ||
1133 | // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK) | |
1134 | // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz | |
1135 | // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier) | |
1136 | // T0 = TIMER_CLOCK1 / 125000 = 192 | |
e16054a4 | 1137 | // 1 Cycle = 8 microseconds(us) == 1 field clock |
e09f21fa | 1138 | |
a739812e | 1139 | void TurnReadLFOn(int delay) { |
1140 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); | |
1141 | // Give it a bit of time for the resonant antenna to settle. | |
1d0ccbe0 | 1142 | |
1143 | // measure antenna strength. | |
1144 | //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10); | |
1145 | // where to save it | |
1146 | ||
b4a6775b | 1147 | SpinDelayUs(delay); // ICEMAN: problem with (us) clock is 21.3us increments |
a739812e | 1148 | } |
1149 | ||
e09f21fa | 1150 | // Write one bit to card |
e16054a4 | 1151 | void T55xxWriteBit(int bit) { |
b8f705e7 | 1152 | if (!bit) |
1d0ccbe0 | 1153 | TurnReadLFOn(WRITE_0); |
e0165dcf | 1154 | else |
1d0ccbe0 | 1155 | TurnReadLFOn(WRITE_1); |
e0165dcf | 1156 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
b4a6775b | 1157 | SpinDelayUs(WRITE_GAP); // ICEMAN: problem with (us) clock is 21.3us increments |
e09f21fa | 1158 | } |
1159 | ||
94422fa2 | 1160 | // Send T5577 reset command then read stream (see if we can identify the start of the stream) |
1161 | void T55xxResetRead(void) { | |
1162 | LED_A_ON(); | |
1163 | //clear buffer now so it does not interfere with timing later | |
c0f15a05 | 1164 | BigBuf_Clear_keep_EM(); |
94422fa2 | 1165 | |
1166 | // Set up FPGA, 125kHz | |
1167 | LFSetupFPGAForADC(95, true); | |
1168 | ||
1169 | // Trigger T55x7 in mode. | |
1170 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
b4a6775b | 1171 | SpinDelayUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments |
94422fa2 | 1172 | |
1173 | // reset tag - op code 00 | |
1174 | T55xxWriteBit(0); | |
1175 | T55xxWriteBit(0); | |
1176 | ||
1177 | // Turn field on to read the response | |
1178 | TurnReadLFOn(READ_GAP); | |
1179 | ||
1180 | // Acquisition | |
1181 | doT55x7Acquisition(BigBuf_max_traceLen()); | |
1182 | ||
1183 | // Turn the field off | |
1184 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
1185 | cmd_send(CMD_ACK,0,0,0,0,0); | |
1186 | LED_A_OFF(); | |
1187 | } | |
1188 | ||
e09f21fa | 1189 | // Write one card block in page 0, no lock |
70459879 | 1190 | void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) { |
e16054a4 | 1191 | LED_A_ON(); |
1d0ccbe0 | 1192 | bool PwdMode = arg & 0x1; |
1193 | uint8_t Page = (arg & 0x2)>>1; | |
e0165dcf | 1194 | uint32_t i = 0; |
1195 | ||
1196 | // Set up FPGA, 125kHz | |
ac2df346 | 1197 | LFSetupFPGAForADC(95, true); |
0de8e387 | 1198 | |
e16054a4 | 1199 | // Trigger T55x7 in mode. |
e0165dcf | 1200 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
b4a6775b | 1201 | SpinDelayUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments |
e0165dcf | 1202 | |
e16054a4 | 1203 | // Opcode 10 |
e0165dcf | 1204 | T55xxWriteBit(1); |
1d0ccbe0 | 1205 | T55xxWriteBit(Page); //Page 0 |
9276e859 | 1206 | if (PwdMode){ |
a739812e | 1207 | // Send Pwd |
e0165dcf | 1208 | for (i = 0x80000000; i != 0; i >>= 1) |
1209 | T55xxWriteBit(Pwd & i); | |
1210 | } | |
a739812e | 1211 | // Send Lock bit |
e0165dcf | 1212 | T55xxWriteBit(0); |
1213 | ||
a739812e | 1214 | // Send Data |
e0165dcf | 1215 | for (i = 0x80000000; i != 0; i >>= 1) |
1216 | T55xxWriteBit(Data & i); | |
1217 | ||
a739812e | 1218 | // Send Block number |
e0165dcf | 1219 | for (i = 0x04; i != 0; i >>= 1) |
1220 | T55xxWriteBit(Block & i); | |
1221 | ||
e16054a4 | 1222 | // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550, |
e0165dcf | 1223 | // so wait a little more) |
e16054a4 | 1224 | TurnReadLFOn(20 * 1000); |
1d0ccbe0 | 1225 | //could attempt to do a read to confirm write took |
1226 | // as the tag should repeat back the new block | |
1227 | // until it is reset, but to confirm it we would | |
1228 | // need to know the current block 0 config mode | |
e16054a4 | 1229 | |
a739812e | 1230 | // turn field off |
e0165dcf | 1231 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
9276e859 | 1232 | LED_A_OFF(); |
e09f21fa | 1233 | } |
1234 | ||
94422fa2 | 1235 | // Write one card block in page 0, no lock |
70459879 | 1236 | void T55xxWriteBlock(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) { |
94422fa2 | 1237 | T55xxWriteBlockExt(Data, Block, Pwd, arg); |
1238 | cmd_send(CMD_ACK,0,0,0,0,0); | |
1239 | } | |
1240 | ||
6426f6ba | 1241 | // Read one card block in page [page] |
9276e859 | 1242 | void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) { |
e16054a4 | 1243 | LED_A_ON(); |
1d0ccbe0 | 1244 | bool PwdMode = arg0 & 0x1; |
1245 | uint8_t Page = (arg0 & 0x2) >> 1; | |
e0165dcf | 1246 | uint32_t i = 0; |
1d0ccbe0 | 1247 | bool RegReadMode = (Block == 0xFF); |
ac2df346 | 1248 | |
a739812e | 1249 | //clear buffer now so it does not interfere with timing later |
b4a6775b | 1250 | BigBuf_Clear_keep_EM(); |
a739812e | 1251 | |
ac2df346 | 1252 | //make sure block is at max 7 |
1253 | Block &= 0x7; | |
e0165dcf | 1254 | |
1d0ccbe0 | 1255 | // Set up FPGA, 125kHz to power up the tag |
ac2df346 | 1256 | LFSetupFPGAForADC(95, true); |
b4a6775b | 1257 | SpinDelay(3); |
0de8e387 | 1258 | |
1d0ccbe0 | 1259 | // Trigger T55x7 Direct Access Mode with start gap |
e0165dcf | 1260 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
b4a6775b | 1261 | SpinDelayUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments |
ac2df346 | 1262 | |
1d0ccbe0 | 1263 | // Opcode 1[page] |
e0165dcf | 1264 | T55xxWriteBit(1); |
1c8fbeb9 | 1265 | T55xxWriteBit(Page); //Page 0 |
ac2df346 | 1266 | |
9276e859 | 1267 | if (PwdMode){ |
a739812e | 1268 | // Send Pwd |
e0165dcf | 1269 | for (i = 0x80000000; i != 0; i >>= 1) |
1270 | T55xxWriteBit(Pwd & i); | |
1271 | } | |
a739812e | 1272 | // Send a zero bit separation |
e0165dcf | 1273 | T55xxWriteBit(0); |
ac2df346 | 1274 | |
1d0ccbe0 | 1275 | // Send Block number (if direct access mode) |
1276 | if (!RegReadMode) | |
b4a6775b | 1277 | for (i = 0x04; i != 0; i >>= 1) |
1278 | T55xxWriteBit(Block & i); | |
e0165dcf | 1279 | |
ac2df346 | 1280 | // Turn field on to read the response |
a739812e | 1281 | TurnReadLFOn(READ_GAP); |
ac2df346 | 1282 | |
1283 | // Acquisition | |
94422fa2 | 1284 | doT55x7Acquisition(12000); |
ac2df346 | 1285 | |
1d0ccbe0 | 1286 | // Turn the field off |
1287 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
e0165dcf | 1288 | cmd_send(CMD_ACK,0,0,0,0,0); |
e16054a4 | 1289 | LED_A_OFF(); |
9276e859 | 1290 | } |
1291 | ||
1292 | void T55xxWakeUp(uint32_t Pwd){ | |
1293 | LED_B_ON(); | |
1294 | uint32_t i = 0; | |
1295 | ||
1296 | // Set up FPGA, 125kHz | |
1297 | LFSetupFPGAForADC(95, true); | |
1298 | ||
1299 | // Trigger T55x7 Direct Access Mode | |
1300 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
b4a6775b | 1301 | SpinDelayUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments |
9276e859 | 1302 | |
1303 | // Opcode 10 | |
1304 | T55xxWriteBit(1); | |
1305 | T55xxWriteBit(0); //Page 0 | |
1306 | ||
1307 | // Send Pwd | |
1308 | for (i = 0x80000000; i != 0; i >>= 1) | |
1309 | T55xxWriteBit(Pwd & i); | |
1310 | ||
1d0ccbe0 | 1311 | // Turn and leave field on to let the begin repeating transmission |
1c8fbeb9 | 1312 | TurnReadLFOn(20*1000); |
e09f21fa | 1313 | } |
1314 | ||
1315 | /*-------------- Cloning routines -----------*/ | |
1d0ccbe0 | 1316 | void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) { |
1317 | // write last block first and config block last (if included) | |
70459879 | 1318 | for (uint8_t i = numblocks+startblock; i > startblock; i--) |
8ce3e4b4 | 1319 | T55xxWriteBlockExt(blockdata[i-1], i-1, 0, 0); |
1d0ccbe0 | 1320 | } |
1321 | ||
e09f21fa | 1322 | // Copy HID id to card and setup block 0 config |
1d0ccbe0 | 1323 | void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) { |
1324 | uint32_t data[] = {0,0,0,0,0,0,0}; | |
1d0ccbe0 | 1325 | uint8_t last_block = 0; |
e0165dcf | 1326 | |
1327 | if (longFMT){ | |
1328 | // Ensure no more than 84 bits supplied | |
614da335 | 1329 | if (hi2 > 0xFFFFF) { |
e0165dcf | 1330 | DbpString("Tags can only have 84 bits."); |
1331 | return; | |
1332 | } | |
1333 | // Build the 6 data blocks for supplied 84bit ID | |
1334 | last_block = 6; | |
1d0ccbe0 | 1335 | // load preamble (1D) & long format identifier (9E manchester encoded) |
94422fa2 | 1336 | data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF); |
1d0ccbe0 | 1337 | // load raw id from hi2, hi, lo to data blocks (manchester encoded) |
1338 | data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF); | |
1339 | data[3] = manchesterEncode2Bytes(hi >> 16); | |
1340 | data[4] = manchesterEncode2Bytes(hi & 0xFFFF); | |
1341 | data[5] = manchesterEncode2Bytes(lo >> 16); | |
1342 | data[6] = manchesterEncode2Bytes(lo & 0xFFFF); | |
1343 | } else { | |
e0165dcf | 1344 | // Ensure no more than 44 bits supplied |
614da335 | 1345 | if (hi > 0xFFF) { |
e0165dcf | 1346 | DbpString("Tags can only have 44 bits."); |
1347 | return; | |
1348 | } | |
e0165dcf | 1349 | // Build the 3 data blocks for supplied 44bit ID |
1350 | last_block = 3; | |
1d0ccbe0 | 1351 | // load preamble |
94422fa2 | 1352 | data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF); |
1d0ccbe0 | 1353 | data[2] = manchesterEncode2Bytes(lo >> 16); |
1354 | data[3] = manchesterEncode2Bytes(lo & 0xFFFF); | |
e0165dcf | 1355 | } |
1d0ccbe0 | 1356 | // load chip config block |
1357 | data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT; | |
e0165dcf | 1358 | |
edaf10af | 1359 | //TODO add selection of chip for Q5 or T55x7 |
1360 | // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT; | |
1361 | ||
e0165dcf | 1362 | LED_D_ON(); |
1363 | // Program the data blocks for supplied ID | |
1364 | // and the block 0 for HID format | |
1d0ccbe0 | 1365 | WriteT55xx(data, 0, last_block+1); |
e0165dcf | 1366 | |
1367 | LED_D_OFF(); | |
1368 | ||
1369 | DbpString("DONE!"); | |
e09f21fa | 1370 | } |
1371 | ||
94422fa2 | 1372 | void CopyIOtoT55x7(uint32_t hi, uint32_t lo) { |
1d0ccbe0 | 1373 | uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo}; |
edaf10af | 1374 | //TODO add selection of chip for Q5 or T55x7 |
118bf0c2 | 1375 | //t5555 (Q5) BITRATE = (RF-2)/2 (iceman) |
1376 | // data[0] = (64 << T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT; | |
e09f21fa | 1377 | |
e0165dcf | 1378 | LED_D_ON(); |
1379 | // Program the data blocks for supplied ID | |
1d0ccbe0 | 1380 | // and the block 0 config |
1381 | WriteT55xx(data, 0, 3); | |
e0165dcf | 1382 | LED_D_OFF(); |
e0165dcf | 1383 | DbpString("DONE!"); |
e09f21fa | 1384 | } |
1385 | ||
1d0ccbe0 | 1386 | // Clone Indala 64-bit tag by UID to T55x7 |
1387 | void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) { | |
1388 | //Program the 2 data blocks for supplied 64bit UID | |
1389 | // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2) | |
1390 | uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo}; | |
edaf10af | 1391 | //TODO add selection of chip for Q5 or T55x7 |
1392 | // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT; | |
1393 | ||
1d0ccbe0 | 1394 | WriteT55xx(data, 0, 3); |
1395 | //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data) | |
1396 | // T5567WriteBlock(0x603E1042,0); | |
1397 | DbpString("DONE!"); | |
1398 | } | |
1399 | // Clone Indala 224-bit tag by UID to T55x7 | |
94422fa2 | 1400 | void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) { |
1d0ccbe0 | 1401 | //Program the 7 data blocks for supplied 224bit UID |
1402 | uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7}; | |
1403 | // and the block 0 for Indala224 format | |
1404 | //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7) | |
1405 | data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT); | |
edaf10af | 1406 | //TODO add selection of chip for Q5 or T55x7 |
1407 | // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT; | |
1d0ccbe0 | 1408 | WriteT55xx(data, 0, 8); |
1409 | //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data) | |
1410 | // T5567WriteBlock(0x603E10E2,0); | |
1411 | DbpString("DONE!"); | |
1412 | } | |
a126332a | 1413 | // clone viking tag to T55xx |
1414 | void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) { | |
1415 | uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2}; | |
118bf0c2 | 1416 | //t5555 (Q5) BITRATE = (RF-2)/2 (iceman) |
a126332a | 1417 | if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT; |
1418 | // Program the data blocks for supplied ID and the block 0 config | |
1419 | WriteT55xx(data, 0, 3); | |
1420 | LED_D_OFF(); | |
1421 | cmd_send(CMD_ACK,0,0,0,0,0); | |
1422 | } | |
1d0ccbe0 | 1423 | |
e09f21fa | 1424 | // Define 9bit header for EM410x tags |
1425 | #define EM410X_HEADER 0x1FF | |
1426 | #define EM410X_ID_LENGTH 40 | |
1427 | ||
94422fa2 | 1428 | void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) { |
e0165dcf | 1429 | int i, id_bit; |
1430 | uint64_t id = EM410X_HEADER; | |
1431 | uint64_t rev_id = 0; // reversed ID | |
1432 | int c_parity[4]; // column parity | |
1433 | int r_parity = 0; // row parity | |
1434 | uint32_t clock = 0; | |
1435 | ||
1436 | // Reverse ID bits given as parameter (for simpler operations) | |
1437 | for (i = 0; i < EM410X_ID_LENGTH; ++i) { | |
1438 | if (i < 32) { | |
1439 | rev_id = (rev_id << 1) | (id_lo & 1); | |
1440 | id_lo >>= 1; | |
1441 | } else { | |
1442 | rev_id = (rev_id << 1) | (id_hi & 1); | |
1443 | id_hi >>= 1; | |
1444 | } | |
1445 | } | |
1446 | ||
1447 | for (i = 0; i < EM410X_ID_LENGTH; ++i) { | |
1448 | id_bit = rev_id & 1; | |
1449 | ||
1450 | if (i % 4 == 0) { | |
1451 | // Don't write row parity bit at start of parsing | |
1452 | if (i) | |
1453 | id = (id << 1) | r_parity; | |
1454 | // Start counting parity for new row | |
1455 | r_parity = id_bit; | |
1456 | } else { | |
1457 | // Count row parity | |
1458 | r_parity ^= id_bit; | |
1459 | } | |
1460 | ||
1461 | // First elements in column? | |
1462 | if (i < 4) | |
1463 | // Fill out first elements | |
1464 | c_parity[i] = id_bit; | |
1465 | else | |
1466 | // Count column parity | |
1467 | c_parity[i % 4] ^= id_bit; | |
1468 | ||
1469 | // Insert ID bit | |
1470 | id = (id << 1) | id_bit; | |
1471 | rev_id >>= 1; | |
1472 | } | |
1473 | ||
1474 | // Insert parity bit of last row | |
1475 | id = (id << 1) | r_parity; | |
1476 | ||
1477 | // Fill out column parity at the end of tag | |
1478 | for (i = 0; i < 4; ++i) | |
1479 | id = (id << 1) | c_parity[i]; | |
1480 | ||
1481 | // Add stop bit | |
1482 | id <<= 1; | |
1483 | ||
1484 | Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555"); | |
1485 | LED_D_ON(); | |
1486 | ||
1487 | // Write EM410x ID | |
6c68b84a | 1488 | uint32_t data[] = {0, (uint32_t)(id>>32), (uint32_t)(id & 0xFFFFFFFF)}; |
edaf10af | 1489 | |
8ce3e4b4 | 1490 | clock = (card & 0xFF00) >> 8; |
1491 | clock = (clock == 0) ? 64 : clock; | |
1492 | Dbprintf("Clock rate: %d", clock); | |
edaf10af | 1493 | if (card & 0xFF) { //t55x7 |
1d0ccbe0 | 1494 | clock = GetT55xxClockBit(clock); |
1495 | if (clock == 0) { | |
e0165dcf | 1496 | Dbprintf("Invalid clock rate: %d", clock); |
1497 | return; | |
1498 | } | |
1d0ccbe0 | 1499 | data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT); |
edaf10af | 1500 | } else { //t5555 (Q5) |
1501 | clock = (clock-2)>>1; //n = (RF-2)/2 | |
1502 | data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT); | |
e0165dcf | 1503 | } |
118bf0c2 | 1504 | |
1d0ccbe0 | 1505 | WriteT55xx(data, 0, 3); |
e0165dcf | 1506 | |
1507 | LED_D_OFF(); | |
8ce3e4b4 | 1508 | Dbprintf("Tag %s written with 0x%08x%08x\n", |
1509 | card ? "T55x7":"T5555", | |
1510 | (uint32_t)(id >> 32), | |
1511 | (uint32_t)id); | |
e09f21fa | 1512 | } |
1513 | ||
e09f21fa | 1514 | //----------------------------------- |
1515 | // EM4469 / EM4305 routines | |
1516 | //----------------------------------- | |
1517 | #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored | |
1518 | #define FWD_CMD_WRITE 0xA | |
1519 | #define FWD_CMD_READ 0x9 | |
1520 | #define FWD_CMD_DISABLE 0x5 | |
1521 | ||
e09f21fa | 1522 | uint8_t forwardLink_data[64]; //array of forwarded bits |
1523 | uint8_t * forward_ptr; //ptr for forward message preparation | |
1524 | uint8_t fwd_bit_sz; //forwardlink bit counter | |
1525 | uint8_t * fwd_write_ptr; //forwardlink bit pointer | |
1526 | ||
1527 | //==================================================================== | |
1528 | // prepares command bits | |
1529 | // see EM4469 spec | |
1530 | //==================================================================== | |
6426f6ba | 1531 | //-------------------------------------------------------------------- |
1532 | // VALUES TAKEN FROM EM4x function: SendForward | |
1533 | // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle) | |
1534 | // WRITE_GAP = 128; (16*8) | |
1535 | // WRITE_1 = 256 32*8; (32*8) | |
1536 | ||
1537 | // These timings work for 4469/4269/4305 (with the 55*8 above) | |
1538 | // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8); | |
1539 | ||
e09f21fa | 1540 | uint8_t Prepare_Cmd( uint8_t cmd ) { |
e09f21fa | 1541 | |
e0165dcf | 1542 | *forward_ptr++ = 0; //start bit |
1543 | *forward_ptr++ = 0; //second pause for 4050 code | |
e09f21fa | 1544 | |
e0165dcf | 1545 | *forward_ptr++ = cmd; |
1546 | cmd >>= 1; | |
1547 | *forward_ptr++ = cmd; | |
1548 | cmd >>= 1; | |
1549 | *forward_ptr++ = cmd; | |
1550 | cmd >>= 1; | |
1551 | *forward_ptr++ = cmd; | |
e09f21fa | 1552 | |
e0165dcf | 1553 | return 6; //return number of emited bits |
e09f21fa | 1554 | } |
1555 | ||
1556 | //==================================================================== | |
1557 | // prepares address bits | |
1558 | // see EM4469 spec | |
1559 | //==================================================================== | |
e09f21fa | 1560 | uint8_t Prepare_Addr( uint8_t addr ) { |
e09f21fa | 1561 | |
e0165dcf | 1562 | register uint8_t line_parity; |
e09f21fa | 1563 | |
e0165dcf | 1564 | uint8_t i; |
1565 | line_parity = 0; | |
1566 | for(i=0;i<6;i++) { | |
1567 | *forward_ptr++ = addr; | |
1568 | line_parity ^= addr; | |
1569 | addr >>= 1; | |
1570 | } | |
e09f21fa | 1571 | |
e0165dcf | 1572 | *forward_ptr++ = (line_parity & 1); |
e09f21fa | 1573 | |
e0165dcf | 1574 | return 7; //return number of emited bits |
e09f21fa | 1575 | } |
1576 | ||
1577 | //==================================================================== | |
1578 | // prepares data bits intreleaved with parity bits | |
1579 | // see EM4469 spec | |
1580 | //==================================================================== | |
e09f21fa | 1581 | uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) { |
e0165dcf | 1582 | |
1583 | register uint8_t line_parity; | |
1584 | register uint8_t column_parity; | |
1585 | register uint8_t i, j; | |
1586 | register uint16_t data; | |
1587 | ||
1588 | data = data_low; | |
1589 | column_parity = 0; | |
1590 | ||
1591 | for(i=0; i<4; i++) { | |
1592 | line_parity = 0; | |
1593 | for(j=0; j<8; j++) { | |
1594 | line_parity ^= data; | |
1595 | column_parity ^= (data & 1) << j; | |
1596 | *forward_ptr++ = data; | |
1597 | data >>= 1; | |
1598 | } | |
1599 | *forward_ptr++ = line_parity; | |
1600 | if(i == 1) | |
1601 | data = data_hi; | |
1602 | } | |
1603 | ||
1604 | for(j=0; j<8; j++) { | |
1605 | *forward_ptr++ = column_parity; | |
1606 | column_parity >>= 1; | |
1607 | } | |
1608 | *forward_ptr = 0; | |
1609 | ||
1610 | return 45; //return number of emited bits | |
e09f21fa | 1611 | } |
1612 | ||
1613 | //==================================================================== | |
1614 | // Forward Link send function | |
1615 | // Requires: forwarLink_data filled with valid bits (1 bit per byte) | |
1616 | // fwd_bit_count set with number of bits to be sent | |
1617 | //==================================================================== | |
1618 | void SendForward(uint8_t fwd_bit_count) { | |
1619 | ||
e0165dcf | 1620 | fwd_write_ptr = forwardLink_data; |
1621 | fwd_bit_sz = fwd_bit_count; | |
1622 | ||
1623 | LED_D_ON(); | |
1624 | ||
6a09bea4 | 1625 | // Set up FPGA, 125kHz |
1626 | LFSetupFPGAForADC(95, true); | |
1627 | ||
e0165dcf | 1628 | // force 1st mod pulse (start gap must be longer for 4305) |
1629 | fwd_bit_sz--; //prepare next bit modulation | |
1630 | fwd_write_ptr++; | |
1631 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
b4a6775b | 1632 | SpinDelayUs(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments |
e0165dcf | 1633 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on |
b4a6775b | 1634 | SpinDelayUs(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments |
e0165dcf | 1635 | |
1636 | // now start writting | |
1637 | while(fwd_bit_sz-- > 0) { //prepare next bit modulation | |
1638 | if(((*fwd_write_ptr++) & 1) == 1) | |
b4a6775b | 1639 | SpinDelayUs(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments |
e0165dcf | 1640 | else { |
1641 | //These timings work for 4469/4269/4305 (with the 55*8 above) | |
1642 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
b4a6775b | 1643 | SpinDelayUs(23*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments |
e0165dcf | 1644 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on |
b4a6775b | 1645 | SpinDelayUs(9*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments |
e0165dcf | 1646 | } |
1647 | } | |
e09f21fa | 1648 | } |
1649 | ||
1650 | void EM4xLogin(uint32_t Password) { | |
1651 | ||
e0165dcf | 1652 | uint8_t fwd_bit_count; |
e09f21fa | 1653 | |
e0165dcf | 1654 | forward_ptr = forwardLink_data; |
1655 | fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN ); | |
1656 | fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 ); | |
e09f21fa | 1657 | |
e0165dcf | 1658 | SendForward(fwd_bit_count); |
e09f21fa | 1659 | |
e0165dcf | 1660 | //Wait for command to complete |
1661 | SpinDelay(20); | |
e09f21fa | 1662 | } |
1663 | ||
1664 | void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { | |
1665 | ||
a739812e | 1666 | uint8_t fwd_bit_count; |
e0165dcf | 1667 | uint8_t *dest = BigBuf_get_addr(); |
a739812e | 1668 | uint16_t bufsize = BigBuf_max_traceLen(); |
b8f705e7 | 1669 | uint32_t i = 0; |
1670 | ||
c0f15a05 | 1671 | // Clear destination buffer before sending the command |
a739812e | 1672 | BigBuf_Clear_ext(false); |
b8f705e7 | 1673 | |
e0165dcf | 1674 | //If password mode do login |
1675 | if (PwdMode == 1) EM4xLogin(Pwd); | |
1676 | ||
1677 | forward_ptr = forwardLink_data; | |
1678 | fwd_bit_count = Prepare_Cmd( FWD_CMD_READ ); | |
1679 | fwd_bit_count += Prepare_Addr( Address ); | |
1680 | ||
e0165dcf | 1681 | // Connect the A/D to the peak-detected low-frequency path. |
1682 | SetAdcMuxFor(GPIO_MUXSEL_LOPKD); | |
1683 | // Now set up the SSC to get the ADC samples that are now streaming at us. | |
1684 | FpgaSetupSsc(); | |
1685 | ||
1686 | SendForward(fwd_bit_count); | |
1687 | ||
1688 | // Now do the acquisition | |
1689 | i = 0; | |
1690 | for(;;) { | |
1691 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { | |
1692 | AT91C_BASE_SSC->SSC_THR = 0x43; | |
1693 | } | |
1694 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { | |
1695 | dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; | |
b8f705e7 | 1696 | ++i; |
a739812e | 1697 | if (i >= bufsize) break; |
e0165dcf | 1698 | } |
1699 | } | |
6a09bea4 | 1700 | |
1701 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
b8f705e7 | 1702 | cmd_send(CMD_ACK,0,0,0,0,0); |
e0165dcf | 1703 | LED_D_OFF(); |
e09f21fa | 1704 | } |
1705 | ||
1706 | void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { | |
1707 | ||
e0165dcf | 1708 | uint8_t fwd_bit_count; |
e09f21fa | 1709 | |
e0165dcf | 1710 | //If password mode do login |
1711 | if (PwdMode == 1) EM4xLogin(Pwd); | |
e09f21fa | 1712 | |
e0165dcf | 1713 | forward_ptr = forwardLink_data; |
1714 | fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE ); | |
1715 | fwd_bit_count += Prepare_Addr( Address ); | |
1716 | fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 ); | |
e09f21fa | 1717 | |
e0165dcf | 1718 | SendForward(fwd_bit_count); |
e09f21fa | 1719 | |
e0165dcf | 1720 | //Wait for write to complete |
1721 | SpinDelay(20); | |
1722 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
1723 | LED_D_OFF(); | |
e09f21fa | 1724 | } |