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[proxmark3-svn] / armsrc / lfops.c
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e09f21fa 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
9//-----------------------------------------------------------------------------
10
11#include "proxmark3.h"
12#include "apps.h"
13#include "util.h"
14#include "hitag2.h"
15#include "crc16.h"
16#include "string.h"
17#include "lfdemod.h"
18#include "lfsampling.h"
1d0ccbe0 19#include "protocols.h"
20#include "usb_cdc.h" //test
e09f21fa 21
22/**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
9276e859 29void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint32_t period_1, uint8_t *command)
e09f21fa 30{
31
e0165dcf 32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
e09f21fa 34
e0165dcf 35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
e09f21fa 37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
e0165dcf 51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
e09f21fa 56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
e0165dcf 58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
e09f21fa 68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
e0165dcf 70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
e09f21fa 71
e0165dcf 72 // now do the read
e09f21fa 73 DoAcquisition_config(false);
74}
75
e09f21fa 76/* blank r/w tag data stream
77...0000000000000000 01111111
781010101010101010101010101010101010101010101010101010101010101010
790011010010100001
8001111111
81101010101010101[0]000...
82
83[5555fe852c5555555555555555fe0000]
84*/
85void ReadTItag(void)
86{
e0165dcf 87 // some hardcoded initial params
88 // when we read a TI tag we sample the zerocross line at 2Mhz
89 // TI tags modulate a 1 as 16 cycles of 123.2Khz
90 // TI tags modulate a 0 as 16 cycles of 134.2Khz
0de8e387 91 #define FSAMPLE 2000000
92 #define FREQLO 123200
93 #define FREQHI 134200
e09f21fa 94
e0165dcf 95 signed char *dest = (signed char *)BigBuf_get_addr();
96 uint16_t n = BigBuf_max_traceLen();
97 // 128 bit shift register [shift3:shift2:shift1:shift0]
98 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
99
100 int i, cycles=0, samples=0;
101 // how many sample points fit in 16 cycles of each frequency
102 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
103 // when to tell if we're close enough to one freq or another
104 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
105
106 // TI tags charge at 134.2Khz
107 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
108 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
109
110 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
111 // connects to SSP_DIN and the SSP_DOUT logic level controls
112 // whether we're modulating the antenna (high)
113 // or listening to the antenna (low)
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
115
116 // get TI tag data into the buffer
117 AcquireTiType();
118
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
120
121 for (i=0; i<n-1; i++) {
122 // count cycles by looking for lo to hi zero crossings
123 if ( (dest[i]<0) && (dest[i+1]>0) ) {
124 cycles++;
125 // after 16 cycles, measure the frequency
126 if (cycles>15) {
127 cycles=0;
128 samples=i-samples; // number of samples in these 16 cycles
129
130 // TI bits are coming to us lsb first so shift them
131 // right through our 128 bit right shift register
132 shift0 = (shift0>>1) | (shift1 << 31);
133 shift1 = (shift1>>1) | (shift2 << 31);
134 shift2 = (shift2>>1) | (shift3 << 31);
135 shift3 >>= 1;
136
137 // check if the cycles fall close to the number
138 // expected for either the low or high frequency
139 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
140 // low frequency represents a 1
141 shift3 |= (1<<31);
142 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
143 // high frequency represents a 0
144 } else {
145 // probably detected a gay waveform or noise
146 // use this as gaydar or discard shift register and start again
147 shift3 = shift2 = shift1 = shift0 = 0;
148 }
149 samples = i;
150
151 // for each bit we receive, test if we've detected a valid tag
152
153 // if we see 17 zeroes followed by 6 ones, we might have a tag
154 // remember the bits are backwards
155 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
156 // if start and end bytes match, we have a tag so break out of the loop
157 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
158 cycles = 0xF0B; //use this as a flag (ugly but whatever)
159 break;
160 }
161 }
162 }
163 }
164 }
165
166 // if flag is set we have a tag
167 if (cycles!=0xF0B) {
168 DbpString("Info: No valid tag detected.");
169 } else {
170 // put 64 bit data into shift1 and shift0
171 shift0 = (shift0>>24) | (shift1 << 8);
172 shift1 = (shift1>>24) | (shift2 << 8);
173
174 // align 16 bit crc into lower half of shift2
175 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
176
177 // if r/w tag, check ident match
e09f21fa 178 if (shift3 & (1<<15) ) {
e0165dcf 179 DbpString("Info: TI tag is rewriteable");
180 // only 15 bits compare, last bit of ident is not valid
e09f21fa 181 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
e0165dcf 182 DbpString("Error: Ident mismatch!");
183 } else {
184 DbpString("Info: TI tag ident is valid");
185 }
186 } else {
187 DbpString("Info: TI tag is readonly");
188 }
189
190 // WARNING the order of the bytes in which we calc crc below needs checking
191 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
192 // bytes in reverse or something
193 // calculate CRC
194 uint32_t crc=0;
195
196 crc = update_crc16(crc, (shift0)&0xff);
197 crc = update_crc16(crc, (shift0>>8)&0xff);
198 crc = update_crc16(crc, (shift0>>16)&0xff);
199 crc = update_crc16(crc, (shift0>>24)&0xff);
200 crc = update_crc16(crc, (shift1)&0xff);
201 crc = update_crc16(crc, (shift1>>8)&0xff);
202 crc = update_crc16(crc, (shift1>>16)&0xff);
203 crc = update_crc16(crc, (shift1>>24)&0xff);
204
1a570b0a 205 Dbprintf("Info: Tag data: %x%08x, crc=%x", (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
e0165dcf 206 if (crc != (shift2&0xffff)) {
207 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
208 } else {
209 DbpString("Info: CRC is good");
210 }
211 }
e09f21fa 212}
213
214void WriteTIbyte(uint8_t b)
215{
e0165dcf 216 int i = 0;
217
218 // modulate 8 bits out to the antenna
219 for (i=0; i<8; i++)
220 {
221 if (b&(1<<i)) {
222 // stop modulating antenna
223 LOW(GPIO_SSC_DOUT);
224 SpinDelayUs(1000);
225 // modulate antenna
226 HIGH(GPIO_SSC_DOUT);
227 SpinDelayUs(1000);
228 } else {
229 // stop modulating antenna
230 LOW(GPIO_SSC_DOUT);
231 SpinDelayUs(300);
232 // modulate antenna
233 HIGH(GPIO_SSC_DOUT);
234 SpinDelayUs(1700);
235 }
236 }
e09f21fa 237}
238
239void AcquireTiType(void)
240{
e0165dcf 241 int i, j, n;
242 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
243 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
a739812e 244 #define TIBUFLEN 1250
e09f21fa 245
e0165dcf 246 // clear buffer
a739812e 247 uint32_t *buf = (uint32_t *)BigBuf_get_addr();
248
249 //clear buffer now so it does not interfere with timing later
250 BigBuf_Clear_ext(false);
e0165dcf 251
252 // Set up the synchronous serial port
253 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
254 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
255
256 // steal this pin from the SSP and use it to control the modulation
257 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
258 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
259
260 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
262
263 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
264 // 48/2 = 24 MHz clock must be divided by 12
265 AT91C_BASE_SSC->SSC_CMR = 12;
266
267 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
268 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
269 AT91C_BASE_SSC->SSC_TCMR = 0;
270 AT91C_BASE_SSC->SSC_TFMR = 0;
271
272 LED_D_ON();
273
274 // modulate antenna
275 HIGH(GPIO_SSC_DOUT);
276
277 // Charge TI tag for 50ms.
278 SpinDelay(50);
279
280 // stop modulating antenna and listen
281 LOW(GPIO_SSC_DOUT);
282
283 LED_D_OFF();
284
285 i = 0;
286 for(;;) {
287 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
a739812e 288 buf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
e0165dcf 289 i++; if(i >= TIBUFLEN) break;
290 }
291 WDT_HIT();
292 }
293
294 // return stolen pin to SSP
295 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
296 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
297
298 char *dest = (char *)BigBuf_get_addr();
a739812e 299 n = TIBUFLEN * 32;
300
e0165dcf 301 // unpack buffer
a739812e 302 for (i = TIBUFLEN-1; i >= 0; i--) {
303 for (j = 0; j < 32; j++) {
304 if(buf[i] & (1 << j)) {
e0165dcf 305 dest[--n] = 1;
306 } else {
307 dest[--n] = -1;
308 }
309 }
310 }
e09f21fa 311}
312
313// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
314// if crc provided, it will be written with the data verbatim (even if bogus)
315// if not provided a valid crc will be computed from the data and written.
316void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
317{
e0165dcf 318 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
319 if(crc == 0) {
320 crc = update_crc16(crc, (idlo)&0xff);
321 crc = update_crc16(crc, (idlo>>8)&0xff);
322 crc = update_crc16(crc, (idlo>>16)&0xff);
323 crc = update_crc16(crc, (idlo>>24)&0xff);
324 crc = update_crc16(crc, (idhi)&0xff);
325 crc = update_crc16(crc, (idhi>>8)&0xff);
326 crc = update_crc16(crc, (idhi>>16)&0xff);
327 crc = update_crc16(crc, (idhi>>24)&0xff);
328 }
a739812e 329 Dbprintf("Writing to tag: %x%08x, crc=%x", (unsigned int) idhi, (unsigned int) idlo, crc);
e0165dcf 330
331 // TI tags charge at 134.2Khz
332 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
333 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
334 // connects to SSP_DIN and the SSP_DOUT logic level controls
335 // whether we're modulating the antenna (high)
336 // or listening to the antenna (low)
337 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
338 LED_A_ON();
339
340 // steal this pin from the SSP and use it to control the modulation
341 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
342 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
343
344 // writing algorithm:
345 // a high bit consists of a field off for 1ms and field on for 1ms
346 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
347 // initiate a charge time of 50ms (field on) then immediately start writing bits
348 // start by writing 0xBB (keyword) and 0xEB (password)
349 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
350 // finally end with 0x0300 (write frame)
1a570b0a 351 // all data is sent lsb first
e0165dcf 352 // finish with 15ms programming time
353
354 // modulate antenna
355 HIGH(GPIO_SSC_DOUT);
356 SpinDelay(50); // charge time
357
358 WriteTIbyte(0xbb); // keyword
359 WriteTIbyte(0xeb); // password
360 WriteTIbyte( (idlo )&0xff );
361 WriteTIbyte( (idlo>>8 )&0xff );
362 WriteTIbyte( (idlo>>16)&0xff );
363 WriteTIbyte( (idlo>>24)&0xff );
364 WriteTIbyte( (idhi )&0xff );
365 WriteTIbyte( (idhi>>8 )&0xff );
366 WriteTIbyte( (idhi>>16)&0xff );
367 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
368 WriteTIbyte( (crc )&0xff ); // crc lo
369 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
370 WriteTIbyte(0x00); // write frame lo
371 WriteTIbyte(0x03); // write frame hi
372 HIGH(GPIO_SSC_DOUT);
373 SpinDelay(50); // programming time
374
375 LED_A_OFF();
376
377 // get TI tag data into the buffer
378 AcquireTiType();
379
380 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
b8f705e7 381 DbpString("Now use 'lf ti read' to check");
e09f21fa 382}
383
cd073027 384void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
e09f21fa 385{
e0165dcf 386 int i;
387 uint8_t *tab = BigBuf_get_addr();
e09f21fa 388
e0165dcf 389 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
e09f21fa 391
e0165dcf 392 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
e0165dcf 393 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
394 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
e09f21fa 395
396 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
a739812e 397 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
e09f21fa 398
e0165dcf 399 i = 0;
400 for(;;) {
401 //wait until SSC_CLK goes HIGH
402 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
c35145bf 403 if(BUTTON_PRESS() || usb_poll_validate_length() ) {
e0165dcf 404 DbpString("Stopped");
405 return;
406 }
407 WDT_HIT();
408 }
a739812e 409 if (ledcontrol) LED_D_ON();
e0165dcf 410
411 if(tab[i])
412 OPEN_COIL();
413 else
414 SHORT_COIL();
415
a739812e 416 if (ledcontrol) LED_D_OFF();
417
e0165dcf 418 //wait until SSC_CLK goes LOW
419 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
c35145bf 420 if( BUTTON_PRESS() || usb_poll_validate_length() ) {
e0165dcf 421 DbpString("Stopped");
422 return;
423 }
424 WDT_HIT();
425 }
426
427 i++;
428 if(i == period) {
429
430 i = 0;
431 if (gap) {
432 SHORT_COIL();
433 SpinDelayUs(gap);
434 }
435 }
436 }
e09f21fa 437}
438
e09f21fa 439#define DEBUG_FRAME_CONTENTS 1
440void SimulateTagLowFrequencyBidir(int divisor, int t0)
441{
442}
443
444// compose fc/8 fc/10 waveform (FSK2)
445static void fc(int c, int *n)
446{
e0165dcf 447 uint8_t *dest = BigBuf_get_addr();
448 int idx;
449
450 // for when we want an fc8 pattern every 4 logical bits
451 if(c==0) {
452 dest[((*n)++)]=1;
453 dest[((*n)++)]=1;
454 dest[((*n)++)]=1;
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=0;
457 dest[((*n)++)]=0;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 }
461
462 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
463 if(c==8) {
464 for (idx=0; idx<6; idx++) {
465 dest[((*n)++)]=1;
466 dest[((*n)++)]=1;
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=0;
470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 }
474 }
475
476 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
477 if(c==10) {
478 for (idx=0; idx<5; idx++) {
479 dest[((*n)++)]=1;
480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=0;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 }
490 }
e09f21fa 491}
492// compose fc/X fc/Y waveform (FSKx)
712ebfa6 493static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
e09f21fa 494{
e0165dcf 495 uint8_t *dest = BigBuf_get_addr();
496 uint8_t halfFC = fc/2;
497 uint8_t wavesPerClock = clock/fc;
498 uint8_t mod = clock % fc; //modifier
499 uint8_t modAdj = fc/mod; //how often to apply modifier
500 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
501 // loop through clock - step field clock
502 for (uint8_t idx=0; idx < wavesPerClock; idx++){
503 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
504 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
505 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
506 *n += fc;
507 }
508 if (mod>0) (*modCnt)++;
509 if ((mod>0) && modAdjOk){ //fsk2
510 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
511 memset(dest+(*n), 0, fc-halfFC);
512 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
513 *n += fc;
514 }
515 }
516 if (mod>0 && !modAdjOk){ //fsk1
517 memset(dest+(*n), 0, mod-(mod/2));
518 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
519 *n += mod;
520 }
e09f21fa 521}
522
523// prepare a waveform pattern in the buffer based on the ID given then
524// simulate a HID tag until the button is pressed
525void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
526{
e0165dcf 527 int n=0, i=0;
528 /*
529 HID tag bitstream format
530 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
531 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
532 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
533 A fc8 is inserted before every 4 bits
534 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
535 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
536 */
537
538 if (hi>0xFFF) {
539 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
540 return;
541 }
542 fc(0,&n);
543 // special start of frame marker containing invalid bit sequences
544 fc(8, &n); fc(8, &n); // invalid
545 fc(8, &n); fc(10, &n); // logical 0
546 fc(10, &n); fc(10, &n); // invalid
547 fc(8, &n); fc(10, &n); // logical 0
548
549 WDT_HIT();
550 // manchester encode bits 43 to 32
551 for (i=11; i>=0; i--) {
552 if ((i%4)==3) fc(0,&n);
553 if ((hi>>i)&1) {
554 fc(10, &n); fc(8, &n); // low-high transition
555 } else {
556 fc(8, &n); fc(10, &n); // high-low transition
557 }
558 }
559
560 WDT_HIT();
561 // manchester encode bits 31 to 0
562 for (i=31; i>=0; i--) {
563 if ((i%4)==3) fc(0,&n);
564 if ((lo>>i)&1) {
565 fc(10, &n); fc(8, &n); // low-high transition
566 } else {
567 fc(8, &n); fc(10, &n); // high-low transition
568 }
569 }
570
a739812e 571 if (ledcontrol) LED_A_ON();
e0165dcf 572 SimulateTagLowFrequency(n, 0, ledcontrol);
a739812e 573 if (ledcontrol) LED_A_OFF();
e09f21fa 574}
575
576// prepare a waveform pattern in the buffer based on the ID given then
577// simulate a FSK tag until the button is pressed
578// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
579void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
580{
e0165dcf 581 int ledcontrol=1;
582 int n=0, i=0;
583 uint8_t fcHigh = arg1 >> 8;
584 uint8_t fcLow = arg1 & 0xFF;
585 uint16_t modCnt = 0;
586 uint8_t clk = arg2 & 0xFF;
587 uint8_t invert = (arg2 >> 8) & 1;
588
589 for (i=0; i<size; i++){
590 if (BitStream[i] == invert){
591 fcAll(fcLow, &n, clk, &modCnt);
592 } else {
593 fcAll(fcHigh, &n, clk, &modCnt);
594 }
595 }
596 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
e0165dcf 597
508b37ba 598 if (ledcontrol) LED_A_ON();
e0165dcf 599 SimulateTagLowFrequency(n, 0, ledcontrol);
508b37ba 600 if (ledcontrol) LED_A_OFF();
e09f21fa 601}
602
603// compose ask waveform for one bit(ASK)
e0165dcf 604static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
e09f21fa 605{
e0165dcf 606 uint8_t *dest = BigBuf_get_addr();
607 uint8_t halfClk = clock/2;
608 // c = current bit 1 or 0
609 if (manchester==1){
610 memset(dest+(*n), c, halfClk);
611 memset(dest+(*n) + halfClk, c^1, halfClk);
612 } else {
613 memset(dest+(*n), c, clock);
614 }
615 *n += clock;
e09f21fa 616}
617
b41534d1 618static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
619{
e0165dcf 620 uint8_t *dest = BigBuf_get_addr();
621 uint8_t halfClk = clock/2;
622 if (c){
623 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
624 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
625 } else {
626 memset(dest+(*n), c ^ *phase, clock);
627 *phase ^= 1;
628 }
b41534d1 629
630}
631
e09f21fa 632// args clock, ask/man or askraw, invert, transmission separator
633void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
634{
e0165dcf 635 int ledcontrol = 1;
636 int n=0, i=0;
637 uint8_t clk = (arg1 >> 8) & 0xFF;
2b3af97d 638 uint8_t encoding = arg1 & 0xFF;
e0165dcf 639 uint8_t separator = arg2 & 1;
640 uint8_t invert = (arg2 >> 8) & 1;
641
642 if (encoding==2){ //biphase
643 uint8_t phase=0;
644 for (i=0; i<size; i++){
645 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
646 }
647 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
648 for (i=0; i<size; i++){
649 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
650 }
651 }
652 } else { // ask/manchester || ask/raw
653 for (i=0; i<size; i++){
654 askSimBit(BitStream[i]^invert, &n, clk, encoding);
655 }
656 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
657 for (i=0; i<size; i++){
658 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
659 }
660 }
661 }
662
663 if (separator==1) Dbprintf("sorry but separator option not yet available");
664
665 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
e0165dcf 666
a739812e 667 if (ledcontrol) LED_A_ON();
e0165dcf 668 SimulateTagLowFrequency(n, 0, ledcontrol);
a739812e 669 if (ledcontrol) LED_A_OFF();
e09f21fa 670}
671
672//carrier can be 2,4 or 8
673static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
674{
e0165dcf 675 uint8_t *dest = BigBuf_get_addr();
676 uint8_t halfWave = waveLen/2;
677 //uint8_t idx;
678 int i = 0;
679 if (phaseChg){
680 // write phase change
681 memset(dest+(*n), *curPhase^1, halfWave);
682 memset(dest+(*n) + halfWave, *curPhase, halfWave);
683 *n += waveLen;
684 *curPhase ^= 1;
685 i += waveLen;
686 }
687 //write each normal clock wave for the clock duration
688 for (; i < clk; i+=waveLen){
689 memset(dest+(*n), *curPhase, halfWave);
690 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
691 *n += waveLen;
692 }
e09f21fa 693}
694
695// args clock, carrier, invert,
696void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
697{
a739812e 698 int ledcontrol = 1;
e0165dcf 699 int n=0, i=0;
700 uint8_t clk = arg1 >> 8;
701 uint8_t carrier = arg1 & 0xFF;
702 uint8_t invert = arg2 & 0xFF;
703 uint8_t curPhase = 0;
704 for (i=0; i<size; i++){
705 if (BitStream[i] == curPhase){
706 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
707 } else {
708 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
709 }
710 }
711 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
e0165dcf 712
a739812e 713 if (ledcontrol) LED_A_ON();
e0165dcf 714 SimulateTagLowFrequency(n, 0, ledcontrol);
a739812e 715 if (ledcontrol) LED_A_OFF();
e09f21fa 716}
717
718// loop to get raw HID waveform then FSK demodulate the TAG ID from it
719void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
720{
e0165dcf 721 uint8_t *dest = BigBuf_get_addr();
e0165dcf 722 size_t size = 0;
723 uint32_t hi2=0, hi=0, lo=0;
724 int idx=0;
725 // Configure to go in 125Khz listen mode
726 LFSetupFPGAForADC(95, true);
e09f21fa 727
6427695b 728 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
e09f21fa 729
e0165dcf 730 WDT_HIT();
731 if (ledcontrol) LED_A_ON();
e09f21fa 732
733 DoAcquisition_default(-1,true);
734 // FSK demodulator
b8f705e7 735 size = 50*128*2; //big enough to catch 2 sequences of largest format
e09f21fa 736 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
e0165dcf 737
b8f705e7 738 if (idx>0 && lo>0 && (size==96 || size==192)){
739 // go over previously decoded manchester data and decode into usable tag ID
740 if (hi2 != 0){ //extra large HID tags 88/192 bits
e0165dcf 741 Dbprintf("TAG ID: %x%08x%08x (%d)",
a739812e 742 (unsigned int) hi2,
743 (unsigned int) hi,
744 (unsigned int) lo,
745 (unsigned int) (lo>>1) & 0xFFFF
746 );
614da335 747 } else { //standard HID tags 44/96 bits
e0165dcf 748 uint8_t bitlen = 0;
749 uint32_t fc = 0;
750 uint32_t cardnum = 0;
a739812e 751
e09f21fa 752 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
e0165dcf 753 uint32_t lo2=0;
754 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
755 uint8_t idx3 = 1;
e09f21fa 756 while(lo2 > 1){ //find last bit set to 1 (format len bit)
757 lo2=lo2 >> 1;
e0165dcf 758 idx3++;
759 }
e09f21fa 760 bitlen = idx3+19;
e0165dcf 761 fc =0;
762 cardnum=0;
e09f21fa 763 if(bitlen == 26){
e0165dcf 764 cardnum = (lo>>1)&0xFFFF;
765 fc = (lo>>17)&0xFF;
766 }
e09f21fa 767 if(bitlen == 37){
e0165dcf 768 cardnum = (lo>>1)&0x7FFFF;
769 fc = ((hi&0xF)<<12)|(lo>>20);
770 }
e09f21fa 771 if(bitlen == 34){
e0165dcf 772 cardnum = (lo>>1)&0xFFFF;
773 fc= ((hi&1)<<15)|(lo>>17);
774 }
e09f21fa 775 if(bitlen == 35){
e0165dcf 776 cardnum = (lo>>1)&0xFFFFF;
777 fc = ((hi&1)<<11)|(lo>>21);
778 }
779 }
780 else { //if bit 38 is not set then 37 bit format is used
781 bitlen= 37;
782 fc =0;
783 cardnum=0;
784 if(bitlen==37){
785 cardnum = (lo>>1)&0x7FFFF;
786 fc = ((hi&0xF)<<12)|(lo>>20);
787 }
788 }
e0165dcf 789 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
a739812e 790 (unsigned int) hi,
791 (unsigned int) lo,
792 (unsigned int) (lo>>1) & 0xFFFF,
793 (unsigned int) bitlen,
794 (unsigned int) fc,
795 (unsigned int) cardnum);
e0165dcf 796 }
797 if (findone){
798 if (ledcontrol) LED_A_OFF();
799 *high = hi;
800 *low = lo;
801 return;
802 }
803 // reset
e0165dcf 804 }
b8f705e7 805 hi2 = hi = lo = idx = 0;
e0165dcf 806 WDT_HIT();
807 }
808 DbpString("Stopped");
809 if (ledcontrol) LED_A_OFF();
e09f21fa 810}
811
db25599d 812// loop to get raw HID waveform then FSK demodulate the TAG ID from it
813void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
814{
815 uint8_t *dest = BigBuf_get_addr();
db25599d 816 size_t size;
817 int idx=0;
818 // Configure to go in 125Khz listen mode
819 LFSetupFPGAForADC(95, true);
820
6427695b 821 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
db25599d 822
823 WDT_HIT();
824 if (ledcontrol) LED_A_ON();
825
826 DoAcquisition_default(-1,true);
827 // FSK demodulator
db25599d 828 size = 50*128*2; //big enough to catch 2 sequences of largest format
829 idx = AWIDdemodFSK(dest, &size);
830
a126332a 831 if (idx<=0 || size!=96) continue;
db25599d 832 // Index map
833 // 0 10 20 30 40 50 60
834 // | | | | | | |
835 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
836 // -----------------------------------------------------------------------------
837 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
838 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
839 // |---26 bit---| |-----117----||-------------142-------------|
840 // b = format bit len, o = odd parity of last 3 bits
841 // f = facility code, c = card number
842 // w = wiegand parity
843 // (26 bit format shown)
844
845 //get raw ID before removing parities
846 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
847 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
848 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
849
850 size = removeParity(dest, idx+8, 4, 1, 88);
a126332a 851 if (size != 66) continue;
db25599d 852 // ok valid card found!
853
854 // Index map
855 // 0 10 20 30 40 50 60
856 // | | | | | | |
857 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
858 // -----------------------------------------------------------------------------
859 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
860 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
861 // |26 bit| |-117--| |-----142------|
862 // b = format bit len, o = odd parity of last 3 bits
863 // f = facility code, c = card number
864 // w = wiegand parity
865 // (26 bit format shown)
866
867 uint32_t fc = 0;
868 uint32_t cardnum = 0;
869 uint32_t code1 = 0;
870 uint32_t code2 = 0;
871 uint8_t fmtLen = bytebits_to_byte(dest,8);
872 if (fmtLen==26){
873 fc = bytebits_to_byte(dest+9, 8);
874 cardnum = bytebits_to_byte(dest+17, 16);
875 code1 = bytebits_to_byte(dest+8,fmtLen);
876 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
877 } else {
878 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
879 if (fmtLen>32){
880 code1 = bytebits_to_byte(dest+8,fmtLen-32);
881 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
882 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
883 } else{
884 code1 = bytebits_to_byte(dest+8,fmtLen);
885 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
886 }
887 }
888 if (findone){
889 if (ledcontrol) LED_A_OFF();
890 return;
891 }
892 // reset
db25599d 893 idx = 0;
894 WDT_HIT();
895 }
896 DbpString("Stopped");
897 if (ledcontrol) LED_A_OFF();
898}
899
e09f21fa 900void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
901{
e0165dcf 902 uint8_t *dest = BigBuf_get_addr();
903
904 size_t size=0, idx=0;
905 int clk=0, invert=0, errCnt=0, maxErr=20;
906 uint32_t hi=0;
907 uint64_t lo=0;
908 // Configure to go in 125Khz listen mode
909 LFSetupFPGAForADC(95, true);
910
6427695b 911 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
e0165dcf 912
913 WDT_HIT();
914 if (ledcontrol) LED_A_ON();
915
916 DoAcquisition_default(-1,true);
917 size = BigBuf_max_traceLen();
e0165dcf 918 //askdemod and manchester decode
b8f705e7 919 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
fef74fdc 920 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
e0165dcf 921 WDT_HIT();
922
b8f705e7 923 if (errCnt<0) continue;
924
e0165dcf 925 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
e0165dcf 926 if (errCnt){
927 if (size>64){
928 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
929 hi,
930 (uint32_t)(lo>>32),
931 (uint32_t)lo,
932 (uint32_t)(lo&0xFFFF),
933 (uint32_t)((lo>>16LL) & 0xFF),
934 (uint32_t)(lo & 0xFFFFFF));
935 } else {
936 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
937 (uint32_t)(lo>>32),
938 (uint32_t)lo,
939 (uint32_t)(lo&0xFFFF),
940 (uint32_t)((lo>>16LL) & 0xFF),
941 (uint32_t)(lo & 0xFFFFFF));
942 }
b8f705e7 943
e0165dcf 944 if (findone){
945 if (ledcontrol) LED_A_OFF();
946 *high=lo>>32;
947 *low=lo & 0xFFFFFFFF;
948 return;
949 }
e0165dcf 950 }
951 WDT_HIT();
b8f705e7 952 hi = lo = size = idx = 0;
953 clk = invert = errCnt = 0;
e0165dcf 954 }
955 DbpString("Stopped");
956 if (ledcontrol) LED_A_OFF();
e09f21fa 957}
958
959void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
960{
e0165dcf 961 uint8_t *dest = BigBuf_get_addr();
962 int idx=0;
963 uint32_t code=0, code2=0;
964 uint8_t version=0;
965 uint8_t facilitycode=0;
966 uint16_t number=0;
b8f705e7 967 uint8_t crc = 0;
968 uint16_t calccrc = 0;
e0165dcf 969 // Configure to go in 125Khz listen mode
970 LFSetupFPGAForADC(95, true);
971
6427695b 972 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
e0165dcf 973 WDT_HIT();
974 if (ledcontrol) LED_A_ON();
e09f21fa 975 DoAcquisition_default(-1,true);
976 //fskdemod and get start index
e0165dcf 977 WDT_HIT();
978 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
b8f705e7 979 if (idx<0) continue;
e0165dcf 980 //valid tag found
981
982 //Index map
983 //0 10 20 30 40 50 60
984 //| | | | | | |
985 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
986 //-----------------------------------------------------------------------------
b8f705e7 987 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
e0165dcf 988 //
b8f705e7 989 //Checksum:
990 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
991 //preamble F0 E0 01 03 B6 75
992 // How to calc checksum,
993 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
994 // F0 + E0 + 01 + 03 + B6 = 28A
995 // 28A & FF = 8A
996 // FF - 8A = 75
997 // Checksum: 0x75
e0165dcf 998 //XSF(version)facility:codeone+codetwo
999 //Handle the data
1000 if(findone){ //only print binary if we are doing one
1001 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1002 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1003 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1004 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1005 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1006 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1007 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1008 }
1009 code = bytebits_to_byte(dest+idx,32);
1010 code2 = bytebits_to_byte(dest+idx+32,32);
1011 version = bytebits_to_byte(dest+idx+27,8); //14,4
a739812e 1012 facilitycode = bytebits_to_byte(dest+idx+18,8);
e0165dcf 1013 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1014
b8f705e7 1015 crc = bytebits_to_byte(dest+idx+54,8);
1016 for (uint8_t i=1; i<6; ++i)
1017 calccrc += bytebits_to_byte(dest+idx+9*i,8);
1018 calccrc &= 0xff;
1019 calccrc = 0xff - calccrc;
1020
1021 char *crcStr = (crc == calccrc) ? "ok":"!crc";
1022
1023 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
e0165dcf 1024 // if we're only looking for one tag
1025 if (findone){
1026 if (ledcontrol) LED_A_OFF();
e0165dcf 1027 *high=code;
1028 *low=code2;
1029 return;
1030 }
1031 code=code2=0;
1032 version=facilitycode=0;
1033 number=0;
1034 idx=0;
b8f705e7 1035
e0165dcf 1036 WDT_HIT();
1037 }
1038 DbpString("Stopped");
1039 if (ledcontrol) LED_A_OFF();
e09f21fa 1040}
1041
1042/*------------------------------
94422fa2 1043 * T5555/T5557/T5567/T5577 routines
e09f21fa 1044 *------------------------------
1d0ccbe0 1045 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1046 *
1047 * Relevant communication times in microsecond
e09f21fa 1048 * To compensate antenna falling times shorten the write times
1049 * and enlarge the gap ones.
6a09bea4 1050 * Q5 tags seems to have issues when these values changes.
e09f21fa 1051 */
0de8e387 1052
8ce3e4b4 1053#define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
4a3f1a37 1054#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
8ce3e4b4 1055#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
4a3f1a37 1056#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
6426f6ba 1057#define READ_GAP 15*8
b8f705e7 1058
1059// VALUES TAKEN FROM EM4x function: SendForward
1060// START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1061// WRITE_GAP = 128; (16*8)
1062// WRITE_1 = 256 32*8; (32*8)
1063
1064// These timings work for 4469/4269/4305 (with the 55*8 above)
1065// WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1066
1067// Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1068// TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1069// Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1070// T0 = TIMER_CLOCK1 / 125000 = 192
e16054a4 1071// 1 Cycle = 8 microseconds(us) == 1 field clock
e09f21fa 1072
a739812e 1073void TurnReadLFOn(int delay) {
1074 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1075 // Give it a bit of time for the resonant antenna to settle.
1d0ccbe0 1076
1077 // measure antenna strength.
1078 //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
1079 // where to save it
1080
1081 SpinDelayUs(delay);
a739812e 1082}
1083
e09f21fa 1084// Write one bit to card
e16054a4 1085void T55xxWriteBit(int bit) {
b8f705e7 1086 if (!bit)
1d0ccbe0 1087 TurnReadLFOn(WRITE_0);
e0165dcf 1088 else
1d0ccbe0 1089 TurnReadLFOn(WRITE_1);
e0165dcf 1090 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1091 SpinDelayUs(WRITE_GAP);
e09f21fa 1092}
1093
94422fa2 1094// Send T5577 reset command then read stream (see if we can identify the start of the stream)
1095void T55xxResetRead(void) {
1096 LED_A_ON();
1097 //clear buffer now so it does not interfere with timing later
1098 BigBuf_Clear_ext(false);
1099
1100 // Set up FPGA, 125kHz
1101 LFSetupFPGAForADC(95, true);
1102
1103 // Trigger T55x7 in mode.
1104 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1105 SpinDelayUs(START_GAP);
1106
1107 // reset tag - op code 00
1108 T55xxWriteBit(0);
1109 T55xxWriteBit(0);
1110
1111 // Turn field on to read the response
1112 TurnReadLFOn(READ_GAP);
1113
1114 // Acquisition
1115 doT55x7Acquisition(BigBuf_max_traceLen());
1116
1117 // Turn the field off
1118 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1119 cmd_send(CMD_ACK,0,0,0,0,0);
1120 LED_A_OFF();
1121}
1122
e09f21fa 1123// Write one card block in page 0, no lock
70459879 1124void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
e16054a4 1125 LED_A_ON();
1d0ccbe0 1126 bool PwdMode = arg & 0x1;
1127 uint8_t Page = (arg & 0x2)>>1;
e0165dcf 1128 uint32_t i = 0;
1129
1130 // Set up FPGA, 125kHz
ac2df346 1131 LFSetupFPGAForADC(95, true);
0de8e387 1132
e16054a4 1133 // Trigger T55x7 in mode.
e0165dcf 1134 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1135 SpinDelayUs(START_GAP);
1136
e16054a4 1137 // Opcode 10
e0165dcf 1138 T55xxWriteBit(1);
1d0ccbe0 1139 T55xxWriteBit(Page); //Page 0
9276e859 1140 if (PwdMode){
a739812e 1141 // Send Pwd
e0165dcf 1142 for (i = 0x80000000; i != 0; i >>= 1)
1143 T55xxWriteBit(Pwd & i);
1144 }
a739812e 1145 // Send Lock bit
e0165dcf 1146 T55xxWriteBit(0);
1147
a739812e 1148 // Send Data
e0165dcf 1149 for (i = 0x80000000; i != 0; i >>= 1)
1150 T55xxWriteBit(Data & i);
1151
a739812e 1152 // Send Block number
e0165dcf 1153 for (i = 0x04; i != 0; i >>= 1)
1154 T55xxWriteBit(Block & i);
1155
e16054a4 1156 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
e0165dcf 1157 // so wait a little more)
e16054a4 1158 TurnReadLFOn(20 * 1000);
1d0ccbe0 1159 //could attempt to do a read to confirm write took
1160 // as the tag should repeat back the new block
1161 // until it is reset, but to confirm it we would
1162 // need to know the current block 0 config mode
e16054a4 1163
a739812e 1164 // turn field off
e0165dcf 1165 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
9276e859 1166 LED_A_OFF();
e09f21fa 1167}
1168
94422fa2 1169// Write one card block in page 0, no lock
70459879 1170void T55xxWriteBlock(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
94422fa2 1171 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1172 cmd_send(CMD_ACK,0,0,0,0,0);
1173}
1174
6426f6ba 1175// Read one card block in page [page]
9276e859 1176void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
e16054a4 1177 LED_A_ON();
1d0ccbe0 1178 bool PwdMode = arg0 & 0x1;
1179 uint8_t Page = (arg0 & 0x2) >> 1;
e0165dcf 1180 uint32_t i = 0;
1d0ccbe0 1181 bool RegReadMode = (Block == 0xFF);
ac2df346 1182
a739812e 1183 //clear buffer now so it does not interfere with timing later
1184 BigBuf_Clear_ext(false);
1185
ac2df346 1186 //make sure block is at max 7
1187 Block &= 0x7;
e0165dcf 1188
1d0ccbe0 1189 // Set up FPGA, 125kHz to power up the tag
ac2df346 1190 LFSetupFPGAForADC(95, true);
0de8e387 1191
1d0ccbe0 1192 // Trigger T55x7 Direct Access Mode with start gap
e0165dcf 1193 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
ac2df346 1194 SpinDelayUs(START_GAP);
1195
1d0ccbe0 1196 // Opcode 1[page]
e0165dcf 1197 T55xxWriteBit(1);
1c8fbeb9 1198 T55xxWriteBit(Page); //Page 0
ac2df346 1199
9276e859 1200 if (PwdMode){
a739812e 1201 // Send Pwd
e0165dcf 1202 for (i = 0x80000000; i != 0; i >>= 1)
1203 T55xxWriteBit(Pwd & i);
1204 }
a739812e 1205 // Send a zero bit separation
e0165dcf 1206 T55xxWriteBit(0);
ac2df346 1207
1d0ccbe0 1208 // Send Block number (if direct access mode)
1209 if (!RegReadMode)
e16054a4 1210 for (i = 0x04; i != 0; i >>= 1)
e0165dcf 1211 T55xxWriteBit(Block & i);
e0165dcf 1212
ac2df346 1213 // Turn field on to read the response
a739812e 1214 TurnReadLFOn(READ_GAP);
ac2df346 1215
1216 // Acquisition
94422fa2 1217 doT55x7Acquisition(12000);
ac2df346 1218
1d0ccbe0 1219 // Turn the field off
1220 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
e0165dcf 1221 cmd_send(CMD_ACK,0,0,0,0,0);
e16054a4 1222 LED_A_OFF();
9276e859 1223}
1224
1225void T55xxWakeUp(uint32_t Pwd){
1226 LED_B_ON();
1227 uint32_t i = 0;
1228
1229 // Set up FPGA, 125kHz
1230 LFSetupFPGAForADC(95, true);
1231
1232 // Trigger T55x7 Direct Access Mode
1233 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1234 SpinDelayUs(START_GAP);
1235
1236 // Opcode 10
1237 T55xxWriteBit(1);
1238 T55xxWriteBit(0); //Page 0
1239
1240 // Send Pwd
1241 for (i = 0x80000000; i != 0; i >>= 1)
1242 T55xxWriteBit(Pwd & i);
1243
1d0ccbe0 1244 // Turn and leave field on to let the begin repeating transmission
1c8fbeb9 1245 TurnReadLFOn(20*1000);
e09f21fa 1246}
1247
1248/*-------------- Cloning routines -----------*/
1d0ccbe0 1249
1250void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1251 // write last block first and config block last (if included)
70459879 1252 for (uint8_t i = numblocks+startblock; i > startblock; i--)
8ce3e4b4 1253 T55xxWriteBlockExt(blockdata[i-1], i-1, 0, 0);
1d0ccbe0 1254}
1255
e09f21fa 1256// Copy HID id to card and setup block 0 config
1d0ccbe0 1257void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1258 uint32_t data[] = {0,0,0,0,0,0,0};
1d0ccbe0 1259 uint8_t last_block = 0;
e0165dcf 1260
1261 if (longFMT){
1262 // Ensure no more than 84 bits supplied
614da335 1263 if (hi2 > 0xFFFFF) {
e0165dcf 1264 DbpString("Tags can only have 84 bits.");
1265 return;
1266 }
1267 // Build the 6 data blocks for supplied 84bit ID
1268 last_block = 6;
1d0ccbe0 1269 // load preamble (1D) & long format identifier (9E manchester encoded)
94422fa2 1270 data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
1d0ccbe0 1271 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1272 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1273 data[3] = manchesterEncode2Bytes(hi >> 16);
1274 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1275 data[5] = manchesterEncode2Bytes(lo >> 16);
1276 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1277 } else {
e0165dcf 1278 // Ensure no more than 44 bits supplied
614da335 1279 if (hi > 0xFFF) {
e0165dcf 1280 DbpString("Tags can only have 44 bits.");
1281 return;
1282 }
e0165dcf 1283 // Build the 3 data blocks for supplied 44bit ID
1284 last_block = 3;
1d0ccbe0 1285 // load preamble
94422fa2 1286 data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
1d0ccbe0 1287 data[2] = manchesterEncode2Bytes(lo >> 16);
1288 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
e0165dcf 1289 }
1d0ccbe0 1290 // load chip config block
1291 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
e0165dcf 1292
edaf10af 1293 //TODO add selection of chip for Q5 or T55x7
1294 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1295
e0165dcf 1296 LED_D_ON();
1297 // Program the data blocks for supplied ID
1298 // and the block 0 for HID format
1d0ccbe0 1299 WriteT55xx(data, 0, last_block+1);
e0165dcf 1300
1301 LED_D_OFF();
1302
1303 DbpString("DONE!");
e09f21fa 1304}
1305
94422fa2 1306void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
1d0ccbe0 1307 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
edaf10af 1308 //TODO add selection of chip for Q5 or T55x7
1309 // data[0] = (((64-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
e09f21fa 1310
e0165dcf 1311 LED_D_ON();
1312 // Program the data blocks for supplied ID
1d0ccbe0 1313 // and the block 0 config
1314 WriteT55xx(data, 0, 3);
e09f21fa 1315
e0165dcf 1316 LED_D_OFF();
e09f21fa 1317
e0165dcf 1318 DbpString("DONE!");
e09f21fa 1319}
1320
1d0ccbe0 1321// Clone Indala 64-bit tag by UID to T55x7
1322void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1323 //Program the 2 data blocks for supplied 64bit UID
1324 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1325 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
edaf10af 1326 //TODO add selection of chip for Q5 or T55x7
1327 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1328
1d0ccbe0 1329 WriteT55xx(data, 0, 3);
1330 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1331 // T5567WriteBlock(0x603E1042,0);
1332 DbpString("DONE!");
1333}
1334// Clone Indala 224-bit tag by UID to T55x7
94422fa2 1335void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
1d0ccbe0 1336 //Program the 7 data blocks for supplied 224bit UID
1337 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1338 // and the block 0 for Indala224 format
1339 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1340 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
edaf10af 1341 //TODO add selection of chip for Q5 or T55x7
1342 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
1d0ccbe0 1343 WriteT55xx(data, 0, 8);
1344 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1345 // T5567WriteBlock(0x603E10E2,0);
1346 DbpString("DONE!");
1347}
a126332a 1348// clone viking tag to T55xx
1349void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
1350 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
1351 if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
1352 // Program the data blocks for supplied ID and the block 0 config
1353 WriteT55xx(data, 0, 3);
1354 LED_D_OFF();
1355 cmd_send(CMD_ACK,0,0,0,0,0);
1356}
1d0ccbe0 1357
e09f21fa 1358// Define 9bit header for EM410x tags
1359#define EM410X_HEADER 0x1FF
1360#define EM410X_ID_LENGTH 40
1361
94422fa2 1362void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
e0165dcf 1363 int i, id_bit;
1364 uint64_t id = EM410X_HEADER;
1365 uint64_t rev_id = 0; // reversed ID
1366 int c_parity[4]; // column parity
1367 int r_parity = 0; // row parity
1368 uint32_t clock = 0;
1369
1370 // Reverse ID bits given as parameter (for simpler operations)
1371 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1372 if (i < 32) {
1373 rev_id = (rev_id << 1) | (id_lo & 1);
1374 id_lo >>= 1;
1375 } else {
1376 rev_id = (rev_id << 1) | (id_hi & 1);
1377 id_hi >>= 1;
1378 }
1379 }
1380
1381 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1382 id_bit = rev_id & 1;
1383
1384 if (i % 4 == 0) {
1385 // Don't write row parity bit at start of parsing
1386 if (i)
1387 id = (id << 1) | r_parity;
1388 // Start counting parity for new row
1389 r_parity = id_bit;
1390 } else {
1391 // Count row parity
1392 r_parity ^= id_bit;
1393 }
1394
1395 // First elements in column?
1396 if (i < 4)
1397 // Fill out first elements
1398 c_parity[i] = id_bit;
1399 else
1400 // Count column parity
1401 c_parity[i % 4] ^= id_bit;
1402
1403 // Insert ID bit
1404 id = (id << 1) | id_bit;
1405 rev_id >>= 1;
1406 }
1407
1408 // Insert parity bit of last row
1409 id = (id << 1) | r_parity;
1410
1411 // Fill out column parity at the end of tag
1412 for (i = 0; i < 4; ++i)
1413 id = (id << 1) | c_parity[i];
1414
1415 // Add stop bit
1416 id <<= 1;
1417
1418 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1419 LED_D_ON();
1420
1421 // Write EM410x ID
8ce3e4b4 1422 uint32_t data[] = {0, (uint32_t)(id>>32), id & 0xFFFFFFFF};
edaf10af 1423
8ce3e4b4 1424 clock = (card & 0xFF00) >> 8;
1425 clock = (clock == 0) ? 64 : clock;
1426 Dbprintf("Clock rate: %d", clock);
edaf10af 1427 if (card & 0xFF) { //t55x7
1d0ccbe0 1428 clock = GetT55xxClockBit(clock);
1429 if (clock == 0) {
e0165dcf 1430 Dbprintf("Invalid clock rate: %d", clock);
1431 return;
1432 }
1d0ccbe0 1433 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
edaf10af 1434 } else { //t5555 (Q5)
1435 clock = (clock-2)>>1; //n = (RF-2)/2
1436 data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
e0165dcf 1437 }
1d0ccbe0 1438
1439 WriteT55xx(data, 0, 3);
e0165dcf 1440
1441 LED_D_OFF();
8ce3e4b4 1442 Dbprintf("Tag %s written with 0x%08x%08x\n",
1443 card ? "T55x7":"T5555",
1444 (uint32_t)(id >> 32),
1445 (uint32_t)id);
e09f21fa 1446}
1447
e09f21fa 1448//-----------------------------------
1449// EM4469 / EM4305 routines
1450//-----------------------------------
1451#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1452#define FWD_CMD_WRITE 0xA
1453#define FWD_CMD_READ 0x9
1454#define FWD_CMD_DISABLE 0x5
1455
e09f21fa 1456uint8_t forwardLink_data[64]; //array of forwarded bits
1457uint8_t * forward_ptr; //ptr for forward message preparation
1458uint8_t fwd_bit_sz; //forwardlink bit counter
1459uint8_t * fwd_write_ptr; //forwardlink bit pointer
1460
1461//====================================================================
1462// prepares command bits
1463// see EM4469 spec
1464//====================================================================
6426f6ba 1465//--------------------------------------------------------------------
1466// VALUES TAKEN FROM EM4x function: SendForward
1467// START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1468// WRITE_GAP = 128; (16*8)
1469// WRITE_1 = 256 32*8; (32*8)
1470
1471// These timings work for 4469/4269/4305 (with the 55*8 above)
1472// WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1473
e09f21fa 1474uint8_t Prepare_Cmd( uint8_t cmd ) {
e09f21fa 1475
e0165dcf 1476 *forward_ptr++ = 0; //start bit
1477 *forward_ptr++ = 0; //second pause for 4050 code
e09f21fa 1478
e0165dcf 1479 *forward_ptr++ = cmd;
1480 cmd >>= 1;
1481 *forward_ptr++ = cmd;
1482 cmd >>= 1;
1483 *forward_ptr++ = cmd;
1484 cmd >>= 1;
1485 *forward_ptr++ = cmd;
e09f21fa 1486
e0165dcf 1487 return 6; //return number of emited bits
e09f21fa 1488}
1489
1490//====================================================================
1491// prepares address bits
1492// see EM4469 spec
1493//====================================================================
e09f21fa 1494uint8_t Prepare_Addr( uint8_t addr ) {
e09f21fa 1495
e0165dcf 1496 register uint8_t line_parity;
e09f21fa 1497
e0165dcf 1498 uint8_t i;
1499 line_parity = 0;
1500 for(i=0;i<6;i++) {
1501 *forward_ptr++ = addr;
1502 line_parity ^= addr;
1503 addr >>= 1;
1504 }
e09f21fa 1505
e0165dcf 1506 *forward_ptr++ = (line_parity & 1);
e09f21fa 1507
e0165dcf 1508 return 7; //return number of emited bits
e09f21fa 1509}
1510
1511//====================================================================
1512// prepares data bits intreleaved with parity bits
1513// see EM4469 spec
1514//====================================================================
e09f21fa 1515uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
e0165dcf 1516
1517 register uint8_t line_parity;
1518 register uint8_t column_parity;
1519 register uint8_t i, j;
1520 register uint16_t data;
1521
1522 data = data_low;
1523 column_parity = 0;
1524
1525 for(i=0; i<4; i++) {
1526 line_parity = 0;
1527 for(j=0; j<8; j++) {
1528 line_parity ^= data;
1529 column_parity ^= (data & 1) << j;
1530 *forward_ptr++ = data;
1531 data >>= 1;
1532 }
1533 *forward_ptr++ = line_parity;
1534 if(i == 1)
1535 data = data_hi;
1536 }
1537
1538 for(j=0; j<8; j++) {
1539 *forward_ptr++ = column_parity;
1540 column_parity >>= 1;
1541 }
1542 *forward_ptr = 0;
1543
1544 return 45; //return number of emited bits
e09f21fa 1545}
1546
1547//====================================================================
1548// Forward Link send function
1549// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1550// fwd_bit_count set with number of bits to be sent
1551//====================================================================
1552void SendForward(uint8_t fwd_bit_count) {
1553
e0165dcf 1554 fwd_write_ptr = forwardLink_data;
1555 fwd_bit_sz = fwd_bit_count;
1556
1557 LED_D_ON();
1558
6a09bea4 1559 // Set up FPGA, 125kHz
1560 LFSetupFPGAForADC(95, true);
1561
e0165dcf 1562 // force 1st mod pulse (start gap must be longer for 4305)
1563 fwd_bit_sz--; //prepare next bit modulation
1564 fwd_write_ptr++;
1565 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1566 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
e0165dcf 1567 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1568 SpinDelayUs(16*8); //16 cycles on (8us each)
1569
1570 // now start writting
1571 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1572 if(((*fwd_write_ptr++) & 1) == 1)
1573 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1574 else {
1575 //These timings work for 4469/4269/4305 (with the 55*8 above)
1576 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1577 SpinDelayUs(23*8); //16-4 cycles off (8us each)
e0165dcf 1578 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1579 SpinDelayUs(9*8); //16 cycles on (8us each)
1580 }
1581 }
e09f21fa 1582}
1583
1584void EM4xLogin(uint32_t Password) {
1585
e0165dcf 1586 uint8_t fwd_bit_count;
e09f21fa 1587
e0165dcf 1588 forward_ptr = forwardLink_data;
1589 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1590 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
e09f21fa 1591
e0165dcf 1592 SendForward(fwd_bit_count);
e09f21fa 1593
e0165dcf 1594 //Wait for command to complete
1595 SpinDelay(20);
e09f21fa 1596}
1597
1598void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1599
a739812e 1600 uint8_t fwd_bit_count;
e0165dcf 1601 uint8_t *dest = BigBuf_get_addr();
a739812e 1602 uint16_t bufsize = BigBuf_max_traceLen();
b8f705e7 1603 uint32_t i = 0;
1604
a739812e 1605 //clear buffer now so it does not interfere with timing later
1606 BigBuf_Clear_ext(false);
b8f705e7 1607
e0165dcf 1608 //If password mode do login
1609 if (PwdMode == 1) EM4xLogin(Pwd);
1610
1611 forward_ptr = forwardLink_data;
1612 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1613 fwd_bit_count += Prepare_Addr( Address );
1614
e0165dcf 1615 // Connect the A/D to the peak-detected low-frequency path.
1616 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1617 // Now set up the SSC to get the ADC samples that are now streaming at us.
1618 FpgaSetupSsc();
1619
1620 SendForward(fwd_bit_count);
1621
1622 // Now do the acquisition
1623 i = 0;
1624 for(;;) {
1625 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1626 AT91C_BASE_SSC->SSC_THR = 0x43;
1627 }
1628 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1629 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
b8f705e7 1630 ++i;
a739812e 1631 if (i >= bufsize) break;
e0165dcf 1632 }
1633 }
6a09bea4 1634
1635 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
b8f705e7 1636 cmd_send(CMD_ACK,0,0,0,0,0);
e0165dcf 1637 LED_D_OFF();
e09f21fa 1638}
1639
1640void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1641
e0165dcf 1642 uint8_t fwd_bit_count;
e09f21fa 1643
e0165dcf 1644 //If password mode do login
1645 if (PwdMode == 1) EM4xLogin(Pwd);
e09f21fa 1646
e0165dcf 1647 forward_ptr = forwardLink_data;
1648 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1649 fwd_bit_count += Prepare_Addr( Address );
1650 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
e09f21fa 1651
e0165dcf 1652 SendForward(fwd_bit_count);
e09f21fa 1653
e0165dcf 1654 //Wait for write to complete
1655 SpinDelay(20);
1656 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1657 LED_D_OFF();
e09f21fa 1658}
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