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@Marshmellow42 's cleanup isn device-side "hf mfu" code. Looks nice. Dump uses...
[proxmark3-svn] / armsrc / lfops.c
CommitLineData
e09f21fa 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
9//-----------------------------------------------------------------------------
10
11#include "proxmark3.h"
12#include "apps.h"
13#include "util.h"
14#include "hitag2.h"
15#include "crc16.h"
16#include "string.h"
17#include "lfdemod.h"
18#include "lfsampling.h"
f7048dc8 19#include "usb_cdc.h"
e09f21fa 20
21
22/**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
30{
31
e0165dcf 32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
e09f21fa 34
e0165dcf 35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
e09f21fa 37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
e0165dcf 51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
e09f21fa 56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
e0165dcf 58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
e09f21fa 68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
e0165dcf 70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
e09f21fa 71
e0165dcf 72 // now do the read
e09f21fa 73 DoAcquisition_config(false);
74}
75
76
77
78/* blank r/w tag data stream
79...0000000000000000 01111111
801010101010101010101010101010101010101010101010101010101010101010
810011010010100001
8201111111
83101010101010101[0]000...
84
85[5555fe852c5555555555555555fe0000]
86*/
87void ReadTItag(void)
88{
e0165dcf 89 // some hardcoded initial params
90 // when we read a TI tag we sample the zerocross line at 2Mhz
91 // TI tags modulate a 1 as 16 cycles of 123.2Khz
92 // TI tags modulate a 0 as 16 cycles of 134.2Khz
e09f21fa 93 #define FSAMPLE 2000000
94 #define FREQLO 123200
95 #define FREQHI 134200
96
e0165dcf 97 signed char *dest = (signed char *)BigBuf_get_addr();
98 uint16_t n = BigBuf_max_traceLen();
99 // 128 bit shift register [shift3:shift2:shift1:shift0]
100 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
101
102 int i, cycles=0, samples=0;
103 // how many sample points fit in 16 cycles of each frequency
104 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
105 // when to tell if we're close enough to one freq or another
106 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
107
108 // TI tags charge at 134.2Khz
109 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
111
112 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
113 // connects to SSP_DIN and the SSP_DOUT logic level controls
114 // whether we're modulating the antenna (high)
115 // or listening to the antenna (low)
116 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
117
118 // get TI tag data into the buffer
119 AcquireTiType();
120
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
122
123 for (i=0; i<n-1; i++) {
124 // count cycles by looking for lo to hi zero crossings
125 if ( (dest[i]<0) && (dest[i+1]>0) ) {
126 cycles++;
127 // after 16 cycles, measure the frequency
128 if (cycles>15) {
129 cycles=0;
130 samples=i-samples; // number of samples in these 16 cycles
131
132 // TI bits are coming to us lsb first so shift them
133 // right through our 128 bit right shift register
134 shift0 = (shift0>>1) | (shift1 << 31);
135 shift1 = (shift1>>1) | (shift2 << 31);
136 shift2 = (shift2>>1) | (shift3 << 31);
137 shift3 >>= 1;
138
139 // check if the cycles fall close to the number
140 // expected for either the low or high frequency
141 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
142 // low frequency represents a 1
143 shift3 |= (1<<31);
144 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
145 // high frequency represents a 0
146 } else {
147 // probably detected a gay waveform or noise
148 // use this as gaydar or discard shift register and start again
149 shift3 = shift2 = shift1 = shift0 = 0;
150 }
151 samples = i;
152
153 // for each bit we receive, test if we've detected a valid tag
154
155 // if we see 17 zeroes followed by 6 ones, we might have a tag
156 // remember the bits are backwards
157 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
158 // if start and end bytes match, we have a tag so break out of the loop
159 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
160 cycles = 0xF0B; //use this as a flag (ugly but whatever)
161 break;
162 }
163 }
164 }
165 }
166 }
167
168 // if flag is set we have a tag
169 if (cycles!=0xF0B) {
170 DbpString("Info: No valid tag detected.");
171 } else {
172 // put 64 bit data into shift1 and shift0
173 shift0 = (shift0>>24) | (shift1 << 8);
174 shift1 = (shift1>>24) | (shift2 << 8);
175
176 // align 16 bit crc into lower half of shift2
177 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
178
179 // if r/w tag, check ident match
e09f21fa 180 if (shift3 & (1<<15) ) {
e0165dcf 181 DbpString("Info: TI tag is rewriteable");
182 // only 15 bits compare, last bit of ident is not valid
e09f21fa 183 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
e0165dcf 184 DbpString("Error: Ident mismatch!");
185 } else {
186 DbpString("Info: TI tag ident is valid");
187 }
188 } else {
189 DbpString("Info: TI tag is readonly");
190 }
191
192 // WARNING the order of the bytes in which we calc crc below needs checking
193 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
194 // bytes in reverse or something
195 // calculate CRC
196 uint32_t crc=0;
197
198 crc = update_crc16(crc, (shift0)&0xff);
199 crc = update_crc16(crc, (shift0>>8)&0xff);
200 crc = update_crc16(crc, (shift0>>16)&0xff);
201 crc = update_crc16(crc, (shift0>>24)&0xff);
202 crc = update_crc16(crc, (shift1)&0xff);
203 crc = update_crc16(crc, (shift1>>8)&0xff);
204 crc = update_crc16(crc, (shift1>>16)&0xff);
205 crc = update_crc16(crc, (shift1>>24)&0xff);
206
207 Dbprintf("Info: Tag data: %x%08x, crc=%x",
208 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
209 if (crc != (shift2&0xffff)) {
210 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
211 } else {
212 DbpString("Info: CRC is good");
213 }
214 }
e09f21fa 215}
216
217void WriteTIbyte(uint8_t b)
218{
e0165dcf 219 int i = 0;
220
221 // modulate 8 bits out to the antenna
222 for (i=0; i<8; i++)
223 {
224 if (b&(1<<i)) {
225 // stop modulating antenna
226 LOW(GPIO_SSC_DOUT);
227 SpinDelayUs(1000);
228 // modulate antenna
229 HIGH(GPIO_SSC_DOUT);
230 SpinDelayUs(1000);
231 } else {
232 // stop modulating antenna
233 LOW(GPIO_SSC_DOUT);
234 SpinDelayUs(300);
235 // modulate antenna
236 HIGH(GPIO_SSC_DOUT);
237 SpinDelayUs(1700);
238 }
239 }
e09f21fa 240}
241
242void AcquireTiType(void)
243{
e0165dcf 244 int i, j, n;
245 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
246 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
e09f21fa 247 #define TIBUFLEN 1250
248
e0165dcf 249 // clear buffer
e09f21fa 250 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
e0165dcf 251 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
252
253 // Set up the synchronous serial port
254 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
255 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
256
257 // steal this pin from the SSP and use it to control the modulation
258 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
259 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
260
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
262 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
263
264 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
265 // 48/2 = 24 MHz clock must be divided by 12
266 AT91C_BASE_SSC->SSC_CMR = 12;
267
268 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
269 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
270 AT91C_BASE_SSC->SSC_TCMR = 0;
271 AT91C_BASE_SSC->SSC_TFMR = 0;
272
273 LED_D_ON();
274
275 // modulate antenna
276 HIGH(GPIO_SSC_DOUT);
277
278 // Charge TI tag for 50ms.
279 SpinDelay(50);
280
281 // stop modulating antenna and listen
282 LOW(GPIO_SSC_DOUT);
283
284 LED_D_OFF();
285
286 i = 0;
287 for(;;) {
288 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
289 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
290 i++; if(i >= TIBUFLEN) break;
291 }
292 WDT_HIT();
293 }
294
295 // return stolen pin to SSP
296 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
297 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
298
299 char *dest = (char *)BigBuf_get_addr();
300 n = TIBUFLEN*32;
301 // unpack buffer
302 for (i=TIBUFLEN-1; i>=0; i--) {
303 for (j=0; j<32; j++) {
304 if(BigBuf[i] & (1 << j)) {
305 dest[--n] = 1;
306 } else {
307 dest[--n] = -1;
308 }
309 }
310 }
e09f21fa 311}
312
313// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
314// if crc provided, it will be written with the data verbatim (even if bogus)
315// if not provided a valid crc will be computed from the data and written.
316void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
317{
e0165dcf 318 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
319 if(crc == 0) {
320 crc = update_crc16(crc, (idlo)&0xff);
321 crc = update_crc16(crc, (idlo>>8)&0xff);
322 crc = update_crc16(crc, (idlo>>16)&0xff);
323 crc = update_crc16(crc, (idlo>>24)&0xff);
324 crc = update_crc16(crc, (idhi)&0xff);
325 crc = update_crc16(crc, (idhi>>8)&0xff);
326 crc = update_crc16(crc, (idhi>>16)&0xff);
327 crc = update_crc16(crc, (idhi>>24)&0xff);
328 }
329 Dbprintf("Writing to tag: %x%08x, crc=%x",
330 (unsigned int) idhi, (unsigned int) idlo, crc);
331
332 // TI tags charge at 134.2Khz
333 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
334 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
335 // connects to SSP_DIN and the SSP_DOUT logic level controls
336 // whether we're modulating the antenna (high)
337 // or listening to the antenna (low)
338 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
339 LED_A_ON();
340
341 // steal this pin from the SSP and use it to control the modulation
342 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344
345 // writing algorithm:
346 // a high bit consists of a field off for 1ms and field on for 1ms
347 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
348 // initiate a charge time of 50ms (field on) then immediately start writing bits
349 // start by writing 0xBB (keyword) and 0xEB (password)
350 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
351 // finally end with 0x0300 (write frame)
352 // all data is sent lsb firts
353 // finish with 15ms programming time
354
355 // modulate antenna
356 HIGH(GPIO_SSC_DOUT);
357 SpinDelay(50); // charge time
358
359 WriteTIbyte(0xbb); // keyword
360 WriteTIbyte(0xeb); // password
361 WriteTIbyte( (idlo )&0xff );
362 WriteTIbyte( (idlo>>8 )&0xff );
363 WriteTIbyte( (idlo>>16)&0xff );
364 WriteTIbyte( (idlo>>24)&0xff );
365 WriteTIbyte( (idhi )&0xff );
366 WriteTIbyte( (idhi>>8 )&0xff );
367 WriteTIbyte( (idhi>>16)&0xff );
368 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
369 WriteTIbyte( (crc )&0xff ); // crc lo
370 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
371 WriteTIbyte(0x00); // write frame lo
372 WriteTIbyte(0x03); // write frame hi
373 HIGH(GPIO_SSC_DOUT);
374 SpinDelay(50); // programming time
375
376 LED_A_OFF();
377
378 // get TI tag data into the buffer
379 AcquireTiType();
380
381 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
b8f705e7 382 DbpString("Now use 'lf ti read' to check");
e09f21fa 383}
384
cd073027 385void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
e09f21fa 386{
e0165dcf 387 int i;
388 uint8_t *tab = BigBuf_get_addr();
e09f21fa 389
e0165dcf 390 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
391 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
e09f21fa 392
e0165dcf 393 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
e09f21fa 394
e0165dcf 395 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
396 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
e09f21fa 397
398 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
399 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
400
e0165dcf 401 i = 0;
402 for(;;) {
403 //wait until SSC_CLK goes HIGH
404 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
f7048dc8 405 if(BUTTON_PRESS() || usb_poll()) {
e0165dcf 406 DbpString("Stopped");
407 return;
408 }
409 WDT_HIT();
410 }
411 if (ledcontrol)
412 LED_D_ON();
413
414 if(tab[i])
415 OPEN_COIL();
416 else
417 SHORT_COIL();
418
419 if (ledcontrol)
420 LED_D_OFF();
421 //wait until SSC_CLK goes LOW
422 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
423 if(BUTTON_PRESS()) {
424 DbpString("Stopped");
425 return;
426 }
427 WDT_HIT();
428 }
429
430 i++;
431 if(i == period) {
432
433 i = 0;
434 if (gap) {
435 SHORT_COIL();
436 SpinDelayUs(gap);
437 }
438 }
439 }
e09f21fa 440}
441
e09f21fa 442#define DEBUG_FRAME_CONTENTS 1
443void SimulateTagLowFrequencyBidir(int divisor, int t0)
444{
445}
446
447// compose fc/8 fc/10 waveform (FSK2)
448static void fc(int c, int *n)
449{
e0165dcf 450 uint8_t *dest = BigBuf_get_addr();
451 int idx;
452
453 // for when we want an fc8 pattern every 4 logical bits
454 if(c==0) {
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=1;
458 dest[((*n)++)]=1;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 dest[((*n)++)]=0;
462 dest[((*n)++)]=0;
463 }
464
465 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
466 if(c==8) {
467 for (idx=0; idx<6; idx++) {
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=1;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 dest[((*n)++)]=0;
475 dest[((*n)++)]=0;
476 }
477 }
478
479 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
480 if(c==10) {
481 for (idx=0; idx<5; idx++) {
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=1;
486 dest[((*n)++)]=1;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 dest[((*n)++)]=0;
491 dest[((*n)++)]=0;
492 }
493 }
e09f21fa 494}
495// compose fc/X fc/Y waveform (FSKx)
712ebfa6 496static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
e09f21fa 497{
e0165dcf 498 uint8_t *dest = BigBuf_get_addr();
499 uint8_t halfFC = fc/2;
500 uint8_t wavesPerClock = clock/fc;
501 uint8_t mod = clock % fc; //modifier
502 uint8_t modAdj = fc/mod; //how often to apply modifier
503 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
504 // loop through clock - step field clock
505 for (uint8_t idx=0; idx < wavesPerClock; idx++){
506 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
507 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
508 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
509 *n += fc;
510 }
511 if (mod>0) (*modCnt)++;
512 if ((mod>0) && modAdjOk){ //fsk2
513 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
514 memset(dest+(*n), 0, fc-halfFC);
515 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
516 *n += fc;
517 }
518 }
519 if (mod>0 && !modAdjOk){ //fsk1
520 memset(dest+(*n), 0, mod-(mod/2));
521 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
522 *n += mod;
523 }
e09f21fa 524}
525
526// prepare a waveform pattern in the buffer based on the ID given then
527// simulate a HID tag until the button is pressed
528void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
529{
e0165dcf 530 int n=0, i=0;
531 /*
532 HID tag bitstream format
533 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
534 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
535 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
536 A fc8 is inserted before every 4 bits
537 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
538 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
539 */
540
541 if (hi>0xFFF) {
542 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
543 return;
544 }
545 fc(0,&n);
546 // special start of frame marker containing invalid bit sequences
547 fc(8, &n); fc(8, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549 fc(10, &n); fc(10, &n); // invalid
550 fc(8, &n); fc(10, &n); // logical 0
551
552 WDT_HIT();
553 // manchester encode bits 43 to 32
554 for (i=11; i>=0; i--) {
555 if ((i%4)==3) fc(0,&n);
556 if ((hi>>i)&1) {
557 fc(10, &n); fc(8, &n); // low-high transition
558 } else {
559 fc(8, &n); fc(10, &n); // high-low transition
560 }
561 }
562
563 WDT_HIT();
564 // manchester encode bits 31 to 0
565 for (i=31; i>=0; i--) {
566 if ((i%4)==3) fc(0,&n);
567 if ((lo>>i)&1) {
568 fc(10, &n); fc(8, &n); // low-high transition
569 } else {
570 fc(8, &n); fc(10, &n); // high-low transition
571 }
572 }
573
574 if (ledcontrol)
575 LED_A_ON();
576 SimulateTagLowFrequency(n, 0, ledcontrol);
577
578 if (ledcontrol)
579 LED_A_OFF();
e09f21fa 580}
581
582// prepare a waveform pattern in the buffer based on the ID given then
583// simulate a FSK tag until the button is pressed
584// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
585void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
586{
e0165dcf 587 int ledcontrol=1;
588 int n=0, i=0;
589 uint8_t fcHigh = arg1 >> 8;
590 uint8_t fcLow = arg1 & 0xFF;
591 uint16_t modCnt = 0;
592 uint8_t clk = arg2 & 0xFF;
593 uint8_t invert = (arg2 >> 8) & 1;
594
595 for (i=0; i<size; i++){
596 if (BitStream[i] == invert){
597 fcAll(fcLow, &n, clk, &modCnt);
598 } else {
599 fcAll(fcHigh, &n, clk, &modCnt);
600 }
601 }
602 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
603 /*Dbprintf("DEBUG: First 32:");
604 uint8_t *dest = BigBuf_get_addr();
605 i=0;
606 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
607 i+=16;
608 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
609 */
610 if (ledcontrol)
611 LED_A_ON();
612
613 SimulateTagLowFrequency(n, 0, ledcontrol);
614
615 if (ledcontrol)
616 LED_A_OFF();
e09f21fa 617}
618
619// compose ask waveform for one bit(ASK)
e0165dcf 620static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
e09f21fa 621{
e0165dcf 622 uint8_t *dest = BigBuf_get_addr();
623 uint8_t halfClk = clock/2;
624 // c = current bit 1 or 0
625 if (manchester==1){
626 memset(dest+(*n), c, halfClk);
627 memset(dest+(*n) + halfClk, c^1, halfClk);
628 } else {
629 memset(dest+(*n), c, clock);
630 }
631 *n += clock;
e09f21fa 632}
633
b41534d1 634static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
635{
e0165dcf 636 uint8_t *dest = BigBuf_get_addr();
637 uint8_t halfClk = clock/2;
638 if (c){
639 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
640 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
641 } else {
642 memset(dest+(*n), c ^ *phase, clock);
643 *phase ^= 1;
644 }
b41534d1 645
646}
647
e09f21fa 648// args clock, ask/man or askraw, invert, transmission separator
649void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
650{
e0165dcf 651 int ledcontrol = 1;
652 int n=0, i=0;
653 uint8_t clk = (arg1 >> 8) & 0xFF;
654 uint8_t encoding = arg1 & 1;
655 uint8_t separator = arg2 & 1;
656 uint8_t invert = (arg2 >> 8) & 1;
657
658 if (encoding==2){ //biphase
659 uint8_t phase=0;
660 for (i=0; i<size; i++){
661 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
662 }
663 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
664 for (i=0; i<size; i++){
665 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
666 }
667 }
668 } else { // ask/manchester || ask/raw
669 for (i=0; i<size; i++){
670 askSimBit(BitStream[i]^invert, &n, clk, encoding);
671 }
672 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
673 for (i=0; i<size; i++){
674 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
675 }
676 }
677 }
678
679 if (separator==1) Dbprintf("sorry but separator option not yet available");
680
681 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
682 //DEBUG
683 //Dbprintf("First 32:");
684 //uint8_t *dest = BigBuf_get_addr();
685 //i=0;
686 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
687 //i+=16;
688 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
689
690 if (ledcontrol)
691 LED_A_ON();
692
693 SimulateTagLowFrequency(n, 0, ledcontrol);
694
695 if (ledcontrol)
696 LED_A_OFF();
e09f21fa 697}
698
699//carrier can be 2,4 or 8
700static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
701{
e0165dcf 702 uint8_t *dest = BigBuf_get_addr();
703 uint8_t halfWave = waveLen/2;
704 //uint8_t idx;
705 int i = 0;
706 if (phaseChg){
707 // write phase change
708 memset(dest+(*n), *curPhase^1, halfWave);
709 memset(dest+(*n) + halfWave, *curPhase, halfWave);
710 *n += waveLen;
711 *curPhase ^= 1;
712 i += waveLen;
713 }
714 //write each normal clock wave for the clock duration
715 for (; i < clk; i+=waveLen){
716 memset(dest+(*n), *curPhase, halfWave);
717 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
718 *n += waveLen;
719 }
e09f21fa 720}
721
722// args clock, carrier, invert,
723void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
724{
e0165dcf 725 int ledcontrol=1;
726 int n=0, i=0;
727 uint8_t clk = arg1 >> 8;
728 uint8_t carrier = arg1 & 0xFF;
729 uint8_t invert = arg2 & 0xFF;
730 uint8_t curPhase = 0;
731 for (i=0; i<size; i++){
732 if (BitStream[i] == curPhase){
733 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
734 } else {
735 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
736 }
737 }
738 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
739 //Dbprintf("DEBUG: First 32:");
740 //uint8_t *dest = BigBuf_get_addr();
741 //i=0;
742 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
743 //i+=16;
744 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
745
746 if (ledcontrol)
747 LED_A_ON();
748 SimulateTagLowFrequency(n, 0, ledcontrol);
749
750 if (ledcontrol)
751 LED_A_OFF();
e09f21fa 752}
753
754// loop to get raw HID waveform then FSK demodulate the TAG ID from it
755void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
756{
e0165dcf 757 uint8_t *dest = BigBuf_get_addr();
b8f705e7 758 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
e0165dcf 759 size_t size = 0;
760 uint32_t hi2=0, hi=0, lo=0;
761 int idx=0;
762 // Configure to go in 125Khz listen mode
763 LFSetupFPGAForADC(95, true);
e09f21fa 764
e0165dcf 765 while(!BUTTON_PRESS()) {
e09f21fa 766
e0165dcf 767 WDT_HIT();
768 if (ledcontrol) LED_A_ON();
e09f21fa 769
770 DoAcquisition_default(-1,true);
771 // FSK demodulator
b8f705e7 772 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
773 size = 50*128*2; //big enough to catch 2 sequences of largest format
e09f21fa 774 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
e0165dcf 775
b8f705e7 776 if (idx>0 && lo>0 && (size==96 || size==192)){
777 // go over previously decoded manchester data and decode into usable tag ID
778 if (hi2 != 0){ //extra large HID tags 88/192 bits
e0165dcf 779 Dbprintf("TAG ID: %x%08x%08x (%d)",
780 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
b8f705e7 781 }else { //standard HID tags 44/96 bits
e0165dcf 782 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
783 uint8_t bitlen = 0;
784 uint32_t fc = 0;
785 uint32_t cardnum = 0;
e09f21fa 786 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
e0165dcf 787 uint32_t lo2=0;
788 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
789 uint8_t idx3 = 1;
e09f21fa 790 while(lo2 > 1){ //find last bit set to 1 (format len bit)
791 lo2=lo2 >> 1;
e0165dcf 792 idx3++;
793 }
e09f21fa 794 bitlen = idx3+19;
e0165dcf 795 fc =0;
796 cardnum=0;
e09f21fa 797 if(bitlen == 26){
e0165dcf 798 cardnum = (lo>>1)&0xFFFF;
799 fc = (lo>>17)&0xFF;
800 }
e09f21fa 801 if(bitlen == 37){
e0165dcf 802 cardnum = (lo>>1)&0x7FFFF;
803 fc = ((hi&0xF)<<12)|(lo>>20);
804 }
e09f21fa 805 if(bitlen == 34){
e0165dcf 806 cardnum = (lo>>1)&0xFFFF;
807 fc= ((hi&1)<<15)|(lo>>17);
808 }
e09f21fa 809 if(bitlen == 35){
e0165dcf 810 cardnum = (lo>>1)&0xFFFFF;
811 fc = ((hi&1)<<11)|(lo>>21);
812 }
813 }
814 else { //if bit 38 is not set then 37 bit format is used
815 bitlen= 37;
816 fc =0;
817 cardnum=0;
818 if(bitlen==37){
819 cardnum = (lo>>1)&0x7FFFF;
820 fc = ((hi&0xF)<<12)|(lo>>20);
821 }
822 }
823 //Dbprintf("TAG ID: %x%08x (%d)",
824 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
825 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
826 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
827 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
828 }
829 if (findone){
830 if (ledcontrol) LED_A_OFF();
831 *high = hi;
832 *low = lo;
833 return;
834 }
835 // reset
e0165dcf 836 }
b8f705e7 837 hi2 = hi = lo = idx = 0;
e0165dcf 838 WDT_HIT();
839 }
840 DbpString("Stopped");
841 if (ledcontrol) LED_A_OFF();
e09f21fa 842}
843
844void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
845{
e0165dcf 846 uint8_t *dest = BigBuf_get_addr();
847
848 size_t size=0, idx=0;
849 int clk=0, invert=0, errCnt=0, maxErr=20;
850 uint32_t hi=0;
851 uint64_t lo=0;
852 // Configure to go in 125Khz listen mode
853 LFSetupFPGAForADC(95, true);
854
855 while(!BUTTON_PRESS()) {
856
857 WDT_HIT();
858 if (ledcontrol) LED_A_ON();
859
860 DoAcquisition_default(-1,true);
861 size = BigBuf_max_traceLen();
e0165dcf 862 //askdemod and manchester decode
b8f705e7 863 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
fef74fdc 864 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
e0165dcf 865 WDT_HIT();
866
b8f705e7 867 if (errCnt<0) continue;
868
e0165dcf 869 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
e0165dcf 870 if (errCnt){
871 if (size>64){
872 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
873 hi,
874 (uint32_t)(lo>>32),
875 (uint32_t)lo,
876 (uint32_t)(lo&0xFFFF),
877 (uint32_t)((lo>>16LL) & 0xFF),
878 (uint32_t)(lo & 0xFFFFFF));
879 } else {
880 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
881 (uint32_t)(lo>>32),
882 (uint32_t)lo,
883 (uint32_t)(lo&0xFFFF),
884 (uint32_t)((lo>>16LL) & 0xFF),
885 (uint32_t)(lo & 0xFFFFFF));
886 }
b8f705e7 887
e0165dcf 888 if (findone){
889 if (ledcontrol) LED_A_OFF();
890 *high=lo>>32;
891 *low=lo & 0xFFFFFFFF;
892 return;
893 }
e0165dcf 894 }
895 WDT_HIT();
b8f705e7 896 hi = lo = size = idx = 0;
897 clk = invert = errCnt = 0;
e0165dcf 898 }
899 DbpString("Stopped");
900 if (ledcontrol) LED_A_OFF();
e09f21fa 901}
902
903void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
904{
e0165dcf 905 uint8_t *dest = BigBuf_get_addr();
906 int idx=0;
907 uint32_t code=0, code2=0;
908 uint8_t version=0;
909 uint8_t facilitycode=0;
910 uint16_t number=0;
b8f705e7 911 uint8_t crc = 0;
912 uint16_t calccrc = 0;
e0165dcf 913 // Configure to go in 125Khz listen mode
914 LFSetupFPGAForADC(95, true);
915
916 while(!BUTTON_PRESS()) {
917 WDT_HIT();
918 if (ledcontrol) LED_A_ON();
e09f21fa 919 DoAcquisition_default(-1,true);
920 //fskdemod and get start index
e0165dcf 921 WDT_HIT();
922 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
b8f705e7 923 if (idx<0) continue;
e0165dcf 924 //valid tag found
925
926 //Index map
927 //0 10 20 30 40 50 60
928 //| | | | | | |
929 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
930 //-----------------------------------------------------------------------------
b8f705e7 931 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
e0165dcf 932 //
b8f705e7 933 //Checksum:
934 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
935 //preamble F0 E0 01 03 B6 75
936 // How to calc checksum,
937 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
938 // F0 + E0 + 01 + 03 + B6 = 28A
939 // 28A & FF = 8A
940 // FF - 8A = 75
941 // Checksum: 0x75
e0165dcf 942 //XSF(version)facility:codeone+codetwo
943 //Handle the data
944 if(findone){ //only print binary if we are doing one
945 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
946 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
947 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
948 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
949 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
950 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
951 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
952 }
953 code = bytebits_to_byte(dest+idx,32);
954 code2 = bytebits_to_byte(dest+idx+32,32);
955 version = bytebits_to_byte(dest+idx+27,8); //14,4
2eec55c8 956 facilitycode = bytebits_to_byte(dest+idx+18,8);
e0165dcf 957 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
958
b8f705e7 959 crc = bytebits_to_byte(dest+idx+54,8);
960 for (uint8_t i=1; i<6; ++i)
961 calccrc += bytebits_to_byte(dest+idx+9*i,8);
962 calccrc &= 0xff;
963 calccrc = 0xff - calccrc;
964
965 char *crcStr = (crc == calccrc) ? "ok":"!crc";
966
967 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
e0165dcf 968 // if we're only looking for one tag
969 if (findone){
970 if (ledcontrol) LED_A_OFF();
971 //LED_A_OFF();
972 *high=code;
973 *low=code2;
974 return;
975 }
976 code=code2=0;
977 version=facilitycode=0;
978 number=0;
979 idx=0;
b8f705e7 980
e0165dcf 981 WDT_HIT();
982 }
983 DbpString("Stopped");
984 if (ledcontrol) LED_A_OFF();
e09f21fa 985}
986
987/*------------------------------
988 * T5555/T5557/T5567 routines
989 *------------------------------
990 */
991
992/* T55x7 configuration register definitions */
993#define T55x7_POR_DELAY 0x00000001
994#define T55x7_ST_TERMINATOR 0x00000008
995#define T55x7_PWD 0x00000010
996#define T55x7_MAXBLOCK_SHIFT 5
997#define T55x7_AOR 0x00000200
998#define T55x7_PSKCF_RF_2 0
999#define T55x7_PSKCF_RF_4 0x00000400
1000#define T55x7_PSKCF_RF_8 0x00000800
1001#define T55x7_MODULATION_DIRECT 0
1002#define T55x7_MODULATION_PSK1 0x00001000
1003#define T55x7_MODULATION_PSK2 0x00002000
1004#define T55x7_MODULATION_PSK3 0x00003000
1005#define T55x7_MODULATION_FSK1 0x00004000
1006#define T55x7_MODULATION_FSK2 0x00005000
1007#define T55x7_MODULATION_FSK1a 0x00006000
1008#define T55x7_MODULATION_FSK2a 0x00007000
1009#define T55x7_MODULATION_MANCHESTER 0x00008000
1010#define T55x7_MODULATION_BIPHASE 0x00010000
1011#define T55x7_BITRATE_RF_8 0
1012#define T55x7_BITRATE_RF_16 0x00040000
1013#define T55x7_BITRATE_RF_32 0x00080000
1014#define T55x7_BITRATE_RF_40 0x000C0000
1015#define T55x7_BITRATE_RF_50 0x00100000
1016#define T55x7_BITRATE_RF_64 0x00140000
1017#define T55x7_BITRATE_RF_100 0x00180000
1018#define T55x7_BITRATE_RF_128 0x001C0000
1019
1020/* T5555 (Q5) configuration register definitions */
1021#define T5555_ST_TERMINATOR 0x00000001
1022#define T5555_MAXBLOCK_SHIFT 0x00000001
1023#define T5555_MODULATION_MANCHESTER 0
1024#define T5555_MODULATION_PSK1 0x00000010
1025#define T5555_MODULATION_PSK2 0x00000020
1026#define T5555_MODULATION_PSK3 0x00000030
1027#define T5555_MODULATION_FSK1 0x00000040
1028#define T5555_MODULATION_FSK2 0x00000050
1029#define T5555_MODULATION_BIPHASE 0x00000060
1030#define T5555_MODULATION_DIRECT 0x00000070
1031#define T5555_INVERT_OUTPUT 0x00000080
1032#define T5555_PSK_RF_2 0
1033#define T5555_PSK_RF_4 0x00000100
1034#define T5555_PSK_RF_8 0x00000200
1035#define T5555_USE_PWD 0x00000400
1036#define T5555_USE_AOR 0x00000800
1037#define T5555_BITRATE_SHIFT 12
1038#define T5555_FAST_WRITE 0x00004000
1039#define T5555_PAGE_SELECT 0x00008000
1040
1041/*
1042 * Relevant times in microsecond
1043 * To compensate antenna falling times shorten the write times
1044 * and enlarge the gap ones.
1045 */
13d77ef9 1046#define START_GAP 50*8 // 10 - 50fc 250
b8f705e7 1047#define WRITE_GAP 20*8 // 8 - 30fc
1048#define WRITE_0 24*8 // 16 - 31fc 24fc 192
1049#define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
1050
1051// VALUES TAKEN FROM EM4x function: SendForward
1052// START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1053// WRITE_GAP = 128; (16*8)
1054// WRITE_1 = 256 32*8; (32*8)
1055
1056// These timings work for 4469/4269/4305 (with the 55*8 above)
1057// WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1058
1059// Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1060// TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1061// Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1062// T0 = TIMER_CLOCK1 / 125000 = 192
1063// 1 Cycle = 8 microseconds(us)
13d77ef9 1064
1065#define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
e09f21fa 1066
1067// Write one bit to card
1068void T55xxWriteBit(int bit)
1069{
e0165dcf 1070 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1071 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1072 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
b8f705e7 1073 if (!bit)
e0165dcf 1074 SpinDelayUs(WRITE_0);
1075 else
1076 SpinDelayUs(WRITE_1);
1077 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1078 SpinDelayUs(WRITE_GAP);
e09f21fa 1079}
1080
1081// Write one card block in page 0, no lock
1082void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1083{
e0165dcf 1084 uint32_t i = 0;
1085
1086 // Set up FPGA, 125kHz
1087 // Wait for config.. (192+8190xPOW)x8 == 67ms
1088 LFSetupFPGAForADC(0, true);
1089
1090 // Now start writting
1091 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1092 SpinDelayUs(START_GAP);
1093
1094 // Opcode
1095 T55xxWriteBit(1);
1096 T55xxWriteBit(0); //Page 0
1097 if (PwdMode == 1){
1098 // Pwd
1099 for (i = 0x80000000; i != 0; i >>= 1)
1100 T55xxWriteBit(Pwd & i);
1101 }
1102 // Lock bit
1103 T55xxWriteBit(0);
1104
1105 // Data
1106 for (i = 0x80000000; i != 0; i >>= 1)
1107 T55xxWriteBit(Data & i);
1108
1109 // Block
1110 for (i = 0x04; i != 0; i >>= 1)
1111 T55xxWriteBit(Block & i);
1112
1113 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1114 // so wait a little more)
1115 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1116 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1117 SpinDelay(20);
1118 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
e09f21fa 1119}
1120
13d77ef9 1121void TurnReadLFOn(){
e0165dcf 1122 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1123 // Give it a bit of time for the resonant antenna to settle.
1124 SpinDelayUs(8*150);
13d77ef9 1125}
1126
1127
e09f21fa 1128// Read one card block in page 0
1129void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1130{
e0165dcf 1131 uint32_t i = 0;
1132 uint8_t *dest = BigBuf_get_addr();
1133 uint16_t bufferlength = BigBuf_max_traceLen();
1134 if ( bufferlength > T55xx_SAMPLES_SIZE )
1135 bufferlength = T55xx_SAMPLES_SIZE;
1136
1137 // Clear destination buffer before sending the command
1138 memset(dest, 0x80, bufferlength);
1139
1140 // Set up FPGA, 125kHz
1141 // Wait for config.. (192+8190xPOW)x8 == 67ms
1142 LFSetupFPGAForADC(0, true);
1143 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1144 SpinDelayUs(START_GAP);
1145
1146 // Opcode
1147 T55xxWriteBit(1);
1148 T55xxWriteBit(0); //Page 0
1149 if (PwdMode == 1){
1150 // Pwd
1151 for (i = 0x80000000; i != 0; i >>= 1)
1152 T55xxWriteBit(Pwd & i);
1153 }
1154 // Lock bit
1155 T55xxWriteBit(0);
1156 // Block
1157 for (i = 0x04; i != 0; i >>= 1)
1158 T55xxWriteBit(Block & i);
1159
1160 // Turn field on to read the response
1161 TurnReadLFOn();
1162 // Now do the acquisition
1163 i = 0;
1164 for(;;) {
1165 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1166 AT91C_BASE_SSC->SSC_THR = 0x43;
1167 LED_D_ON();
1168 }
1169 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1170 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1171 i++;
1172 LED_D_OFF();
1173 if (i >= bufferlength) break;
1174 }
1175 }
1176
1177 cmd_send(CMD_ACK,0,0,0,0,0);
1178 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1179 LED_D_OFF();
e09f21fa 1180}
1181
1182// Read card traceability data (page 1)
1183void T55xxReadTrace(void){
e0165dcf 1184
1185 uint32_t i = 0;
1186 uint8_t *dest = BigBuf_get_addr();
1187 uint16_t bufferlength = BigBuf_max_traceLen();
1188 if ( bufferlength > T55xx_SAMPLES_SIZE )
1189 bufferlength= T55xx_SAMPLES_SIZE;
1190
1191 // Clear destination buffer before sending the command
1192 memset(dest, 0x80, bufferlength);
1193
1194 LFSetupFPGAForADC(0, true);
1195 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1196 SpinDelayUs(START_GAP);
1197
1198 // Opcode
1199 T55xxWriteBit(1);
1200 T55xxWriteBit(1); //Page 1
1201
1202 // Turn field on to read the response
1203 TurnReadLFOn();
1204
1205 // Now do the acquisition
1206 for(;;) {
1207 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1208 AT91C_BASE_SSC->SSC_THR = 0x43;
1209 LED_D_ON();
1210 }
1211 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1212 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1213 i++;
1214 LED_D_OFF();
1215
1216 if (i >= bufferlength) break;
1217 }
1218 }
1219
1220 cmd_send(CMD_ACK,0,0,0,0,0);
1221 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1222 LED_D_OFF();
e09f21fa 1223}
1224
1225/*-------------- Cloning routines -----------*/
1226// Copy HID id to card and setup block 0 config
1227void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1228{
e0165dcf 1229 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1230 int last_block = 0;
1231
1232 if (longFMT){
1233 // Ensure no more than 84 bits supplied
1234 if (hi2>0xFFFFF) {
1235 DbpString("Tags can only have 84 bits.");
1236 return;
1237 }
1238 // Build the 6 data blocks for supplied 84bit ID
1239 last_block = 6;
1240 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1241 for (int i=0;i<4;i++) {
1242 if (hi2 & (1<<(19-i)))
1243 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1244 else
1245 data1 |= (1<<((3-i)*2)); // 0 -> 01
1246 }
1247
1248 data2 = 0;
1249 for (int i=0;i<16;i++) {
1250 if (hi2 & (1<<(15-i)))
1251 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1252 else
1253 data2 |= (1<<((15-i)*2)); // 0 -> 01
1254 }
1255
1256 data3 = 0;
1257 for (int i=0;i<16;i++) {
1258 if (hi & (1<<(31-i)))
1259 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1260 else
1261 data3 |= (1<<((15-i)*2)); // 0 -> 01
1262 }
1263
1264 data4 = 0;
1265 for (int i=0;i<16;i++) {
1266 if (hi & (1<<(15-i)))
1267 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1268 else
1269 data4 |= (1<<((15-i)*2)); // 0 -> 01
1270 }
1271
1272 data5 = 0;
1273 for (int i=0;i<16;i++) {
1274 if (lo & (1<<(31-i)))
1275 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1276 else
1277 data5 |= (1<<((15-i)*2)); // 0 -> 01
1278 }
1279
1280 data6 = 0;
1281 for (int i=0;i<16;i++) {
1282 if (lo & (1<<(15-i)))
1283 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1284 else
1285 data6 |= (1<<((15-i)*2)); // 0 -> 01
1286 }
1287 }
1288 else {
1289 // Ensure no more than 44 bits supplied
1290 if (hi>0xFFF) {
1291 DbpString("Tags can only have 44 bits.");
1292 return;
1293 }
1294
1295 // Build the 3 data blocks for supplied 44bit ID
1296 last_block = 3;
1297
1298 data1 = 0x1D000000; // load preamble
1299
1300 for (int i=0;i<12;i++) {
1301 if (hi & (1<<(11-i)))
1302 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1303 else
1304 data1 |= (1<<((11-i)*2)); // 0 -> 01
1305 }
1306
1307 data2 = 0;
1308 for (int i=0;i<16;i++) {
1309 if (lo & (1<<(31-i)))
1310 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1311 else
1312 data2 |= (1<<((15-i)*2)); // 0 -> 01
1313 }
1314
1315 data3 = 0;
1316 for (int i=0;i<16;i++) {
1317 if (lo & (1<<(15-i)))
1318 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1319 else
1320 data3 |= (1<<((15-i)*2)); // 0 -> 01
1321 }
1322 }
1323
1324 LED_D_ON();
1325 // Program the data blocks for supplied ID
1326 // and the block 0 for HID format
1327 T55xxWriteBlock(data1,1,0,0);
1328 T55xxWriteBlock(data2,2,0,0);
1329 T55xxWriteBlock(data3,3,0,0);
1330
1331 if (longFMT) { // if long format there are 6 blocks
1332 T55xxWriteBlock(data4,4,0,0);
1333 T55xxWriteBlock(data5,5,0,0);
1334 T55xxWriteBlock(data6,6,0,0);
1335 }
1336
1337 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1338 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1339 T55x7_MODULATION_FSK2a |
1340 last_block << T55x7_MAXBLOCK_SHIFT,
1341 0,0,0);
1342
1343 LED_D_OFF();
1344
1345 DbpString("DONE!");
e09f21fa 1346}
1347
1348void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1349{
e0165dcf 1350 int data1=0, data2=0; //up to six blocks for long format
e09f21fa 1351
e0165dcf 1352 data1 = hi; // load preamble
1353 data2 = lo;
e09f21fa 1354
e0165dcf 1355 LED_D_ON();
1356 // Program the data blocks for supplied ID
1357 // and the block 0 for HID format
1358 T55xxWriteBlock(data1,1,0,0);
1359 T55xxWriteBlock(data2,2,0,0);
e09f21fa 1360
e0165dcf 1361 //Config Block
1362 T55xxWriteBlock(0x00147040,0,0,0);
1363 LED_D_OFF();
e09f21fa 1364
e0165dcf 1365 DbpString("DONE!");
e09f21fa 1366}
1367
1368// Define 9bit header for EM410x tags
1369#define EM410X_HEADER 0x1FF
1370#define EM410X_ID_LENGTH 40
1371
1372void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1373{
e0165dcf 1374 int i, id_bit;
1375 uint64_t id = EM410X_HEADER;
1376 uint64_t rev_id = 0; // reversed ID
1377 int c_parity[4]; // column parity
1378 int r_parity = 0; // row parity
1379 uint32_t clock = 0;
1380
1381 // Reverse ID bits given as parameter (for simpler operations)
1382 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1383 if (i < 32) {
1384 rev_id = (rev_id << 1) | (id_lo & 1);
1385 id_lo >>= 1;
1386 } else {
1387 rev_id = (rev_id << 1) | (id_hi & 1);
1388 id_hi >>= 1;
1389 }
1390 }
1391
1392 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1393 id_bit = rev_id & 1;
1394
1395 if (i % 4 == 0) {
1396 // Don't write row parity bit at start of parsing
1397 if (i)
1398 id = (id << 1) | r_parity;
1399 // Start counting parity for new row
1400 r_parity = id_bit;
1401 } else {
1402 // Count row parity
1403 r_parity ^= id_bit;
1404 }
1405
1406 // First elements in column?
1407 if (i < 4)
1408 // Fill out first elements
1409 c_parity[i] = id_bit;
1410 else
1411 // Count column parity
1412 c_parity[i % 4] ^= id_bit;
1413
1414 // Insert ID bit
1415 id = (id << 1) | id_bit;
1416 rev_id >>= 1;
1417 }
1418
1419 // Insert parity bit of last row
1420 id = (id << 1) | r_parity;
1421
1422 // Fill out column parity at the end of tag
1423 for (i = 0; i < 4; ++i)
1424 id = (id << 1) | c_parity[i];
1425
1426 // Add stop bit
1427 id <<= 1;
1428
1429 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1430 LED_D_ON();
1431
1432 // Write EM410x ID
1433 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1434 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1435
1436 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1437 if (card) {
1438 // Clock rate is stored in bits 8-15 of the card value
1439 clock = (card & 0xFF00) >> 8;
1440 Dbprintf("Clock rate: %d", clock);
1441 switch (clock)
1442 {
1443 case 32:
1444 clock = T55x7_BITRATE_RF_32;
1445 break;
1446 case 16:
1447 clock = T55x7_BITRATE_RF_16;
1448 break;
1449 case 0:
1450 // A value of 0 is assumed to be 64 for backwards-compatibility
1451 // Fall through...
1452 case 64:
1453 clock = T55x7_BITRATE_RF_64;
1454 break;
1455 default:
1456 Dbprintf("Invalid clock rate: %d", clock);
1457 return;
1458 }
1459
1460 // Writing configuration for T55x7 tag
1461 T55xxWriteBlock(clock |
1462 T55x7_MODULATION_MANCHESTER |
1463 2 << T55x7_MAXBLOCK_SHIFT,
1464 0, 0, 0);
1465 }
1466 else
1467 // Writing configuration for T5555(Q5) tag
1468 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1469 T5555_MODULATION_MANCHESTER |
1470 2 << T5555_MAXBLOCK_SHIFT,
1471 0, 0, 0);
1472
1473 LED_D_OFF();
1474 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1475 (uint32_t)(id >> 32), (uint32_t)id);
e09f21fa 1476}
1477
1478// Clone Indala 64-bit tag by UID to T55x7
1479void CopyIndala64toT55x7(int hi, int lo)
1480{
1481
e0165dcf 1482 //Program the 2 data blocks for supplied 64bit UID
1483 // and the block 0 for Indala64 format
1484 T55xxWriteBlock(hi,1,0,0);
1485 T55xxWriteBlock(lo,2,0,0);
1486 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1487 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1488 T55x7_MODULATION_PSK1 |
1489 2 << T55x7_MAXBLOCK_SHIFT,
1490 0, 0, 0);
1491 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1492 // T5567WriteBlock(0x603E1042,0);
e09f21fa 1493
e0165dcf 1494 DbpString("DONE!");
e09f21fa 1495
1496}
1497
1498void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1499{
1500
e0165dcf 1501 //Program the 7 data blocks for supplied 224bit UID
1502 // and the block 0 for Indala224 format
1503 T55xxWriteBlock(uid1,1,0,0);
1504 T55xxWriteBlock(uid2,2,0,0);
1505 T55xxWriteBlock(uid3,3,0,0);
1506 T55xxWriteBlock(uid4,4,0,0);
1507 T55xxWriteBlock(uid5,5,0,0);
1508 T55xxWriteBlock(uid6,6,0,0);
1509 T55xxWriteBlock(uid7,7,0,0);
1510 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1511 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1512 T55x7_MODULATION_PSK1 |
1513 7 << T55x7_MAXBLOCK_SHIFT,
1514 0,0,0);
1515 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1516 // T5567WriteBlock(0x603E10E2,0);
1517
1518 DbpString("DONE!");
e09f21fa 1519
1520}
1521
1522
1523#define abs(x) ( ((x)<0) ? -(x) : (x) )
1524#define max(x,y) ( x<y ? y:x)
1525
1526int DemodPCF7931(uint8_t **outBlocks) {
b8f705e7 1527
1528 uint8_t bits[256] = {0x00};
1529 uint8_t blocks[8][16];
1530 uint8_t *dest = BigBuf_get_addr();
1531
e0165dcf 1532 int GraphTraceLen = BigBuf_max_traceLen();
b8f705e7 1533 if ( GraphTraceLen > 18000 )
1534 GraphTraceLen = 18000;
1535
1536
e0165dcf 1537 int i, j, lastval, bitidx, half_switch;
1538 int clock = 64;
1539 int tolerance = clock / 8;
1540 int pmc, block_done;
1541 int lc, warnings = 0;
1542 int num_blocks = 0;
1543 int lmin=128, lmax=128;
1544 uint8_t dir;
e09f21fa 1545
1546 LFSetupFPGAForADC(95, true);
b8f705e7 1547 DoAcquisition_default(0, true);
e09f21fa 1548
e0165dcf 1549 lmin = 64;
1550 lmax = 192;
1551
1552 i = 2;
1553
1554 /* Find first local max/min */
b8f705e7 1555 if(dest[1] > dest[0]) {
e0165dcf 1556 while(i < GraphTraceLen) {
b8f705e7 1557 if( !(dest[i] > dest[i-1]) && dest[i] > lmax)
e0165dcf 1558 break;
1559 i++;
1560 }
1561 dir = 0;
1562 }
1563 else {
1564 while(i < GraphTraceLen) {
b8f705e7 1565 if( !(dest[i] < dest[i-1]) && dest[i] < lmin)
e0165dcf 1566 break;
1567 i++;
1568 }
1569 dir = 1;
1570 }
1571
1572 lastval = i++;
1573 half_switch = 0;
1574 pmc = 0;
1575 block_done = 0;
1576
1577 for (bitidx = 0; i < GraphTraceLen; i++)
1578 {
b8f705e7 1579 if ( (dest[i-1] > dest[i] && dir == 1 && dest[i] > lmax) || (dest[i-1] < dest[i] && dir == 0 && dest[i] < lmin))
e0165dcf 1580 {
1581 lc = i - lastval;
1582 lastval = i;
1583
1584 // Switch depending on lc length:
1585 // Tolerance is 1/8 of clock rate (arbitrary)
1586 if (abs(lc-clock/4) < tolerance) {
1587 // 16T0
1588 if((i - pmc) == lc) { /* 16T0 was previous one */
1589 /* It's a PMC ! */
1590 i += (128+127+16+32+33+16)-1;
1591 lastval = i;
1592 pmc = 0;
1593 block_done = 1;
1594 }
1595 else {
1596 pmc = i;
1597 }
1598 } else if (abs(lc-clock/2) < tolerance) {
1599 // 32TO
1600 if((i - pmc) == lc) { /* 16T0 was previous one */
1601 /* It's a PMC ! */
1602 i += (128+127+16+32+33)-1;
1603 lastval = i;
1604 pmc = 0;
1605 block_done = 1;
1606 }
1607 else if(half_switch == 1) {
b8f705e7 1608 bits[bitidx++] = 0;
e0165dcf 1609 half_switch = 0;
1610 }
1611 else
1612 half_switch++;
1613 } else if (abs(lc-clock) < tolerance) {
1614 // 64TO
b8f705e7 1615 bits[bitidx++] = 1;
e0165dcf 1616 } else {
1617 // Error
1618 warnings++;
1619 if (warnings > 10)
1620 {
1621 Dbprintf("Error: too many detection errors, aborting.");
1622 return 0;
1623 }
1624 }
1625
1626 if(block_done == 1) {
1627 if(bitidx == 128) {
1628 for(j=0; j<16; j++) {
b8f705e7 1629 blocks[num_blocks][j] = 128*bits[j*8+7]+
1630 64*bits[j*8+6]+
1631 32*bits[j*8+5]+
1632 16*bits[j*8+4]+
1633 8*bits[j*8+3]+
1634 4*bits[j*8+2]+
1635 2*bits[j*8+1]+
1636 bits[j*8];
1637
e0165dcf 1638 }
1639 num_blocks++;
1640 }
1641 bitidx = 0;
1642 block_done = 0;
1643 half_switch = 0;
1644 }
1645 if(i < GraphTraceLen)
b8f705e7 1646 dir =(dest[i-1] > dest[i]) ? 0 : 1;
e0165dcf 1647 }
1648 if(bitidx==255)
1649 bitidx=0;
1650 warnings = 0;
1651 if(num_blocks == 4) break;
1652 }
b8f705e7 1653 memcpy(outBlocks, blocks, 16*num_blocks);
e0165dcf 1654 return num_blocks;
e09f21fa 1655}
1656
1657int IsBlock0PCF7931(uint8_t *Block) {
e0165dcf 1658 // Assume RFU means 0 :)
1659 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1660 return 1;
1661 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1662 return 1;
1663 return 0;
e09f21fa 1664}
1665
1666int IsBlock1PCF7931(uint8_t *Block) {
e0165dcf 1667 // Assume RFU means 0 :)
1668 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1669 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1670 return 1;
e09f21fa 1671
e0165dcf 1672 return 0;
e09f21fa 1673}
1674
1675#define ALLOC 16
1676
1677void ReadPCF7931() {
e0165dcf 1678 uint8_t Blocks[8][17];
1679 uint8_t tmpBlocks[4][16];
1680 int i, j, ind, ind2, n;
1681 int num_blocks = 0;
1682 int max_blocks = 8;
1683 int ident = 0;
1684 int error = 0;
1685 int tries = 0;
1686
1687 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1688
1689 do {
1690 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1691 n = DemodPCF7931((uint8_t**)tmpBlocks);
1692 if(!n)
1693 error++;
1694 if(error==10 && num_blocks == 0) {
1695 Dbprintf("Error, no tag or bad tag");
1696 return;
1697 }
1698 else if (tries==20 || error==10) {
1699 Dbprintf("Error reading the tag");
1700 Dbprintf("Here is the partial content");
1701 goto end;
1702 }
1703
1704 for(i=0; i<n; i++)
1705 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1706 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1707 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1708 if(!ident) {
1709 for(i=0; i<n; i++) {
1710 if(IsBlock0PCF7931(tmpBlocks[i])) {
1711 // Found block 0 ?
1712 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1713 // Found block 1!
1714 // \o/
1715 ident = 1;
1716 memcpy(Blocks[0], tmpBlocks[i], 16);
1717 Blocks[0][ALLOC] = 1;
1718 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1719 Blocks[1][ALLOC] = 1;
1720 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1721 // Debug print
1722 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1723 num_blocks = 2;
1724 // Handle following blocks
1725 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1726 if(j==n) j=0;
1727 if(j==i) break;
1728 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1729 Blocks[ind2][ALLOC] = 1;
1730 }
1731 break;
1732 }
1733 }
1734 }
1735 }
1736 else {
1737 for(i=0; i<n; i++) { // Look for identical block in known blocks
1738 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1739 for(j=0; j<max_blocks; j++) {
1740 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1741 // Found an identical block
1742 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1743 if(ind2 < 0)
1744 ind2 = max_blocks;
1745 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1746 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1747 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1748 Blocks[ind2][ALLOC] = 1;
1749 num_blocks++;
1750 if(num_blocks == max_blocks) goto end;
1751 }
1752 }
1753 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1754 if(ind2 > max_blocks)
1755 ind2 = 0;
1756 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1757 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1758 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1759 Blocks[ind2][ALLOC] = 1;
1760 num_blocks++;
1761 if(num_blocks == max_blocks) goto end;
1762 }
1763 }
1764 }
1765 }
1766 }
1767 }
1768 }
1769 tries++;
1770 if (BUTTON_PRESS()) return;
1771 } while (num_blocks != max_blocks);
e09f21fa 1772 end:
e0165dcf 1773 Dbprintf("-----------------------------------------");
1774 Dbprintf("Memory content:");
1775 Dbprintf("-----------------------------------------");
1776 for(i=0; i<max_blocks; i++) {
1777 if(Blocks[i][ALLOC]==1)
1778 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1779 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1780 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1781 else
1782 Dbprintf("<missing block %d>", i);
1783 }
1784 Dbprintf("-----------------------------------------");
1785
1786 return ;
e09f21fa 1787}
1788
1789
1790//-----------------------------------
1791// EM4469 / EM4305 routines
1792//-----------------------------------
1793#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1794#define FWD_CMD_WRITE 0xA
1795#define FWD_CMD_READ 0x9
1796#define FWD_CMD_DISABLE 0x5
1797
1798
1799uint8_t forwardLink_data[64]; //array of forwarded bits
1800uint8_t * forward_ptr; //ptr for forward message preparation
1801uint8_t fwd_bit_sz; //forwardlink bit counter
1802uint8_t * fwd_write_ptr; //forwardlink bit pointer
1803
1804//====================================================================
1805// prepares command bits
1806// see EM4469 spec
1807//====================================================================
1808//--------------------------------------------------------------------
1809uint8_t Prepare_Cmd( uint8_t cmd ) {
e0165dcf 1810 //--------------------------------------------------------------------
e09f21fa 1811
e0165dcf 1812 *forward_ptr++ = 0; //start bit
1813 *forward_ptr++ = 0; //second pause for 4050 code
e09f21fa 1814
e0165dcf 1815 *forward_ptr++ = cmd;
1816 cmd >>= 1;
1817 *forward_ptr++ = cmd;
1818 cmd >>= 1;
1819 *forward_ptr++ = cmd;
1820 cmd >>= 1;
1821 *forward_ptr++ = cmd;
e09f21fa 1822
e0165dcf 1823 return 6; //return number of emited bits
e09f21fa 1824}
1825
1826//====================================================================
1827// prepares address bits
1828// see EM4469 spec
1829//====================================================================
1830
1831//--------------------------------------------------------------------
1832uint8_t Prepare_Addr( uint8_t addr ) {
e0165dcf 1833 //--------------------------------------------------------------------
e09f21fa 1834
e0165dcf 1835 register uint8_t line_parity;
e09f21fa 1836
e0165dcf 1837 uint8_t i;
1838 line_parity = 0;
1839 for(i=0;i<6;i++) {
1840 *forward_ptr++ = addr;
1841 line_parity ^= addr;
1842 addr >>= 1;
1843 }
e09f21fa 1844
e0165dcf 1845 *forward_ptr++ = (line_parity & 1);
e09f21fa 1846
e0165dcf 1847 return 7; //return number of emited bits
e09f21fa 1848}
1849
1850//====================================================================
1851// prepares data bits intreleaved with parity bits
1852// see EM4469 spec
1853//====================================================================
1854
1855//--------------------------------------------------------------------
1856uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
e0165dcf 1857 //--------------------------------------------------------------------
1858
1859 register uint8_t line_parity;
1860 register uint8_t column_parity;
1861 register uint8_t i, j;
1862 register uint16_t data;
1863
1864 data = data_low;
1865 column_parity = 0;
1866
1867 for(i=0; i<4; i++) {
1868 line_parity = 0;
1869 for(j=0; j<8; j++) {
1870 line_parity ^= data;
1871 column_parity ^= (data & 1) << j;
1872 *forward_ptr++ = data;
1873 data >>= 1;
1874 }
1875 *forward_ptr++ = line_parity;
1876 if(i == 1)
1877 data = data_hi;
1878 }
1879
1880 for(j=0; j<8; j++) {
1881 *forward_ptr++ = column_parity;
1882 column_parity >>= 1;
1883 }
1884 *forward_ptr = 0;
1885
1886 return 45; //return number of emited bits
e09f21fa 1887}
1888
1889//====================================================================
1890// Forward Link send function
1891// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1892// fwd_bit_count set with number of bits to be sent
1893//====================================================================
1894void SendForward(uint8_t fwd_bit_count) {
1895
e0165dcf 1896 fwd_write_ptr = forwardLink_data;
1897 fwd_bit_sz = fwd_bit_count;
1898
1899 LED_D_ON();
1900
1901 //Field on
1902 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1903 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1904 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1905
1906 // Give it a bit of time for the resonant antenna to settle.
1907 // And for the tag to fully power up
1908 SpinDelay(150);
1909
1910 // force 1st mod pulse (start gap must be longer for 4305)
1911 fwd_bit_sz--; //prepare next bit modulation
1912 fwd_write_ptr++;
1913 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1914 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1915 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1916 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1917 SpinDelayUs(16*8); //16 cycles on (8us each)
1918
1919 // now start writting
1920 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1921 if(((*fwd_write_ptr++) & 1) == 1)
1922 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1923 else {
1924 //These timings work for 4469/4269/4305 (with the 55*8 above)
1925 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1926 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1927 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1928 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1929 SpinDelayUs(9*8); //16 cycles on (8us each)
1930 }
1931 }
e09f21fa 1932}
1933
1934void EM4xLogin(uint32_t Password) {
1935
e0165dcf 1936 uint8_t fwd_bit_count;
e09f21fa 1937
e0165dcf 1938 forward_ptr = forwardLink_data;
1939 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1940 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
e09f21fa 1941
e0165dcf 1942 SendForward(fwd_bit_count);
e09f21fa 1943
e0165dcf 1944 //Wait for command to complete
1945 SpinDelay(20);
e09f21fa 1946
1947}
1948
1949void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1950
e0165dcf 1951 uint8_t *dest = BigBuf_get_addr();
b8f705e7 1952 uint16_t bufferlength = BigBuf_max_traceLen();
1953 uint32_t i = 0;
1954
1955 // Clear destination buffer before sending the command 0x80 = average.
1956 memset(dest, 0x80, bufferlength);
1957
1958 uint8_t fwd_bit_count;
e0165dcf 1959
1960 //If password mode do login
1961 if (PwdMode == 1) EM4xLogin(Pwd);
1962
1963 forward_ptr = forwardLink_data;
1964 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1965 fwd_bit_count += Prepare_Addr( Address );
1966
e0165dcf 1967 // Connect the A/D to the peak-detected low-frequency path.
1968 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1969 // Now set up the SSC to get the ADC samples that are now streaming at us.
1970 FpgaSetupSsc();
1971
1972 SendForward(fwd_bit_count);
1973
1974 // Now do the acquisition
1975 i = 0;
1976 for(;;) {
1977 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1978 AT91C_BASE_SSC->SSC_THR = 0x43;
1979 }
1980 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1981 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
b8f705e7 1982 ++i;
1983 if (i >= bufferlength) break;
e0165dcf 1984 }
1985 }
b8f705e7 1986
1987 cmd_send(CMD_ACK,0,0,0,0,0);
e0165dcf 1988 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1989 LED_D_OFF();
e09f21fa 1990}
1991
1992void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1993
e0165dcf 1994 uint8_t fwd_bit_count;
e09f21fa 1995
e0165dcf 1996 //If password mode do login
1997 if (PwdMode == 1) EM4xLogin(Pwd);
e09f21fa 1998
e0165dcf 1999 forward_ptr = forwardLink_data;
2000 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
2001 fwd_bit_count += Prepare_Addr( Address );
2002 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
e09f21fa 2003
e0165dcf 2004 SendForward(fwd_bit_count);
e09f21fa 2005
e0165dcf 2006 //Wait for write to complete
2007 SpinDelay(20);
2008 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2009 LED_D_OFF();
e09f21fa 2010}
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