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15c4dc5a | 1 | //----------------------------------------------------------------------------- |
b62a5a84 | 2 | // Merlok - June 2011, 2012 |
15c4dc5a | 3 | // Gerhard de Koning Gans - May 2008 |
534983d7 | 4 | // Hagen Fritsch - June 2010 |
bd20f8f4 | 5 | // |
6 | // This code is licensed to you under the terms of the GNU GPL, version 2 or, | |
7 | // at your option, any later version. See the LICENSE.txt file for the text of | |
8 | // the license. | |
15c4dc5a | 9 | //----------------------------------------------------------------------------- |
bd20f8f4 | 10 | // Routines to support ISO 14443 type A. |
11 | //----------------------------------------------------------------------------- | |
12 | ||
de77d4ac | 13 | #include "iso14443a.h" |
14 | ||
b7d3e899 | 15 | #include <stdio.h> |
16 | #include <string.h> | |
e30c654b | 17 | #include "proxmark3.h" |
15c4dc5a | 18 | #include "apps.h" |
f7e3ed82 | 19 | #include "util.h" |
902cb3c0 | 20 | #include "cmd.h" |
15c4dc5a | 21 | #include "iso14443crc.h" |
33443e7c | 22 | #include "crapto1/crapto1.h" |
20f9a2a1 | 23 | #include "mifareutil.h" |
de77d4ac | 24 | #include "mifaresniff.h" |
3000dc4e | 25 | #include "BigBuf.h" |
c872d8c1 | 26 | #include "protocols.h" |
1f065e1d | 27 | #include "parity.h" |
28 | ||
de77d4ac | 29 | typedef struct { |
30 | enum { | |
31 | DEMOD_UNSYNCD, | |
32 | // DEMOD_HALF_SYNCD, | |
33 | // DEMOD_MOD_FIRST_HALF, | |
34 | // DEMOD_NOMOD_FIRST_HALF, | |
35 | DEMOD_MANCHESTER_DATA | |
36 | } state; | |
37 | uint16_t twoBits; | |
38 | uint16_t highCnt; | |
39 | uint16_t bitCount; | |
40 | uint16_t collisionPos; | |
41 | uint16_t syncBit; | |
42 | uint8_t parityBits; | |
43 | uint8_t parityLen; | |
44 | uint16_t shiftReg; | |
45 | uint16_t samples; | |
46 | uint16_t len; | |
47 | uint32_t startTime, endTime; | |
48 | uint8_t *output; | |
49 | uint8_t *parity; | |
50 | } tDemod; | |
51 | ||
52 | typedef enum { | |
53 | MOD_NOMOD = 0, | |
54 | MOD_SECOND_HALF, | |
55 | MOD_FIRST_HALF, | |
56 | MOD_BOTH_HALVES | |
57 | } Modulation_t; | |
58 | ||
59 | typedef struct { | |
60 | enum { | |
61 | STATE_UNSYNCD, | |
62 | STATE_START_OF_COMMUNICATION, | |
63 | STATE_MILLER_X, | |
64 | STATE_MILLER_Y, | |
65 | STATE_MILLER_Z, | |
66 | // DROP_NONE, | |
67 | // DROP_FIRST_HALF, | |
68 | } state; | |
69 | uint16_t shiftReg; | |
70 | int16_t bitCount; | |
71 | uint16_t len; | |
72 | uint16_t byteCntMax; | |
73 | uint16_t posCnt; | |
74 | uint16_t syncBit; | |
75 | uint8_t parityBits; | |
76 | uint8_t parityLen; | |
77 | uint32_t fourBits; | |
78 | uint32_t startTime, endTime; | |
79 | uint8_t *output; | |
80 | uint8_t *parity; | |
81 | } tUart; | |
c872d8c1 | 82 | |
534983d7 | 83 | static uint32_t iso14a_timeout; |
db68bcdb | 84 | #define MAX_ISO14A_TIMEOUT 524288 |
85 | ||
1e262141 | 86 | int rsamples = 0; |
1e262141 | 87 | uint8_t trigger = 0; |
b0127e65 | 88 | // the block number for the ISO14443-4 PCB |
89 | static uint8_t iso14_pcb_blocknum = 0; | |
15c4dc5a | 90 | |
7bc95e2e | 91 | // |
92 | // ISO14443 timing: | |
93 | // | |
94 | // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles | |
95 | #define REQUEST_GUARD_TIME (7000/16 + 1) | |
96 | // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles | |
97 | #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1) | |
de77d4ac | 98 | // bool LastCommandWasRequest = false; |
7bc95e2e | 99 | |
100 | // | |
101 | // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz) | |
102 | // | |
d714d3ef | 103 | // When the PM acts as reader and is receiving tag data, it takes |
104 | // 3 ticks delay in the AD converter | |
105 | // 16 ticks until the modulation detector completes and sets curbit | |
106 | // 8 ticks until bit_to_arm is assigned from curbit | |
107 | // 8*16 ticks for the transfer from FPGA to ARM | |
7bc95e2e | 108 | // 4*16 ticks until we measure the time |
109 | // - 8*16 ticks because we measure the time of the previous transfer | |
d714d3ef | 110 | #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16) |
7bc95e2e | 111 | |
112 | // When the PM acts as a reader and is sending, it takes | |
113 | // 4*16 ticks until we can write data to the sending hold register | |
114 | // 8*16 ticks until the SHR is transferred to the Sending Shift Register | |
115 | // 8 ticks until the first transfer starts | |
116 | // 8 ticks later the FPGA samples the data | |
117 | // 1 tick to assign mod_sig_coil | |
118 | #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1) | |
119 | ||
120 | // When the PM acts as tag and is receiving it takes | |
d714d3ef | 121 | // 2 ticks delay in the RF part (for the first falling edge), |
7bc95e2e | 122 | // 3 ticks for the A/D conversion, |
123 | // 8 ticks on average until the start of the SSC transfer, | |
124 | // 8 ticks until the SSC samples the first data | |
125 | // 7*16 ticks to complete the transfer from FPGA to ARM | |
126 | // 8 ticks until the next ssp_clk rising edge | |
d714d3ef | 127 | // 4*16 ticks until we measure the time |
7bc95e2e | 128 | // - 8*16 ticks because we measure the time of the previous transfer |
d714d3ef | 129 | #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16) |
7bc95e2e | 130 | |
131 | // The FPGA will report its internal sending delay in | |
132 | uint16_t FpgaSendQueueDelay; | |
133 | // the 5 first bits are the number of bits buffered in mod_sig_buf | |
134 | // the last three bits are the remaining ticks/2 after the mod_sig_buf shift | |
135 | #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1) | |
136 | ||
137 | // When the PM acts as tag and is sending, it takes | |
6e49717b | 138 | // 4*16 + 8 ticks until we can write data to the sending hold register |
7bc95e2e | 139 | // 8*16 ticks until the SHR is transferred to the Sending Shift Register |
6e49717b | 140 | // 8 ticks later the FPGA samples the first data |
141 | // + 16 ticks until assigned to mod_sig | |
7bc95e2e | 142 | // + 1 tick to assign mod_sig_coil |
6e49717b | 143 | // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf) |
144 | #define DELAY_ARM2AIR_AS_TAG (4*16 + 8 + 8*16 + 8 + 16 + 1 + DELAY_FPGA_QUEUE) | |
7bc95e2e | 145 | |
146 | // When the PM acts as sniffer and is receiving tag data, it takes | |
147 | // 3 ticks A/D conversion | |
d714d3ef | 148 | // 14 ticks to complete the modulation detection |
149 | // 8 ticks (on average) until the result is stored in to_arm | |
7bc95e2e | 150 | // + the delays in transferring data - which is the same for |
151 | // sniffing reader and tag data and therefore not relevant | |
d714d3ef | 152 | #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8) |
7bc95e2e | 153 | |
d714d3ef | 154 | // When the PM acts as sniffer and is receiving reader data, it takes |
155 | // 2 ticks delay in analogue RF receiver (for the falling edge of the | |
156 | // start bit, which marks the start of the communication) | |
7bc95e2e | 157 | // 3 ticks A/D conversion |
d714d3ef | 158 | // 8 ticks on average until the data is stored in to_arm. |
7bc95e2e | 159 | // + the delays in transferring data - which is the same for |
160 | // sniffing reader and tag data and therefore not relevant | |
d714d3ef | 161 | #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8) |
7bc95e2e | 162 | |
163 | //variables used for timing purposes: | |
164 | //these are in ssp_clk cycles: | |
6a1f2d82 | 165 | static uint32_t NextTransferTime; |
166 | static uint32_t LastTimeProxToAirStart; | |
167 | static uint32_t LastProxToAirDuration; | |
7bc95e2e | 168 | |
169 | ||
170 | ||
8f51ddb0 | 171 | // CARD TO READER - manchester |
72934aa3 | 172 | // Sequence D: 11110000 modulation with subcarrier during first half |
173 | // Sequence E: 00001111 modulation with subcarrier during second half | |
174 | // Sequence F: 00000000 no modulation with subcarrier | |
8f51ddb0 | 175 | // READER TO CARD - miller |
72934aa3 | 176 | // Sequence X: 00001100 drop after half a period |
177 | // Sequence Y: 00000000 no drop | |
178 | // Sequence Z: 11000000 drop at start | |
179 | #define SEC_D 0xf0 | |
180 | #define SEC_E 0x0f | |
181 | #define SEC_F 0x00 | |
182 | #define SEC_X 0x0c | |
183 | #define SEC_Y 0x00 | |
184 | #define SEC_Z 0xc0 | |
15c4dc5a | 185 | |
902cb3c0 | 186 | void iso14a_set_trigger(bool enable) { |
534983d7 | 187 | trigger = enable; |
188 | } | |
189 | ||
d19929cb | 190 | |
bb04ef21 | 191 | void iso14a_set_timeout(uint32_t timeout) { |
fa85b085 | 192 | // adjust timeout by FPGA delays and 2 additional ssp_frames to detect SOF |
193 | iso14a_timeout = timeout + (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/(16*8) + 2; | |
47b78133 | 194 | if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", timeout, timeout / 106); |
b0127e65 | 195 | } |
8556b852 | 196 | |
19a700a8 | 197 | |
47b78133 | 198 | uint32_t iso14a_get_timeout(void) { |
fa85b085 | 199 | return iso14a_timeout - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/(16*8) - 2; |
19a700a8 | 200 | } |
201 | ||
15c4dc5a | 202 | //----------------------------------------------------------------------------- |
203 | // Generate the parity value for a byte sequence | |
e30c654b | 204 | // |
15c4dc5a | 205 | //----------------------------------------------------------------------------- |
6a1f2d82 | 206 | void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par) |
15c4dc5a | 207 | { |
6a1f2d82 | 208 | uint16_t paritybit_cnt = 0; |
209 | uint16_t paritybyte_cnt = 0; | |
210 | uint8_t parityBits = 0; | |
211 | ||
212 | for (uint16_t i = 0; i < iLen; i++) { | |
213 | // Generate the parity bits | |
1f065e1d | 214 | parityBits |= ((oddparity8(pbtCmd[i])) << (7-paritybit_cnt)); |
6a1f2d82 | 215 | if (paritybit_cnt == 7) { |
216 | par[paritybyte_cnt] = parityBits; // save 8 Bits parity | |
217 | parityBits = 0; // and advance to next Parity Byte | |
218 | paritybyte_cnt++; | |
219 | paritybit_cnt = 0; | |
220 | } else { | |
221 | paritybit_cnt++; | |
222 | } | |
5f6d6c90 | 223 | } |
6a1f2d82 | 224 | |
225 | // save remaining parity bits | |
226 | par[paritybyte_cnt] = parityBits; | |
227 | ||
15c4dc5a | 228 | } |
229 | ||
534983d7 | 230 | void AppendCrc14443a(uint8_t* data, int len) |
15c4dc5a | 231 | { |
5f6d6c90 | 232 | ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1); |
15c4dc5a | 233 | } |
234 | ||
6e49717b | 235 | static void AppendCrc14443b(uint8_t* data, int len) |
48ece4a7 | 236 | { |
237 | ComputeCrc14443(CRC_14443_B,data,len,data+len,data+len+1); | |
238 | } | |
239 | ||
240 | ||
7bc95e2e | 241 | //============================================================================= |
242 | // ISO 14443 Type A - Miller decoder | |
243 | //============================================================================= | |
244 | // Basics: | |
245 | // This decoder is used when the PM3 acts as a tag. | |
246 | // The reader will generate "pauses" by temporarily switching of the field. | |
247 | // At the PM3 antenna we will therefore measure a modulated antenna voltage. | |
248 | // The FPGA does a comparison with a threshold and would deliver e.g.: | |
249 | // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 ....... | |
250 | // The Miller decoder needs to identify the following sequences: | |
251 | // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0") | |
252 | // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information") | |
253 | // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1") | |
254 | // Note 1: the bitstream may start at any time. We therefore need to sync. | |
255 | // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence. | |
15c4dc5a | 256 | //----------------------------------------------------------------------------- |
b62a5a84 | 257 | static tUart Uart; |
15c4dc5a | 258 | |
d7aa3739 | 259 | // Lookup-Table to decide if 4 raw bits are a modulation. |
05ddb52c | 260 | // We accept the following: |
261 | // 0001 - a 3 tick wide pause | |
262 | // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left | |
263 | // 0111 - a 2 tick wide pause shifted left | |
264 | // 1001 - a 2 tick wide pause shifted right | |
d7aa3739 | 265 | const bool Mod_Miller_LUT[] = { |
de77d4ac | 266 | false, true, false, true, false, false, false, true, |
267 | false, true, false, false, false, false, false, false | |
d7aa3739 | 268 | }; |
05ddb52c | 269 | #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4]) |
270 | #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)]) | |
d7aa3739 | 271 | |
6e49717b | 272 | static void UartReset() |
15c4dc5a | 273 | { |
7bc95e2e | 274 | Uart.state = STATE_UNSYNCD; |
275 | Uart.bitCount = 0; | |
276 | Uart.len = 0; // number of decoded data bytes | |
6a1f2d82 | 277 | Uart.parityLen = 0; // number of decoded parity bytes |
7bc95e2e | 278 | Uart.shiftReg = 0; // shiftreg to hold decoded data bits |
6a1f2d82 | 279 | Uart.parityBits = 0; // holds 8 parity bits |
7bc95e2e | 280 | Uart.startTime = 0; |
281 | Uart.endTime = 0; | |
282 | } | |
15c4dc5a | 283 | |
6e49717b | 284 | static void UartInit(uint8_t *data, uint8_t *parity) |
6a1f2d82 | 285 | { |
286 | Uart.output = data; | |
287 | Uart.parity = parity; | |
05ddb52c | 288 | Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits |
6a1f2d82 | 289 | UartReset(); |
290 | } | |
d714d3ef | 291 | |
7bc95e2e | 292 | // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time |
293 | static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time) | |
294 | { | |
15c4dc5a | 295 | |
ef00343c | 296 | Uart.fourBits = (Uart.fourBits << 8) | bit; |
7bc95e2e | 297 | |
0c8d25eb | 298 | if (Uart.state == STATE_UNSYNCD) { // not yet synced |
3fe4ff4f | 299 | |
ef00343c | 300 | Uart.syncBit = 9999; // not set |
05ddb52c | 301 | // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from |
302 | // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111) | |
303 | // we therefore look for a ...xx11111111111100x11111xxxxxx... pattern | |
304 | // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's) | |
48ece4a7 | 305 | #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00000111 11111111 11101111 10000000 |
306 | #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00000111 11111111 10001111 10000000 | |
05ddb52c | 307 | if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7; |
308 | else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6; | |
309 | else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5; | |
310 | else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4; | |
311 | else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3; | |
312 | else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2; | |
313 | else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1; | |
314 | else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0; | |
315 | ||
ef00343c | 316 | if (Uart.syncBit != 9999) { // found a sync bit |
317 | Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8); | |
318 | Uart.startTime -= Uart.syncBit; | |
319 | Uart.endTime = Uart.startTime; | |
320 | Uart.state = STATE_START_OF_COMMUNICATION; | |
7bc95e2e | 321 | } |
15c4dc5a | 322 | |
7bc95e2e | 323 | } else { |
15c4dc5a | 324 | |
ef00343c | 325 | if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) { |
326 | if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error | |
d7aa3739 | 327 | UartReset(); |
d7aa3739 | 328 | } else { // Modulation in first half = Sequence Z = logic "0" |
7bc95e2e | 329 | if (Uart.state == STATE_MILLER_X) { // error - must not follow after X |
330 | UartReset(); | |
7bc95e2e | 331 | } else { |
332 | Uart.bitCount++; | |
333 | Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg | |
334 | Uart.state = STATE_MILLER_Z; | |
335 | Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6; | |
336 | if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity) | |
337 | Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); | |
338 | Uart.parityBits <<= 1; // make room for the parity bit | |
339 | Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit | |
340 | Uart.bitCount = 0; | |
341 | Uart.shiftReg = 0; | |
6a1f2d82 | 342 | if((Uart.len&0x0007) == 0) { // every 8 data bytes |
343 | Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits | |
344 | Uart.parityBits = 0; | |
345 | } | |
15c4dc5a | 346 | } |
7bc95e2e | 347 | } |
d7aa3739 | 348 | } |
349 | } else { | |
ef00343c | 350 | if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1" |
7bc95e2e | 351 | Uart.bitCount++; |
352 | Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg | |
353 | Uart.state = STATE_MILLER_X; | |
354 | Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2; | |
355 | if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity) | |
356 | Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); | |
357 | Uart.parityBits <<= 1; // make room for the new parity bit | |
358 | Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit | |
359 | Uart.bitCount = 0; | |
360 | Uart.shiftReg = 0; | |
6a1f2d82 | 361 | if ((Uart.len&0x0007) == 0) { // every 8 data bytes |
362 | Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits | |
363 | Uart.parityBits = 0; | |
364 | } | |
7bc95e2e | 365 | } |
d7aa3739 | 366 | } else { // no modulation in both halves - Sequence Y |
7bc95e2e | 367 | if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication |
15c4dc5a | 368 | Uart.state = STATE_UNSYNCD; |
6a1f2d82 | 369 | Uart.bitCount--; // last "0" was part of EOC sequence |
370 | Uart.shiftReg <<= 1; // drop it | |
371 | if(Uart.bitCount > 0) { // if we decoded some bits | |
372 | Uart.shiftReg >>= (9 - Uart.bitCount); // right align them | |
373 | Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output | |
374 | Uart.parityBits <<= 1; // add a (void) parity bit | |
375 | Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits | |
376 | Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it | |
de77d4ac | 377 | return true; |
6a1f2d82 | 378 | } else if (Uart.len & 0x0007) { // there are some parity bits to store |
379 | Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits | |
380 | Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them | |
52bfb955 | 381 | } |
382 | if (Uart.len) { | |
de77d4ac | 383 | return true; // we are finished with decoding the raw data sequence |
52bfb955 | 384 | } else { |
0c8d25eb | 385 | UartReset(); // Nothing received - start over |
7bc95e2e | 386 | } |
15c4dc5a | 387 | } |
7bc95e2e | 388 | if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC |
389 | UartReset(); | |
7bc95e2e | 390 | } else { // a logic "0" |
391 | Uart.bitCount++; | |
392 | Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg | |
393 | Uart.state = STATE_MILLER_Y; | |
394 | if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity) | |
395 | Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); | |
396 | Uart.parityBits <<= 1; // make room for the parity bit | |
397 | Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit | |
398 | Uart.bitCount = 0; | |
399 | Uart.shiftReg = 0; | |
6a1f2d82 | 400 | if ((Uart.len&0x0007) == 0) { // every 8 data bytes |
401 | Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits | |
402 | Uart.parityBits = 0; | |
403 | } | |
15c4dc5a | 404 | } |
405 | } | |
d7aa3739 | 406 | } |
15c4dc5a | 407 | } |
7bc95e2e | 408 | |
409 | } | |
15c4dc5a | 410 | |
de77d4ac | 411 | return false; // not finished yet, need more data |
15c4dc5a | 412 | } |
413 | ||
7bc95e2e | 414 | |
415 | ||
15c4dc5a | 416 | //============================================================================= |
e691fc45 | 417 | // ISO 14443 Type A - Manchester decoder |
15c4dc5a | 418 | //============================================================================= |
e691fc45 | 419 | // Basics: |
7bc95e2e | 420 | // This decoder is used when the PM3 acts as a reader. |
e691fc45 | 421 | // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage |
422 | // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following: | |
423 | // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ....... | |
424 | // The Manchester decoder needs to identify the following sequences: | |
425 | // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication") | |
426 | // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0 | |
427 | // 8 ticks unmodulated: Sequence F = end of communication | |
428 | // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D | |
7bc95e2e | 429 | // Note 1: the bitstream may start at any time. We therefore need to sync. |
e691fc45 | 430 | // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only) |
b62a5a84 | 431 | static tDemod Demod; |
15c4dc5a | 432 | |
d7aa3739 | 433 | // Lookup-Table to decide if 4 raw bits are a modulation. |
d714d3ef | 434 | // We accept three or four "1" in any position |
7bc95e2e | 435 | const bool Mod_Manchester_LUT[] = { |
de77d4ac | 436 | false, false, false, false, false, false, false, true, |
437 | false, false, false, true, false, true, true, true | |
7bc95e2e | 438 | }; |
439 | ||
440 | #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4]) | |
441 | #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)]) | |
15c4dc5a | 442 | |
2f2d9fc5 | 443 | |
6e49717b | 444 | static void DemodReset() |
e691fc45 | 445 | { |
7bc95e2e | 446 | Demod.state = DEMOD_UNSYNCD; |
447 | Demod.len = 0; // number of decoded data bytes | |
6a1f2d82 | 448 | Demod.parityLen = 0; |
7bc95e2e | 449 | Demod.shiftReg = 0; // shiftreg to hold decoded data bits |
450 | Demod.parityBits = 0; // | |
451 | Demod.collisionPos = 0; // Position of collision bit | |
452 | Demod.twoBits = 0xffff; // buffer for 2 Bits | |
453 | Demod.highCnt = 0; | |
454 | Demod.startTime = 0; | |
455 | Demod.endTime = 0; | |
e691fc45 | 456 | } |
15c4dc5a | 457 | |
6e49717b | 458 | static void DemodInit(uint8_t *data, uint8_t *parity) |
6a1f2d82 | 459 | { |
460 | Demod.output = data; | |
461 | Demod.parity = parity; | |
462 | DemodReset(); | |
463 | } | |
464 | ||
7bc95e2e | 465 | // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time |
466 | static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time) | |
e691fc45 | 467 | { |
7bc95e2e | 468 | |
469 | Demod.twoBits = (Demod.twoBits << 8) | bit; | |
e691fc45 | 470 | |
7bc95e2e | 471 | if (Demod.state == DEMOD_UNSYNCD) { |
472 | ||
473 | if (Demod.highCnt < 2) { // wait for a stable unmodulated signal | |
474 | if (Demod.twoBits == 0x0000) { | |
475 | Demod.highCnt++; | |
476 | } else { | |
477 | Demod.highCnt = 0; | |
478 | } | |
479 | } else { | |
480 | Demod.syncBit = 0xFFFF; // not set | |
481 | if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7; | |
482 | else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6; | |
483 | else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5; | |
484 | else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4; | |
485 | else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3; | |
486 | else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2; | |
487 | else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1; | |
488 | else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0; | |
d7aa3739 | 489 | if (Demod.syncBit != 0xFFFF) { |
7bc95e2e | 490 | Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8); |
491 | Demod.startTime -= Demod.syncBit; | |
492 | Demod.bitCount = offset; // number of decoded data bits | |
e691fc45 | 493 | Demod.state = DEMOD_MANCHESTER_DATA; |
2f2d9fc5 | 494 | } |
7bc95e2e | 495 | } |
15c4dc5a | 496 | |
7bc95e2e | 497 | } else { |
15c4dc5a | 498 | |
7bc95e2e | 499 | if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half |
500 | if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision | |
e691fc45 | 501 | if (!Demod.collisionPos) { |
502 | Demod.collisionPos = (Demod.len << 3) + Demod.bitCount; | |
503 | } | |
504 | } // modulation in first half only - Sequence D = 1 | |
7bc95e2e | 505 | Demod.bitCount++; |
506 | Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg | |
507 | if(Demod.bitCount == 9) { // if we decoded a full byte (including parity) | |
e691fc45 | 508 | Demod.output[Demod.len++] = (Demod.shiftReg & 0xff); |
7bc95e2e | 509 | Demod.parityBits <<= 1; // make room for the parity bit |
e691fc45 | 510 | Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit |
511 | Demod.bitCount = 0; | |
512 | Demod.shiftReg = 0; | |
6a1f2d82 | 513 | if((Demod.len&0x0007) == 0) { // every 8 data bytes |
514 | Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits | |
515 | Demod.parityBits = 0; | |
516 | } | |
15c4dc5a | 517 | } |
7bc95e2e | 518 | Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4; |
519 | } else { // no modulation in first half | |
520 | if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0 | |
e691fc45 | 521 | Demod.bitCount++; |
7bc95e2e | 522 | Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg |
e691fc45 | 523 | if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity) |
e691fc45 | 524 | Demod.output[Demod.len++] = (Demod.shiftReg & 0xff); |
7bc95e2e | 525 | Demod.parityBits <<= 1; // make room for the new parity bit |
e691fc45 | 526 | Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit |
527 | Demod.bitCount = 0; | |
528 | Demod.shiftReg = 0; | |
6a1f2d82 | 529 | if ((Demod.len&0x0007) == 0) { // every 8 data bytes |
530 | Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1 | |
531 | Demod.parityBits = 0; | |
532 | } | |
15c4dc5a | 533 | } |
7bc95e2e | 534 | Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1); |
e691fc45 | 535 | } else { // no modulation in both halves - End of communication |
6a1f2d82 | 536 | if(Demod.bitCount > 0) { // there are some remaining data bits |
537 | Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits | |
538 | Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output | |
539 | Demod.parityBits <<= 1; // add a (void) parity bit | |
540 | Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits | |
541 | Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them | |
de77d4ac | 542 | return true; |
6a1f2d82 | 543 | } else if (Demod.len & 0x0007) { // there are some parity bits to store |
544 | Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits | |
545 | Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them | |
52bfb955 | 546 | } |
547 | if (Demod.len) { | |
de77d4ac | 548 | return true; // we are finished with decoding the raw data sequence |
d7aa3739 | 549 | } else { // nothing received. Start over |
550 | DemodReset(); | |
e691fc45 | 551 | } |
15c4dc5a | 552 | } |
7bc95e2e | 553 | } |
e691fc45 | 554 | |
555 | } | |
15c4dc5a | 556 | |
de77d4ac | 557 | return false; // not finished yet, need more data |
15c4dc5a | 558 | } |
559 | ||
560 | //============================================================================= | |
561 | // Finally, a `sniffer' for ISO 14443 Type A | |
562 | // Both sides of communication! | |
563 | //============================================================================= | |
564 | ||
565 | //----------------------------------------------------------------------------- | |
566 | // Record the sequence of commands sent by the reader to the tag, with | |
567 | // triggering so that we start recording at the point that the tag is moved | |
568 | // near the reader. | |
569 | //----------------------------------------------------------------------------- | |
5cd9ec01 M |
570 | void RAMFUNC SnoopIso14443a(uint8_t param) { |
571 | // param: | |
572 | // bit 0 - trigger from first card answer | |
573 | // bit 1 - trigger from first reader 7-bit request | |
574 | ||
575 | LEDsoff(); | |
5cd9ec01 | 576 | |
09ffd16e | 577 | iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER); |
578 | ||
f71f4deb | 579 | // Allocate memory from BigBuf for some buffers |
580 | // free all previous allocations first | |
581 | BigBuf_free(); | |
582 | ||
5cd9ec01 | 583 | // The command (reader -> tag) that we're receiving. |
f71f4deb | 584 | uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE); |
585 | uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE); | |
6a1f2d82 | 586 | |
5cd9ec01 | 587 | // The response (tag -> reader) that we're receiving. |
f71f4deb | 588 | uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE); |
589 | uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE); | |
5cd9ec01 M |
590 | |
591 | // The DMA buffer, used to stream samples from the FPGA | |
f71f4deb | 592 | uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE); |
593 | ||
594 | // init trace buffer | |
3000dc4e | 595 | clear_trace(); |
de77d4ac | 596 | set_tracing(true); |
f71f4deb | 597 | |
7bc95e2e | 598 | uint8_t *data = dmaBuf; |
599 | uint8_t previous_data = 0; | |
5cd9ec01 M |
600 | int maxDataLen = 0; |
601 | int dataLen = 0; | |
de77d4ac | 602 | bool TagIsActive = false; |
603 | bool ReaderIsActive = false; | |
7bc95e2e | 604 | |
5cd9ec01 | 605 | // Set up the demodulator for tag -> reader responses. |
6a1f2d82 | 606 | DemodInit(receivedResponse, receivedResponsePar); |
607 | ||
5cd9ec01 | 608 | // Set up the demodulator for the reader -> tag commands |
6a1f2d82 | 609 | UartInit(receivedCmd, receivedCmdPar); |
610 | ||
7bc95e2e | 611 | // Setup and start DMA. |
5cd9ec01 | 612 | FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); |
7bc95e2e | 613 | |
09ffd16e | 614 | // We won't start recording the frames that we acquire until we trigger; |
615 | // a good trigger condition to get started is probably when we see a | |
616 | // response from the tag. | |
de77d4ac | 617 | // triggered == false -- to wait first for card |
09ffd16e | 618 | bool triggered = !(param & 0x03); |
619 | ||
5cd9ec01 | 620 | // And now we loop, receiving samples. |
de77d4ac | 621 | for(uint32_t rsamples = 0; true; ) { |
7bc95e2e | 622 | |
5cd9ec01 M |
623 | if(BUTTON_PRESS()) { |
624 | DbpString("cancelled by button"); | |
7bc95e2e | 625 | break; |
5cd9ec01 | 626 | } |
15c4dc5a | 627 | |
5cd9ec01 M |
628 | LED_A_ON(); |
629 | WDT_HIT(); | |
15c4dc5a | 630 | |
5cd9ec01 M |
631 | int register readBufDataP = data - dmaBuf; |
632 | int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; | |
633 | if (readBufDataP <= dmaBufDataP){ | |
634 | dataLen = dmaBufDataP - readBufDataP; | |
635 | } else { | |
7bc95e2e | 636 | dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; |
5cd9ec01 M |
637 | } |
638 | // test for length of buffer | |
639 | if(dataLen > maxDataLen) { | |
640 | maxDataLen = dataLen; | |
f71f4deb | 641 | if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) { |
7bc95e2e | 642 | Dbprintf("blew circular buffer! dataLen=%d", dataLen); |
643 | break; | |
5cd9ec01 M |
644 | } |
645 | } | |
646 | if(dataLen < 1) continue; | |
647 | ||
648 | // primary buffer was stopped( <-- we lost data! | |
649 | if (!AT91C_BASE_PDC_SSC->PDC_RCR) { | |
650 | AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf; | |
651 | AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE; | |
7bc95e2e | 652 | Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary |
5cd9ec01 M |
653 | } |
654 | // secondary buffer sets as primary, secondary buffer was stopped | |
655 | if (!AT91C_BASE_PDC_SSC->PDC_RNCR) { | |
656 | AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf; | |
657 | AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE; | |
658 | } | |
659 | ||
660 | LED_A_OFF(); | |
7bc95e2e | 661 | |
662 | if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder | |
3be2a5ae | 663 | |
7bc95e2e | 664 | if(!TagIsActive) { // no need to try decoding reader data if the tag is sending |
665 | uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4); | |
666 | if (MillerDecoding(readerdata, (rsamples-1)*4)) { | |
667 | LED_C_ON(); | |
5cd9ec01 | 668 | |
7bc95e2e | 669 | // check - if there is a short 7bit request from reader |
de77d4ac | 670 | if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = true; |
5cd9ec01 | 671 | |
7bc95e2e | 672 | if(triggered) { |
6a1f2d82 | 673 | if (!LogTrace(receivedCmd, |
674 | Uart.len, | |
675 | Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, | |
676 | Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, | |
677 | Uart.parity, | |
de77d4ac | 678 | true)) break; |
7bc95e2e | 679 | } |
680 | /* And ready to receive another command. */ | |
48ece4a7 | 681 | UartReset(); |
7bc95e2e | 682 | /* And also reset the demod code, which might have been */ |
683 | /* false-triggered by the commands from the reader. */ | |
684 | DemodReset(); | |
685 | LED_B_OFF(); | |
686 | } | |
687 | ReaderIsActive = (Uart.state != STATE_UNSYNCD); | |
5cd9ec01 | 688 | } |
3be2a5ae | 689 | |
7bc95e2e | 690 | if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time |
691 | uint8_t tagdata = (previous_data << 4) | (*data & 0x0F); | |
692 | if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) { | |
693 | LED_B_ON(); | |
5cd9ec01 | 694 | |
6a1f2d82 | 695 | if (!LogTrace(receivedResponse, |
696 | Demod.len, | |
697 | Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER, | |
698 | Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER, | |
699 | Demod.parity, | |
de77d4ac | 700 | false)) break; |
5cd9ec01 | 701 | |
de77d4ac | 702 | if ((!triggered) && (param & 0x01)) triggered = true; |
5cd9ec01 | 703 | |
7bc95e2e | 704 | // And ready to receive another response. |
705 | DemodReset(); | |
48ece4a7 | 706 | // And reset the Miller decoder including itS (now outdated) input buffer |
707 | UartInit(receivedCmd, receivedCmdPar); | |
708 | ||
7bc95e2e | 709 | LED_C_OFF(); |
710 | } | |
711 | TagIsActive = (Demod.state != DEMOD_UNSYNCD); | |
712 | } | |
5cd9ec01 M |
713 | } |
714 | ||
7bc95e2e | 715 | previous_data = *data; |
716 | rsamples++; | |
5cd9ec01 | 717 | data++; |
d714d3ef | 718 | if(data == dmaBuf + DMA_BUFFER_SIZE) { |
5cd9ec01 M |
719 | data = dmaBuf; |
720 | } | |
721 | } // main cycle | |
722 | ||
723 | DbpString("COMMAND FINISHED"); | |
15c4dc5a | 724 | |
7bc95e2e | 725 | FpgaDisableSscDma(); |
726 | Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len); | |
3000dc4e | 727 | Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]); |
5cd9ec01 | 728 | LEDsoff(); |
15c4dc5a | 729 | } |
730 | ||
15c4dc5a | 731 | //----------------------------------------------------------------------------- |
732 | // Prepare tag messages | |
733 | //----------------------------------------------------------------------------- | |
6a1f2d82 | 734 | static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity) |
15c4dc5a | 735 | { |
8f51ddb0 | 736 | ToSendReset(); |
15c4dc5a | 737 | |
738 | // Correction bit, might be removed when not needed | |
739 | ToSendStuffBit(0); | |
740 | ToSendStuffBit(0); | |
741 | ToSendStuffBit(0); | |
742 | ToSendStuffBit(0); | |
743 | ToSendStuffBit(1); // 1 | |
744 | ToSendStuffBit(0); | |
745 | ToSendStuffBit(0); | |
746 | ToSendStuffBit(0); | |
8f51ddb0 | 747 | |
15c4dc5a | 748 | // Send startbit |
72934aa3 | 749 | ToSend[++ToSendMax] = SEC_D; |
7bc95e2e | 750 | LastProxToAirDuration = 8 * ToSendMax - 4; |
15c4dc5a | 751 | |
6a1f2d82 | 752 | for(uint16_t i = 0; i < len; i++) { |
8f51ddb0 | 753 | uint8_t b = cmd[i]; |
15c4dc5a | 754 | |
755 | // Data bits | |
6a1f2d82 | 756 | for(uint16_t j = 0; j < 8; j++) { |
15c4dc5a | 757 | if(b & 1) { |
72934aa3 | 758 | ToSend[++ToSendMax] = SEC_D; |
15c4dc5a | 759 | } else { |
72934aa3 | 760 | ToSend[++ToSendMax] = SEC_E; |
8f51ddb0 M |
761 | } |
762 | b >>= 1; | |
763 | } | |
15c4dc5a | 764 | |
0014cb46 | 765 | // Get the parity bit |
6a1f2d82 | 766 | if (parity[i>>3] & (0x80>>(i&0x0007))) { |
8f51ddb0 | 767 | ToSend[++ToSendMax] = SEC_D; |
7bc95e2e | 768 | LastProxToAirDuration = 8 * ToSendMax - 4; |
15c4dc5a | 769 | } else { |
72934aa3 | 770 | ToSend[++ToSendMax] = SEC_E; |
7bc95e2e | 771 | LastProxToAirDuration = 8 * ToSendMax; |
15c4dc5a | 772 | } |
8f51ddb0 | 773 | } |
15c4dc5a | 774 | |
8f51ddb0 M |
775 | // Send stopbit |
776 | ToSend[++ToSendMax] = SEC_F; | |
15c4dc5a | 777 | |
8f51ddb0 M |
778 | // Convert from last byte pos to length |
779 | ToSendMax++; | |
8f51ddb0 M |
780 | } |
781 | ||
15c4dc5a | 782 | |
8f51ddb0 M |
783 | static void Code4bitAnswerAsTag(uint8_t cmd) |
784 | { | |
785 | int i; | |
786 | ||
5f6d6c90 | 787 | ToSendReset(); |
8f51ddb0 M |
788 | |
789 | // Correction bit, might be removed when not needed | |
790 | ToSendStuffBit(0); | |
791 | ToSendStuffBit(0); | |
792 | ToSendStuffBit(0); | |
793 | ToSendStuffBit(0); | |
794 | ToSendStuffBit(1); // 1 | |
795 | ToSendStuffBit(0); | |
796 | ToSendStuffBit(0); | |
797 | ToSendStuffBit(0); | |
798 | ||
799 | // Send startbit | |
800 | ToSend[++ToSendMax] = SEC_D; | |
801 | ||
802 | uint8_t b = cmd; | |
803 | for(i = 0; i < 4; i++) { | |
804 | if(b & 1) { | |
805 | ToSend[++ToSendMax] = SEC_D; | |
7bc95e2e | 806 | LastProxToAirDuration = 8 * ToSendMax - 4; |
8f51ddb0 M |
807 | } else { |
808 | ToSend[++ToSendMax] = SEC_E; | |
7bc95e2e | 809 | LastProxToAirDuration = 8 * ToSendMax; |
8f51ddb0 M |
810 | } |
811 | b >>= 1; | |
812 | } | |
813 | ||
814 | // Send stopbit | |
815 | ToSend[++ToSendMax] = SEC_F; | |
816 | ||
5f6d6c90 | 817 | // Convert from last byte pos to length |
818 | ToSendMax++; | |
15c4dc5a | 819 | } |
820 | ||
6e49717b | 821 | |
822 | static uint8_t *LastReaderTraceTime = NULL; | |
823 | ||
824 | static void EmLogTraceReader(void) { | |
825 | // remember last reader trace start to fix timing info later | |
826 | LastReaderTraceTime = BigBuf_get_addr() + BigBuf_get_traceLen(); | |
827 | LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, true); | |
828 | } | |
829 | ||
830 | ||
831 | static void FixLastReaderTraceTime(uint32_t tag_StartTime) { | |
832 | uint32_t reader_EndTime = Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG; | |
833 | uint32_t reader_StartTime = Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG; | |
834 | uint16_t reader_modlen = reader_EndTime - reader_StartTime; | |
835 | uint16_t approx_fdt = tag_StartTime - reader_EndTime; | |
836 | uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20; | |
837 | reader_StartTime = tag_StartTime - exact_fdt - reader_modlen; | |
838 | LastReaderTraceTime[0] = (reader_StartTime >> 0) & 0xff; | |
839 | LastReaderTraceTime[1] = (reader_StartTime >> 8) & 0xff; | |
840 | LastReaderTraceTime[2] = (reader_StartTime >> 16) & 0xff; | |
841 | LastReaderTraceTime[3] = (reader_StartTime >> 24) & 0xff; | |
842 | } | |
843 | ||
844 | ||
845 | static void EmLogTraceTag(uint8_t *tag_data, uint16_t tag_len, uint8_t *tag_Parity, uint32_t ProxToAirDuration) { | |
846 | uint32_t tag_StartTime = LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG; | |
847 | uint32_t tag_EndTime = (LastTimeProxToAirStart + ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG; | |
848 | LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, false); | |
849 | FixLastReaderTraceTime(tag_StartTime); | |
850 | } | |
851 | ||
852 | ||
15c4dc5a | 853 | //----------------------------------------------------------------------------- |
854 | // Wait for commands from reader | |
855 | // Stop when button is pressed | |
de77d4ac | 856 | // Or return true when command is captured |
15c4dc5a | 857 | //----------------------------------------------------------------------------- |
6a1f2d82 | 858 | static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len) |
15c4dc5a | 859 | { |
860 | // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen | |
861 | // only, since we are receiving, not transmitting). | |
862 | // Signal field is off with the appropriate LED | |
863 | LED_D_OFF(); | |
864 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN); | |
865 | ||
866 | // Now run a `software UART' on the stream of incoming samples. | |
6a1f2d82 | 867 | UartInit(received, parity); |
7bc95e2e | 868 | |
869 | // clear RXRDY: | |
870 | uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; | |
15c4dc5a | 871 | |
872 | for(;;) { | |
873 | WDT_HIT(); | |
874 | ||
de77d4ac | 875 | if(BUTTON_PRESS()) return false; |
7bc95e2e | 876 | |
15c4dc5a | 877 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { |
7bc95e2e | 878 | b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; |
879 | if(MillerDecoding(b, 0)) { | |
880 | *len = Uart.len; | |
6e49717b | 881 | EmLogTraceReader(); |
de77d4ac | 882 | return true; |
15c4dc5a | 883 | } |
7bc95e2e | 884 | } |
15c4dc5a | 885 | } |
886 | } | |
28afbd2b | 887 | |
6e49717b | 888 | |
b35e04a7 | 889 | static int EmSend4bitEx(uint8_t resp); |
28afbd2b | 890 | int EmSend4bit(uint8_t resp); |
b35e04a7 | 891 | static int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, uint8_t *par); |
892 | int EmSendCmdEx(uint8_t *resp, uint16_t respLen); | |
893 | int EmSendPrecompiledCmd(tag_response_info_t *response_info); | |
15c4dc5a | 894 | |
ce02f6f9 | 895 | |
6e49717b | 896 | static bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) { |
7bc95e2e | 897 | // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes |
ce02f6f9 | 898 | // This will need the following byte array for a modulation sequence |
899 | // 144 data bits (18 * 8) | |
900 | // 18 parity bits | |
901 | // 2 Start and stop | |
902 | // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA) | |
903 | // 1 just for the case | |
904 | // ----------- + | |
905 | // 166 bytes, since every bit that needs to be send costs us a byte | |
906 | // | |
f71f4deb | 907 | |
908 | ||
ce02f6f9 | 909 | // Prepare the tag modulation bits from the message |
6e49717b | 910 | GetParity(response_info->response, response_info->response_n, &(response_info->par)); |
911 | CodeIso14443aAsTagPar(response_info->response,response_info->response_n, &(response_info->par)); | |
ce02f6f9 | 912 | |
913 | // Make sure we do not exceed the free buffer space | |
914 | if (ToSendMax > max_buffer_size) { | |
915 | Dbprintf("Out of memory, when modulating bits for tag answer:"); | |
6e49717b | 916 | Dbhexdump(response_info->response_n, response_info->response, false); |
ce02f6f9 | 917 | return false; |
918 | } | |
919 | ||
920 | // Copy the byte array, used for this modulation to the buffer position | |
6e49717b | 921 | memcpy(response_info->modulation, ToSend, ToSendMax); |
ce02f6f9 | 922 | |
7bc95e2e | 923 | // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them |
ce02f6f9 | 924 | response_info->modulation_n = ToSendMax; |
7bc95e2e | 925 | response_info->ProxToAirDuration = LastProxToAirDuration; |
ce02f6f9 | 926 | |
927 | return true; | |
928 | } | |
929 | ||
f71f4deb | 930 | |
931 | // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit. | |
932 | // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction) | |
6e49717b | 933 | // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits for the modulation |
f71f4deb | 934 | // -> need 273 bytes buffer |
935 | #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273 | |
936 | ||
6e49717b | 937 | bool prepare_allocated_tag_modulation(tag_response_info_t* response_info, uint8_t **buffer, size_t *max_buffer_size) { |
938 | ||
ce02f6f9 | 939 | // Retrieve and store the current buffer index |
6e49717b | 940 | response_info->modulation = *buffer; |
ce02f6f9 | 941 | |
942 | // Forward the prepare tag modulation function to the inner function | |
6e49717b | 943 | if (prepare_tag_modulation(response_info, *max_buffer_size)) { |
944 | // Update the free buffer offset and the remaining buffer size | |
945 | *buffer += ToSendMax; | |
946 | *max_buffer_size -= ToSendMax; | |
ce02f6f9 | 947 | return true; |
948 | } else { | |
949 | return false; | |
950 | } | |
951 | } | |
952 | ||
15c4dc5a | 953 | //----------------------------------------------------------------------------- |
954 | // Main loop of simulated tag: receive commands from reader, decide what | |
955 | // response to send, and send it. | |
956 | //----------------------------------------------------------------------------- | |
28afbd2b | 957 | void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data) |
15c4dc5a | 958 | { |
81cd0474 | 959 | uint8_t sak; |
960 | ||
961 | // The first response contains the ATQA (note: bytes are transmitted in reverse order). | |
962 | uint8_t response1[2]; | |
963 | ||
964 | switch (tagType) { | |
965 | case 1: { // MIFARE Classic | |
966 | // Says: I am Mifare 1k - original line | |
967 | response1[0] = 0x04; | |
968 | response1[1] = 0x00; | |
969 | sak = 0x08; | |
970 | } break; | |
971 | case 2: { // MIFARE Ultralight | |
972 | // Says: I am a stupid memory tag, no crypto | |
973 | response1[0] = 0x04; | |
974 | response1[1] = 0x00; | |
975 | sak = 0x00; | |
976 | } break; | |
977 | case 3: { // MIFARE DESFire | |
978 | // Says: I am a DESFire tag, ph33r me | |
979 | response1[0] = 0x04; | |
980 | response1[1] = 0x03; | |
981 | sak = 0x20; | |
982 | } break; | |
983 | case 4: { // ISO/IEC 14443-4 | |
984 | // Says: I am a javacard (JCOP) | |
985 | response1[0] = 0x04; | |
986 | response1[1] = 0x00; | |
987 | sak = 0x28; | |
988 | } break; | |
3fe4ff4f | 989 | case 5: { // MIFARE TNP3XXX |
990 | // Says: I am a toy | |
991 | response1[0] = 0x01; | |
992 | response1[1] = 0x0f; | |
993 | sak = 0x01; | |
994 | } break; | |
81cd0474 | 995 | default: { |
996 | Dbprintf("Error: unkown tagtype (%d)",tagType); | |
997 | return; | |
998 | } break; | |
999 | } | |
1000 | ||
1001 | // The second response contains the (mandatory) first 24 bits of the UID | |
c8b6da22 | 1002 | uint8_t response2[5] = {0x00}; |
81cd0474 | 1003 | |
1004 | // Check if the uid uses the (optional) part | |
c8b6da22 | 1005 | uint8_t response2a[5] = {0x00}; |
1006 | ||
81cd0474 | 1007 | if (uid_2nd) { |
1008 | response2[0] = 0x88; | |
1009 | num_to_bytes(uid_1st,3,response2+1); | |
1010 | num_to_bytes(uid_2nd,4,response2a); | |
1011 | response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3]; | |
1012 | ||
1013 | // Configure the ATQA and SAK accordingly | |
1014 | response1[0] |= 0x40; | |
1015 | sak |= 0x04; | |
1016 | } else { | |
1017 | num_to_bytes(uid_1st,4,response2); | |
1018 | // Configure the ATQA and SAK accordingly | |
1019 | response1[0] &= 0xBF; | |
1020 | sak &= 0xFB; | |
1021 | } | |
1022 | ||
1023 | // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID. | |
1024 | response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3]; | |
1025 | ||
1026 | // Prepare the mandatory SAK (for 4 and 7 byte UID) | |
c8b6da22 | 1027 | uint8_t response3[3] = {0x00}; |
81cd0474 | 1028 | response3[0] = sak; |
1029 | ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]); | |
1030 | ||
1031 | // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit | |
c8b6da22 | 1032 | uint8_t response3a[3] = {0x00}; |
81cd0474 | 1033 | response3a[0] = sak & 0xFB; |
1034 | ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]); | |
1035 | ||
254b70a4 | 1036 | uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce |
6a1f2d82 | 1037 | uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS: |
1038 | // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present, | |
1039 | // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1 | |
1040 | // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us) | |
1041 | // TC(1) = 0x02: CID supported, NAD not supported | |
ce02f6f9 | 1042 | ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]); |
1043 | ||
7bc95e2e | 1044 | #define TAG_RESPONSE_COUNT 7 |
1045 | tag_response_info_t responses[TAG_RESPONSE_COUNT] = { | |
1046 | { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type | |
1047 | { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid | |
1048 | { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked | |
1049 | { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1 | |
1050 | { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2 | |
1051 | { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce) | |
1052 | { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS | |
1053 | }; | |
1054 | ||
1055 | // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it | |
1056 | // Such a response is less time critical, so we can prepare them on the fly | |
1057 | #define DYNAMIC_RESPONSE_BUFFER_SIZE 64 | |
1058 | #define DYNAMIC_MODULATION_BUFFER_SIZE 512 | |
1059 | uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE]; | |
1060 | uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE]; | |
1061 | tag_response_info_t dynamic_response_info = { | |
1062 | .response = dynamic_response_buffer, | |
1063 | .response_n = 0, | |
1064 | .modulation = dynamic_modulation_buffer, | |
1065 | .modulation_n = 0 | |
1066 | }; | |
ce02f6f9 | 1067 | |
09ffd16e | 1068 | // We need to listen to the high-frequency, peak-detected path. |
1069 | iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN); | |
1070 | ||
f71f4deb | 1071 | BigBuf_free_keep_EM(); |
1072 | ||
1073 | // allocate buffers: | |
1074 | uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE); | |
1075 | uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE); | |
6e49717b | 1076 | uint8_t *free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE); |
1077 | size_t free_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE; | |
f71f4deb | 1078 | // clear trace |
3000dc4e | 1079 | clear_trace(); |
de77d4ac | 1080 | set_tracing(true); |
f71f4deb | 1081 | |
7bc95e2e | 1082 | // Prepare the responses of the anticollision phase |
ce02f6f9 | 1083 | // there will be not enough time to do this at the moment the reader sends it REQA |
7bc95e2e | 1084 | for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) { |
6e49717b | 1085 | prepare_allocated_tag_modulation(&responses[i], &free_buffer_pointer, &free_buffer_size); |
7bc95e2e | 1086 | } |
15c4dc5a | 1087 | |
7bc95e2e | 1088 | int len = 0; |
15c4dc5a | 1089 | |
1090 | // To control where we are in the protocol | |
1091 | int order = 0; | |
1092 | int lastorder; | |
1093 | ||
1094 | // Just to allow some checks | |
1095 | int happened = 0; | |
1096 | int happened2 = 0; | |
81cd0474 | 1097 | int cmdsRecvd = 0; |
15c4dc5a | 1098 | |
254b70a4 | 1099 | cmdsRecvd = 0; |
7bc95e2e | 1100 | tag_response_info_t* p_response; |
15c4dc5a | 1101 | |
254b70a4 | 1102 | LED_A_ON(); |
1103 | for(;;) { | |
7bc95e2e | 1104 | // Clean receive command buffer |
6a1f2d82 | 1105 | if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) { |
ce02f6f9 | 1106 | DbpString("Button press"); |
254b70a4 | 1107 | break; |
1108 | } | |
7bc95e2e | 1109 | |
1110 | p_response = NULL; | |
1111 | ||
254b70a4 | 1112 | // Okay, look at the command now. |
1113 | lastorder = order; | |
1114 | if(receivedCmd[0] == 0x26) { // Received a REQUEST | |
ce02f6f9 | 1115 | p_response = &responses[0]; order = 1; |
254b70a4 | 1116 | } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP |
ce02f6f9 | 1117 | p_response = &responses[0]; order = 6; |
254b70a4 | 1118 | } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1) |
ce02f6f9 | 1119 | p_response = &responses[1]; order = 2; |
6a1f2d82 | 1120 | } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2) |
ce02f6f9 | 1121 | p_response = &responses[2]; order = 20; |
254b70a4 | 1122 | } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1) |
ce02f6f9 | 1123 | p_response = &responses[3]; order = 3; |
254b70a4 | 1124 | } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2) |
ce02f6f9 | 1125 | p_response = &responses[4]; order = 30; |
254b70a4 | 1126 | } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ |
b35e04a7 | 1127 | EmSendCmdEx(data+(4*receivedCmd[1]),16); |
7bc95e2e | 1128 | // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]); |
5f6d6c90 | 1129 | // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below |
7bc95e2e | 1130 | p_response = NULL; |
254b70a4 | 1131 | } else if(receivedCmd[0] == 0x50) { // Received a HALT |
7bc95e2e | 1132 | p_response = NULL; |
254b70a4 | 1133 | } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request |
ce02f6f9 | 1134 | p_response = &responses[5]; order = 7; |
254b70a4 | 1135 | } else if(receivedCmd[0] == 0xE0) { // Received a RATS request |
7bc95e2e | 1136 | if (tagType == 1 || tagType == 2) { // RATS not supported |
1137 | EmSend4bit(CARD_NACK_NA); | |
1138 | p_response = NULL; | |
1139 | } else { | |
1140 | p_response = &responses[6]; order = 70; | |
1141 | } | |
6a1f2d82 | 1142 | } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication) |
7bc95e2e | 1143 | uint32_t nr = bytes_to_num(receivedCmd,4); |
1144 | uint32_t ar = bytes_to_num(receivedCmd+4,4); | |
1145 | Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar); | |
1146 | } else { | |
1147 | // Check for ISO 14443A-4 compliant commands, look at left nibble | |
1148 | switch (receivedCmd[0]) { | |
1149 | ||
1150 | case 0x0B: | |
1151 | case 0x0A: { // IBlock (command) | |
1152 | dynamic_response_info.response[0] = receivedCmd[0]; | |
1153 | dynamic_response_info.response[1] = 0x00; | |
1154 | dynamic_response_info.response[2] = 0x90; | |
1155 | dynamic_response_info.response[3] = 0x00; | |
1156 | dynamic_response_info.response_n = 4; | |
1157 | } break; | |
1158 | ||
1159 | case 0x1A: | |
1160 | case 0x1B: { // Chaining command | |
1161 | dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1); | |
1162 | dynamic_response_info.response_n = 2; | |
1163 | } break; | |
1164 | ||
1165 | case 0xaa: | |
1166 | case 0xbb: { | |
1167 | dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11; | |
1168 | dynamic_response_info.response_n = 2; | |
1169 | } break; | |
1170 | ||
1171 | case 0xBA: { // | |
1172 | memcpy(dynamic_response_info.response,"\xAB\x00",2); | |
1173 | dynamic_response_info.response_n = 2; | |
1174 | } break; | |
1175 | ||
1176 | case 0xCA: | |
1177 | case 0xC2: { // Readers sends deselect command | |
1178 | memcpy(dynamic_response_info.response,"\xCA\x00",2); | |
1179 | dynamic_response_info.response_n = 2; | |
1180 | } break; | |
1181 | ||
1182 | default: { | |
1183 | // Never seen this command before | |
7bc95e2e | 1184 | Dbprintf("Received unknown command (len=%d):",len); |
1185 | Dbhexdump(len,receivedCmd,false); | |
1186 | // Do not respond | |
1187 | dynamic_response_info.response_n = 0; | |
1188 | } break; | |
1189 | } | |
ce02f6f9 | 1190 | |
7bc95e2e | 1191 | if (dynamic_response_info.response_n > 0) { |
1192 | // Copy the CID from the reader query | |
1193 | dynamic_response_info.response[1] = receivedCmd[1]; | |
ce02f6f9 | 1194 | |
7bc95e2e | 1195 | // Add CRC bytes, always used in ISO 14443A-4 compliant cards |
1196 | AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n); | |
1197 | dynamic_response_info.response_n += 2; | |
ce02f6f9 | 1198 | |
7bc95e2e | 1199 | if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) { |
1200 | Dbprintf("Error preparing tag response"); | |
7bc95e2e | 1201 | break; |
1202 | } | |
1203 | p_response = &dynamic_response_info; | |
1204 | } | |
81cd0474 | 1205 | } |
15c4dc5a | 1206 | |
1207 | // Count number of wakeups received after a halt | |
1208 | if(order == 6 && lastorder == 5) { happened++; } | |
1209 | ||
1210 | // Count number of other messages after a halt | |
1211 | if(order != 6 && lastorder == 5) { happened2++; } | |
1212 | ||
15c4dc5a | 1213 | if(cmdsRecvd > 999) { |
1214 | DbpString("1000 commands later..."); | |
254b70a4 | 1215 | break; |
15c4dc5a | 1216 | } |
ce02f6f9 | 1217 | cmdsRecvd++; |
1218 | ||
1219 | if (p_response != NULL) { | |
b35e04a7 | 1220 | EmSendPrecompiledCmd(p_response); |
7bc95e2e | 1221 | } |
1222 | ||
1223 | if (!tracing) { | |
1224 | Dbprintf("Trace Full. Simulation stopped."); | |
1225 | break; | |
1226 | } | |
1227 | } | |
15c4dc5a | 1228 | |
1229 | Dbprintf("%x %x %x", happened, happened2, cmdsRecvd); | |
1230 | LED_A_OFF(); | |
f71f4deb | 1231 | BigBuf_free_keep_EM(); |
15c4dc5a | 1232 | } |
1233 | ||
9492e0b0 | 1234 | |
1235 | // prepare a delayed transfer. This simply shifts ToSend[] by a number | |
1236 | // of bits specified in the delay parameter. | |
6e49717b | 1237 | static void PrepareDelayedTransfer(uint16_t delay) |
9492e0b0 | 1238 | { |
1239 | uint8_t bitmask = 0; | |
1240 | uint8_t bits_to_shift = 0; | |
1241 | uint8_t bits_shifted = 0; | |
1242 | ||
1243 | delay &= 0x07; | |
1244 | if (delay) { | |
1245 | for (uint16_t i = 0; i < delay; i++) { | |
1246 | bitmask |= (0x01 << i); | |
1247 | } | |
7bc95e2e | 1248 | ToSend[ToSendMax++] = 0x00; |
9492e0b0 | 1249 | for (uint16_t i = 0; i < ToSendMax; i++) { |
1250 | bits_to_shift = ToSend[i] & bitmask; | |
1251 | ToSend[i] = ToSend[i] >> delay; | |
1252 | ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay)); | |
1253 | bits_shifted = bits_to_shift; | |
1254 | } | |
1255 | } | |
1256 | } | |
1257 | ||
7bc95e2e | 1258 | |
1259 | //------------------------------------------------------------------------------------- | |
15c4dc5a | 1260 | // Transmit the command (to the tag) that was placed in ToSend[]. |
9492e0b0 | 1261 | // Parameter timing: |
7bc95e2e | 1262 | // if NULL: transfer at next possible time, taking into account |
47b78133 | 1263 | // request guard time, startup frame guard time and frame delay time |
7bc95e2e | 1264 | // if == 0: transfer immediately and return time of transfer |
9492e0b0 | 1265 | // if != 0: delay transfer until time specified |
7bc95e2e | 1266 | //------------------------------------------------------------------------------------- |
6a1f2d82 | 1267 | static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing) |
15c4dc5a | 1268 | { |
7bc95e2e | 1269 | |
9492e0b0 | 1270 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD); |
e30c654b | 1271 | |
7bc95e2e | 1272 | uint32_t ThisTransferTime = 0; |
e30c654b | 1273 | |
9492e0b0 | 1274 | if (timing) { |
1275 | if(*timing == 0) { // Measure time | |
7bc95e2e | 1276 | *timing = (GetCountSspClk() + 8) & 0xfffffff8; |
9492e0b0 | 1277 | } else { |
1278 | PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks) | |
1279 | } | |
7bc95e2e | 1280 | if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing"); |
1281 | while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks) | |
1282 | LastTimeProxToAirStart = *timing; | |
1283 | } else { | |
1284 | ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8); | |
1285 | while(GetCountSspClk() < ThisTransferTime); | |
1286 | LastTimeProxToAirStart = ThisTransferTime; | |
9492e0b0 | 1287 | } |
1288 | ||
7bc95e2e | 1289 | // clear TXRDY |
1290 | AT91C_BASE_SSC->SSC_THR = SEC_Y; | |
1291 | ||
7bc95e2e | 1292 | uint16_t c = 0; |
9492e0b0 | 1293 | for(;;) { |
1294 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { | |
1295 | AT91C_BASE_SSC->SSC_THR = cmd[c]; | |
1296 | c++; | |
1297 | if(c >= len) { | |
1298 | break; | |
1299 | } | |
1300 | } | |
1301 | } | |
7bc95e2e | 1302 | |
1303 | NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME); | |
15c4dc5a | 1304 | } |
1305 | ||
7bc95e2e | 1306 | |
15c4dc5a | 1307 | //----------------------------------------------------------------------------- |
195af472 | 1308 | // Prepare reader command (in bits, support short frames) to send to FPGA |
15c4dc5a | 1309 | //----------------------------------------------------------------------------- |
6e49717b | 1310 | static void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity) |
15c4dc5a | 1311 | { |
7bc95e2e | 1312 | int i, j; |
1313 | int last; | |
1314 | uint8_t b; | |
e30c654b | 1315 | |
7bc95e2e | 1316 | ToSendReset(); |
e30c654b | 1317 | |
7bc95e2e | 1318 | // Start of Communication (Seq. Z) |
1319 | ToSend[++ToSendMax] = SEC_Z; | |
1320 | LastProxToAirDuration = 8 * (ToSendMax+1) - 6; | |
1321 | last = 0; | |
1322 | ||
1323 | size_t bytecount = nbytes(bits); | |
1324 | // Generate send structure for the data bits | |
1325 | for (i = 0; i < bytecount; i++) { | |
1326 | // Get the current byte to send | |
1327 | b = cmd[i]; | |
1328 | size_t bitsleft = MIN((bits-(i*8)),8); | |
1329 | ||
1330 | for (j = 0; j < bitsleft; j++) { | |
1331 | if (b & 1) { | |
1332 | // Sequence X | |
1333 | ToSend[++ToSendMax] = SEC_X; | |
1334 | LastProxToAirDuration = 8 * (ToSendMax+1) - 2; | |
1335 | last = 1; | |
1336 | } else { | |
1337 | if (last == 0) { | |
1338 | // Sequence Z | |
1339 | ToSend[++ToSendMax] = SEC_Z; | |
1340 | LastProxToAirDuration = 8 * (ToSendMax+1) - 6; | |
1341 | } else { | |
1342 | // Sequence Y | |
1343 | ToSend[++ToSendMax] = SEC_Y; | |
1344 | last = 0; | |
1345 | } | |
1346 | } | |
1347 | b >>= 1; | |
1348 | } | |
1349 | ||
6a1f2d82 | 1350 | // Only transmit parity bit if we transmitted a complete byte |
48ece4a7 | 1351 | if (j == 8 && parity != NULL) { |
7bc95e2e | 1352 | // Get the parity bit |
6a1f2d82 | 1353 | if (parity[i>>3] & (0x80 >> (i&0x0007))) { |
7bc95e2e | 1354 | // Sequence X |
1355 | ToSend[++ToSendMax] = SEC_X; | |
1356 | LastProxToAirDuration = 8 * (ToSendMax+1) - 2; | |
1357 | last = 1; | |
1358 | } else { | |
1359 | if (last == 0) { | |
1360 | // Sequence Z | |
1361 | ToSend[++ToSendMax] = SEC_Z; | |
1362 | LastProxToAirDuration = 8 * (ToSendMax+1) - 6; | |
1363 | } else { | |
1364 | // Sequence Y | |
1365 | ToSend[++ToSendMax] = SEC_Y; | |
1366 | last = 0; | |
1367 | } | |
1368 | } | |
1369 | } | |
1370 | } | |
e30c654b | 1371 | |
7bc95e2e | 1372 | // End of Communication: Logic 0 followed by Sequence Y |
1373 | if (last == 0) { | |
1374 | // Sequence Z | |
1375 | ToSend[++ToSendMax] = SEC_Z; | |
1376 | LastProxToAirDuration = 8 * (ToSendMax+1) - 6; | |
1377 | } else { | |
1378 | // Sequence Y | |
1379 | ToSend[++ToSendMax] = SEC_Y; | |
1380 | last = 0; | |
1381 | } | |
1382 | ToSend[++ToSendMax] = SEC_Y; | |
e30c654b | 1383 | |
7bc95e2e | 1384 | // Convert to length of command: |
1385 | ToSendMax++; | |
15c4dc5a | 1386 | } |
1387 | ||
0c8d25eb | 1388 | |
9ca155ba M |
1389 | //----------------------------------------------------------------------------- |
1390 | // Wait for commands from reader | |
1391 | // Stop when button is pressed (return 1) or field was gone (return 2) | |
1392 | // Or return 0 when command is captured | |
1393 | //----------------------------------------------------------------------------- | |
6e49717b | 1394 | int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity) |
9ca155ba M |
1395 | { |
1396 | *len = 0; | |
1397 | ||
1398 | uint32_t timer = 0, vtime = 0; | |
1399 | int analogCnt = 0; | |
1400 | int analogAVG = 0; | |
1401 | ||
9ca155ba M |
1402 | // Set ADC to read field strength |
1403 | AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST; | |
1404 | AT91C_BASE_ADC->ADC_MR = | |
0c8d25eb | 1405 | ADC_MODE_PRESCALE(63) | |
1406 | ADC_MODE_STARTUP_TIME(1) | | |
1407 | ADC_MODE_SAMPLE_HOLD_TIME(15); | |
9ca155ba M |
1408 | AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF); |
1409 | // start ADC | |
1410 | AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START; | |
1411 | ||
b35e04a7 | 1412 | // Run a 'software UART' on the stream of incoming samples. |
6a1f2d82 | 1413 | UartInit(received, parity); |
7bc95e2e | 1414 | |
b35e04a7 | 1415 | // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN |
1416 | do { | |
1417 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { | |
1418 | AT91C_BASE_SSC->SSC_THR = SEC_F; | |
1419 | uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; (void) b; | |
1420 | } | |
1421 | } while (GetCountSspClk() < LastTimeProxToAirStart + LastProxToAirDuration + (FpgaSendQueueDelay>>3)); | |
1422 | ||
1423 | // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen | |
1424 | // only, since we are receiving, not transmitting). | |
1425 | // Signal field is off with the appropriate LED | |
1426 | LED_D_OFF(); | |
1427 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN); | |
1428 | ||
9ca155ba M |
1429 | for(;;) { |
1430 | WDT_HIT(); | |
1431 | ||
1432 | if (BUTTON_PRESS()) return 1; | |
1433 | ||
1434 | // test if the field exists | |
1435 | if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) { | |
1436 | analogCnt++; | |
1437 | analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF]; | |
1438 | AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START; | |
1439 | if (analogCnt >= 32) { | |
0c8d25eb | 1440 | if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) { |
9ca155ba M |
1441 | vtime = GetTickCount(); |
1442 | if (!timer) timer = vtime; | |
1443 | // 50ms no field --> card to idle state | |
1444 | if (vtime - timer > 50) return 2; | |
1445 | } else | |
1446 | if (timer) timer = 0; | |
1447 | analogCnt = 0; | |
1448 | analogAVG = 0; | |
1449 | } | |
1450 | } | |
7bc95e2e | 1451 | |
9ca155ba | 1452 | // receive and test the miller decoding |
7bc95e2e | 1453 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { |
b35e04a7 | 1454 | uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; |
7bc95e2e | 1455 | if(MillerDecoding(b, 0)) { |
1456 | *len = Uart.len; | |
6e49717b | 1457 | EmLogTraceReader(); |
9ca155ba M |
1458 | return 0; |
1459 | } | |
7bc95e2e | 1460 | } |
1461 | ||
9ca155ba M |
1462 | } |
1463 | } | |
1464 | ||
9ca155ba | 1465 | |
b35e04a7 | 1466 | static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen) |
7bc95e2e | 1467 | { |
1468 | uint8_t b; | |
1469 | uint16_t i = 0; | |
b35e04a7 | 1470 | bool correctionNeeded; |
1471 | ||
9ca155ba M |
1472 | // Modulate Manchester |
1473 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD); | |
7bc95e2e | 1474 | |
1475 | // include correction bit if necessary | |
b35e04a7 | 1476 | if (Uart.bitCount == 7) |
1477 | { | |
1478 | // Short tags (7 bits) don't have parity, determine the correct value from MSB | |
1479 | correctionNeeded = Uart.output[0] & 0x40; | |
1480 | } | |
1481 | else | |
1482 | { | |
1483 | // Look at the last parity bit | |
1484 | correctionNeeded = Uart.parity[(Uart.len-1)/8] & (0x80 >> ((Uart.len-1) & 7)); | |
7bc95e2e | 1485 | } |
b35e04a7 | 1486 | |
7bc95e2e | 1487 | if(correctionNeeded) { |
9ca155ba M |
1488 | // 1236, so correction bit needed |
1489 | i = 0; | |
7bc95e2e | 1490 | } else { |
1491 | i = 1; | |
9ca155ba | 1492 | } |
7bc95e2e | 1493 | |
d714d3ef | 1494 | // clear receiving shift register and holding register |
7bc95e2e | 1495 | while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)); |
1496 | b = AT91C_BASE_SSC->SSC_RHR; (void) b; | |
1497 | while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)); | |
1498 | b = AT91C_BASE_SSC->SSC_RHR; (void) b; | |
9ca155ba | 1499 | |
7bc95e2e | 1500 | // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line) |
1501 | for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never | |
1502 | while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)); | |
1503 | if (AT91C_BASE_SSC->SSC_RHR) break; | |
1504 | } | |
1505 | ||
6e49717b | 1506 | LastTimeProxToAirStart = (GetCountSspClk() & 0xfffffff8) + (correctionNeeded?8:0); |
7bc95e2e | 1507 | |
9ca155ba | 1508 | // send cycle |
bb42a03e | 1509 | for(; i < respLen; ) { |
9ca155ba | 1510 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { |
7bc95e2e | 1511 | AT91C_BASE_SSC->SSC_THR = resp[i++]; |
1512 | FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR; | |
9ca155ba | 1513 | } |
7bc95e2e | 1514 | |
9ca155ba M |
1515 | if(BUTTON_PRESS()) { |
1516 | break; | |
1517 | } | |
1518 | } | |
1519 | ||
1520 | return 0; | |
1521 | } | |
1522 | ||
6e49717b | 1523 | |
b35e04a7 | 1524 | static int EmSend4bitEx(uint8_t resp){ |
7bc95e2e | 1525 | Code4bitAnswerAsTag(resp); |
b35e04a7 | 1526 | int res = EmSendCmd14443aRaw(ToSend, ToSendMax); |
7bc95e2e | 1527 | // do the tracing for the previous reader request and this tag answer: |
6e49717b | 1528 | EmLogTraceTag(&resp, 1, NULL, LastProxToAirDuration); |
0a39986e | 1529 | return res; |
9ca155ba M |
1530 | } |
1531 | ||
6e49717b | 1532 | |
8f51ddb0 | 1533 | int EmSend4bit(uint8_t resp){ |
b35e04a7 | 1534 | return EmSend4bitEx(resp); |
8f51ddb0 M |
1535 | } |
1536 | ||
6e49717b | 1537 | |
b35e04a7 | 1538 | static int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, uint8_t *par){ |
7bc95e2e | 1539 | CodeIso14443aAsTagPar(resp, respLen, par); |
b35e04a7 | 1540 | int res = EmSendCmd14443aRaw(ToSend, ToSendMax); |
7bc95e2e | 1541 | // do the tracing for the previous reader request and this tag answer: |
6e49717b | 1542 | EmLogTraceTag(resp, respLen, par, LastProxToAirDuration); |
8f51ddb0 M |
1543 | return res; |
1544 | } | |
1545 | ||
6e49717b | 1546 | |
b35e04a7 | 1547 | int EmSendCmdEx(uint8_t *resp, uint16_t respLen){ |
6a1f2d82 | 1548 | uint8_t par[MAX_PARITY_SIZE]; |
1549 | GetParity(resp, respLen, par); | |
b35e04a7 | 1550 | return EmSendCmdExPar(resp, respLen, par); |
8f51ddb0 M |
1551 | } |
1552 | ||
6e49717b | 1553 | |
6a1f2d82 | 1554 | int EmSendCmd(uint8_t *resp, uint16_t respLen){ |
1555 | uint8_t par[MAX_PARITY_SIZE]; | |
1556 | GetParity(resp, respLen, par); | |
b35e04a7 | 1557 | return EmSendCmdExPar(resp, respLen, par); |
8f51ddb0 M |
1558 | } |
1559 | ||
6e49717b | 1560 | |
6a1f2d82 | 1561 | int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){ |
b35e04a7 | 1562 | return EmSendCmdExPar(resp, respLen, par); |
7bc95e2e | 1563 | } |
1564 | ||
6e49717b | 1565 | |
b35e04a7 | 1566 | int EmSendPrecompiledCmd(tag_response_info_t *response_info) { |
1567 | int ret = EmSendCmd14443aRaw(response_info->modulation, response_info->modulation_n); | |
6e49717b | 1568 | // do the tracing for the previous reader request and this tag answer: |
1569 | EmLogTraceTag(response_info->response, response_info->response_n, &(response_info->par), response_info->ProxToAirDuration); | |
1570 | return ret; | |
9ca155ba M |
1571 | } |
1572 | ||
6e49717b | 1573 | |
15c4dc5a | 1574 | //----------------------------------------------------------------------------- |
1575 | // Wait a certain time for tag response | |
de77d4ac | 1576 | // If a response is captured return true |
1577 | // If it takes too long return false | |
15c4dc5a | 1578 | //----------------------------------------------------------------------------- |
6a1f2d82 | 1579 | static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset) |
15c4dc5a | 1580 | { |
52bfb955 | 1581 | uint32_t c; |
e691fc45 | 1582 | |
15c4dc5a | 1583 | // Set FPGA mode to "reader listen mode", no modulation (listen |
534983d7 | 1584 | // only, since we are receiving, not transmitting). |
1585 | // Signal field is on with the appropriate LED | |
1586 | LED_D_ON(); | |
1587 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN); | |
1c611bbd | 1588 | |
534983d7 | 1589 | // Now get the answer from the card |
6a1f2d82 | 1590 | DemodInit(receivedResponse, receivedResponsePar); |
15c4dc5a | 1591 | |
7bc95e2e | 1592 | // clear RXRDY: |
1593 | uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; | |
0c8d25eb | 1594 | |
15c4dc5a | 1595 | c = 0; |
1596 | for(;;) { | |
534983d7 | 1597 | WDT_HIT(); |
15c4dc5a | 1598 | |
534983d7 | 1599 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { |
534983d7 | 1600 | b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; |
7bc95e2e | 1601 | if(ManchesterDecoding(b, offset, 0)) { |
1602 | NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD); | |
de77d4ac | 1603 | return true; |
19a700a8 | 1604 | } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) { |
de77d4ac | 1605 | return false; |
15c4dc5a | 1606 | } |
534983d7 | 1607 | } |
1608 | } | |
15c4dc5a | 1609 | } |
1610 | ||
48ece4a7 | 1611 | |
6a1f2d82 | 1612 | void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing) |
15c4dc5a | 1613 | { |
6a1f2d82 | 1614 | CodeIso14443aBitsAsReaderPar(frame, bits, par); |
dfc3c505 | 1615 | |
7bc95e2e | 1616 | // Send command to tag |
1617 | TransmitFor14443a(ToSend, ToSendMax, timing); | |
1618 | if(trigger) | |
1619 | LED_A_ON(); | |
dfc3c505 | 1620 | |
7bc95e2e | 1621 | // Log reader command in trace buffer |
1622 | if (tracing) { | |
de77d4ac | 1623 | LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, true); |
7bc95e2e | 1624 | } |
15c4dc5a | 1625 | } |
1626 | ||
48ece4a7 | 1627 | |
6a1f2d82 | 1628 | void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing) |
dfc3c505 | 1629 | { |
6a1f2d82 | 1630 | ReaderTransmitBitsPar(frame, len*8, par, timing); |
dfc3c505 | 1631 | } |
15c4dc5a | 1632 | |
48ece4a7 | 1633 | |
6e49717b | 1634 | static void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing) |
e691fc45 | 1635 | { |
1636 | // Generate parity and redirect | |
6a1f2d82 | 1637 | uint8_t par[MAX_PARITY_SIZE]; |
1638 | GetParity(frame, len/8, par); | |
1639 | ReaderTransmitBitsPar(frame, len, par, timing); | |
e691fc45 | 1640 | } |
1641 | ||
48ece4a7 | 1642 | |
6a1f2d82 | 1643 | void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing) |
15c4dc5a | 1644 | { |
1645 | // Generate parity and redirect | |
6a1f2d82 | 1646 | uint8_t par[MAX_PARITY_SIZE]; |
1647 | GetParity(frame, len, par); | |
1648 | ReaderTransmitBitsPar(frame, len*8, par, timing); | |
15c4dc5a | 1649 | } |
1650 | ||
6e49717b | 1651 | |
1652 | static int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity) | |
e691fc45 | 1653 | { |
de77d4ac | 1654 | if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return false; |
7bc95e2e | 1655 | if (tracing) { |
de77d4ac | 1656 | LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, false); |
7bc95e2e | 1657 | } |
e691fc45 | 1658 | return Demod.len; |
1659 | } | |
1660 | ||
6e49717b | 1661 | |
6a1f2d82 | 1662 | int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity) |
15c4dc5a | 1663 | { |
de77d4ac | 1664 | if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return false; |
7bc95e2e | 1665 | if (tracing) { |
de77d4ac | 1666 | LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, false); |
7bc95e2e | 1667 | } |
e691fc45 | 1668 | return Demod.len; |
f89c7050 M |
1669 | } |
1670 | ||
47b78133 | 1671 | |
1672 | static void iso14a_set_ATS_times(uint8_t *ats) { | |
1673 | ||
1674 | uint8_t tb1; | |
1675 | uint8_t fwi, sfgi; | |
1676 | uint32_t fwt, sfgt; | |
1677 | ||
1678 | if (ats[0] > 1) { // there is a format byte T0 | |
1679 | if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1) | |
1680 | if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1) | |
1681 | tb1 = ats[3]; | |
1682 | } else { | |
1683 | tb1 = ats[2]; | |
1684 | } | |
1685 | fwi = (tb1 & 0xf0) >> 4; // frame waiting time integer (FWI) | |
1686 | if (fwi != 15) { | |
1687 | fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc | |
1688 | iso14a_set_timeout(fwt/(8*16)); | |
1689 | } | |
1690 | sfgi = tb1 & 0x0f; // startup frame guard time integer (SFGI) | |
1691 | if (sfgi != 0 && sfgi != 15) { | |
1692 | sfgt = 256 * 16 * (1 << sfgi); // startup frame guard time (SFGT) in 1/fc | |
1693 | NextTransferTime = MAX(NextTransferTime, Demod.endTime + (sfgt - DELAY_AIR2ARM_AS_READER - DELAY_ARM2AIR_AS_READER)/16); | |
1694 | } | |
1695 | } | |
1696 | } | |
1697 | } | |
1698 | ||
1699 | ||
1700 | static int GetATQA(uint8_t *resp, uint8_t *resp_par) { | |
1701 | ||
1702 | #define WUPA_RETRY_TIMEOUT 10 // 10ms | |
1703 | uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP | |
1704 | ||
1705 | uint32_t save_iso14a_timeout = iso14a_get_timeout(); | |
1706 | iso14a_set_timeout(1236/(16*8)+1); // response to WUPA is expected at exactly 1236/fc. No need to wait longer. | |
1707 | ||
1708 | uint32_t start_time = GetTickCount(); | |
1709 | int len; | |
1710 | ||
1711 | // we may need several tries if we did send an unknown command or a wrong authentication before... | |
1712 | do { | |
1713 | // Broadcast for a card, WUPA (0x52) will force response from all cards in the field | |
1714 | ReaderTransmitBitsPar(wupa, 7, NULL, NULL); | |
1715 | // Receive the ATQA | |
1716 | len = ReaderReceive(resp, resp_par); | |
1717 | } while (len == 0 && GetTickCount() <= start_time + WUPA_RETRY_TIMEOUT); | |
1718 | ||
1719 | iso14a_set_timeout(save_iso14a_timeout); | |
1720 | return len; | |
1721 | } | |
1722 | ||
1723 | ||
de77d4ac | 1724 | // performs iso14443a anticollision (optional) and card select procedure |
1725 | // fills the uid and cuid pointer unless NULL | |
1726 | // fills the card info record unless NULL | |
1727 | // if anticollision is false, then the UID must be provided in uid_ptr[] | |
1728 | // and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID) | |
c04a4b60 | 1729 | // requests ATS unless no_rats is true |
1730 | int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr, bool anticollision, uint8_t num_cascades, bool no_rats) { | |
6a1f2d82 | 1731 | uint8_t sel_all[] = { 0x93,0x20 }; |
1732 | uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; | |
1733 | uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0 | |
f71f4deb | 1734 | uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller |
1735 | uint8_t resp_par[MAX_PARITY_SIZE]; | |
6a1f2d82 | 1736 | byte_t uid_resp[4]; |
1737 | size_t uid_resp_len; | |
1738 | ||
1739 | uint8_t sak = 0x04; // cascade uid | |
1740 | int cascade_level = 0; | |
1741 | int len; | |
1742 | ||
618c220c OM |
1743 | // init card struct |
1744 | if(p_hi14a_card) { | |
1745 | p_hi14a_card->uidlen = 0; | |
1746 | memset(p_hi14a_card->uid, 0, 10); | |
1747 | p_hi14a_card->ats_len = 0; | |
1748 | } | |
1749 | ||
47b78133 | 1750 | if (!GetATQA(resp, resp_par)) { |
1751 | return 0; | |
1752 | } | |
6a1f2d82 | 1753 | |
1754 | if(p_hi14a_card) { | |
1755 | memcpy(p_hi14a_card->atqa, resp, 2); | |
6a1f2d82 | 1756 | } |
5f6d6c90 | 1757 | |
de77d4ac | 1758 | if (anticollision) { |
1759 | // clear uid | |
1760 | if (uid_ptr) { | |
1761 | memset(uid_ptr,0,10); | |
1762 | } | |
6a1f2d82 | 1763 | } |
79a73ab2 | 1764 | |
ee1eadee | 1765 | // check for proprietary anticollision: |
1766 | if ((resp[0] & 0x1F) == 0) { | |
1767 | return 3; | |
1768 | } | |
1769 | ||
6a1f2d82 | 1770 | // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in |
1771 | // which case we need to make a cascade 2 request and select - this is a long UID | |
1772 | // While the UID is not complete, the 3nd bit (from the right) is set in the SAK. | |
1773 | for(; sak & 0x04; cascade_level++) { | |
1774 | // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97) | |
1775 | sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2; | |
1776 | ||
de77d4ac | 1777 | if (anticollision) { |
1778 | // SELECT_ALL | |
1779 | ReaderTransmit(sel_all, sizeof(sel_all), NULL); | |
1780 | if (!ReaderReceive(resp, resp_par)) return 0; | |
1781 | ||
1782 | if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit | |
1783 | memset(uid_resp, 0, 4); | |
1784 | uint16_t uid_resp_bits = 0; | |
1785 | uint16_t collision_answer_offset = 0; | |
1786 | // anti-collision-loop: | |
1787 | while (Demod.collisionPos) { | |
1788 | Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos); | |
1789 | for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point | |
1790 | uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01; | |
1791 | uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8); | |
1792 | } | |
1793 | uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position | |
1794 | uid_resp_bits++; | |
1795 | // construct anticollosion command: | |
1796 | sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits | |
1797 | for (uint16_t i = 0; i <= uid_resp_bits/8; i++) { | |
1798 | sel_uid[2+i] = uid_resp[i]; | |
1799 | } | |
1800 | collision_answer_offset = uid_resp_bits%8; | |
1801 | ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL); | |
1802 | if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0; | |
6a1f2d82 | 1803 | } |
de77d4ac | 1804 | // finally, add the last bits and BCC of the UID |
1805 | for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) { | |
1806 | uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01; | |
1807 | uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8); | |
6a1f2d82 | 1808 | } |
de77d4ac | 1809 | |
1810 | } else { // no collision, use the response to SELECT_ALL as current uid | |
1811 | memcpy(uid_resp, resp, 4); | |
e691fc45 | 1812 | } |
de77d4ac | 1813 | } else { |
1814 | if (cascade_level < num_cascades - 1) { | |
1815 | uid_resp[0] = 0x88; | |
1816 | memcpy(uid_resp+1, uid_ptr+cascade_level*3, 3); | |
1817 | } else { | |
1818 | memcpy(uid_resp, uid_ptr+cascade_level*3, 4); | |
e691fc45 | 1819 | } |
6a1f2d82 | 1820 | } |
1821 | uid_resp_len = 4; | |
5f6d6c90 | 1822 | |
6a1f2d82 | 1823 | // calculate crypto UID. Always use last 4 Bytes. |
1824 | if(cuid_ptr) { | |
1825 | *cuid_ptr = bytes_to_num(uid_resp, 4); | |
1826 | } | |
e30c654b | 1827 | |
6a1f2d82 | 1828 | // Construct SELECT UID command |
1829 | sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC) | |
de77d4ac | 1830 | memcpy(sel_uid+2, uid_resp, 4); // the UID received during anticollision, or the provided UID |
6a1f2d82 | 1831 | sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC |
1832 | AppendCrc14443a(sel_uid, 7); // calculate and add CRC | |
1833 | ReaderTransmit(sel_uid, sizeof(sel_uid), NULL); | |
1834 | ||
1835 | // Receive the SAK | |
1836 | if (!ReaderReceive(resp, resp_par)) return 0; | |
1837 | sak = resp[0]; | |
de77d4ac | 1838 | |
1839 | // Test if more parts of the uid are coming | |
6a1f2d82 | 1840 | if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) { |
1841 | // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of: | |
1842 | // http://www.nxp.com/documents/application_note/AN10927.pdf | |
6a1f2d82 | 1843 | uid_resp[0] = uid_resp[1]; |
1844 | uid_resp[1] = uid_resp[2]; | |
1845 | uid_resp[2] = uid_resp[3]; | |
6a1f2d82 | 1846 | uid_resp_len = 3; |
1847 | } | |
5f6d6c90 | 1848 | |
de77d4ac | 1849 | if(uid_ptr && anticollision) { |
6a1f2d82 | 1850 | memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len); |
1851 | } | |
5f6d6c90 | 1852 | |
6a1f2d82 | 1853 | if(p_hi14a_card) { |
1854 | memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len); | |
1855 | p_hi14a_card->uidlen += uid_resp_len; | |
1856 | } | |
1857 | } | |
79a73ab2 | 1858 | |
6a1f2d82 | 1859 | if(p_hi14a_card) { |
1860 | p_hi14a_card->sak = sak; | |
6a1f2d82 | 1861 | } |
534983d7 | 1862 | |
7376da5c | 1863 | // PICC compilant with iso14443a-4 ---> (SAK & 0x20 != 0) |
3fe4ff4f | 1864 | if( (sak & 0x20) == 0) return 2; |
534983d7 | 1865 | |
c04a4b60 | 1866 | if (!no_rats) { |
1867 | // Request for answer to select | |
1868 | AppendCrc14443a(rats, 2); | |
1869 | ReaderTransmit(rats, sizeof(rats), NULL); | |
1c611bbd | 1870 | |
c04a4b60 | 1871 | if (!(len = ReaderReceive(resp, resp_par))) return 0; |
5191b3d1 | 1872 | |
c04a4b60 | 1873 | if(p_hi14a_card) { |
1874 | memcpy(p_hi14a_card->ats, resp, len); | |
1875 | p_hi14a_card->ats_len = len; | |
1876 | } | |
19a700a8 | 1877 | |
c04a4b60 | 1878 | // reset the PCB block number |
1879 | iso14_pcb_blocknum = 0; | |
19a700a8 | 1880 | |
47b78133 | 1881 | // set default timeout and delay next transfer based on ATS |
1882 | iso14a_set_ATS_times(resp); | |
1883 | ||
c04a4b60 | 1884 | } |
6a1f2d82 | 1885 | return 1; |
7e758047 | 1886 | } |
15c4dc5a | 1887 | |
6e49717b | 1888 | |
7bc95e2e | 1889 | void iso14443a_setup(uint8_t fpga_minor_mode) { |
7cc204bf | 1890 | FpgaDownloadAndGo(FPGA_BITSTREAM_HF); |
9492e0b0 | 1891 | // Set up the synchronous serial port |
1892 | FpgaSetupSsc(); | |
7bc95e2e | 1893 | // connect Demodulated Signal to ADC: |
7e758047 | 1894 | SetAdcMuxFor(GPIO_MUXSEL_HIPKD); |
e30c654b | 1895 | |
7e758047 | 1896 | // Signal field is on with the appropriate LED |
7bc95e2e | 1897 | if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD |
1898 | || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) { | |
1899 | LED_D_ON(); | |
1900 | } else { | |
1901 | LED_D_OFF(); | |
1902 | } | |
1903 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode); | |
534983d7 | 1904 | |
7bc95e2e | 1905 | // Start the timer |
1906 | StartCountSspClk(); | |
1907 | ||
1908 | DemodReset(); | |
1909 | UartReset(); | |
1910 | NextTransferTime = 2*DELAY_ARM2AIR_AS_READER; | |
6e49717b | 1911 | iso14a_set_timeout(1060); // 10ms default |
7e758047 | 1912 | } |
15c4dc5a | 1913 | |
ba4f95b4 | 1914 | /* Peter Fillmore 2015 |
1915 | Added card id field to the function | |
1916 | info from ISO14443A standard | |
1917 | b1 = Block Number | |
1918 | b2 = RFU (always 1) | |
1919 | b3 = depends on block | |
1920 | b4 = Card ID following if set to 1 | |
1921 | b5 = depends on block type | |
1922 | b6 = depends on block type | |
1923 | b7,b8 = block type. | |
1924 | Coding of I-BLOCK: | |
1925 | b8 b7 b6 b5 b4 b3 b2 b1 | |
1926 | 0 0 0 x x x 1 x | |
1927 | b5 = chaining bit | |
1928 | Coding of R-block: | |
1929 | b8 b7 b6 b5 b4 b3 b2 b1 | |
1930 | 1 0 1 x x 0 1 x | |
1931 | b5 = ACK/NACK | |
1932 | Coding of S-block: | |
1933 | b8 b7 b6 b5 b4 b3 b2 b1 | |
1934 | 1 1 x x x 0 1 0 | |
1935 | b5,b6 = 00 - DESELECT | |
1936 | 11 - WTX | |
1937 | */ | |
6a1f2d82 | 1938 | int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) { |
1939 | uint8_t parity[MAX_PARITY_SIZE]; | |
b7d3e899 | 1940 | uint8_t real_cmd[cmd_len + 4]; |
1941 | ||
1942 | // ISO 14443 APDU frame: PCB [CID] [NAD] APDU CRC PCB=0x02 | |
1943 | real_cmd[0] = 0x02; // bnr,nad,cid,chn=0; i-block(0x00) | |
b0127e65 | 1944 | // put block number into the PCB |
1945 | real_cmd[0] |= iso14_pcb_blocknum; | |
b7d3e899 | 1946 | memcpy(real_cmd + 1, cmd, cmd_len); |
1947 | AppendCrc14443a(real_cmd, cmd_len + 1); | |
534983d7 | 1948 | |
b7d3e899 | 1949 | ReaderTransmit(real_cmd, cmd_len + 3, NULL); |
1950 | ||
6a1f2d82 | 1951 | size_t len = ReaderReceive(data, parity); |
1952 | uint8_t *data_bytes = (uint8_t *) data; | |
b7d3e899 | 1953 | |
1954 | if (!len) { | |
b0127e65 | 1955 | return 0; //DATA LINK ERROR |
b7d3e899 | 1956 | } else{ |
a63505c9 | 1957 | // S-Block WTX |
1958 | while((data_bytes[0] & 0xF2) == 0xF2) { | |
7c7327e7 | 1959 | uint32_t save_iso14a_timeout = iso14a_get_timeout(); |
db68bcdb | 1960 | // temporarily increase timeout |
7c7327e7 | 1961 | iso14a_set_timeout(MAX((data_bytes[1] & 0x3f) * save_iso14a_timeout, MAX_ISO14A_TIMEOUT)); |
a63505c9 | 1962 | // Transmit WTX back |
1963 | // byte1 - WTXM [1..59]. command FWT=FWT*WTXM | |
1964 | data_bytes[1] = data_bytes[1] & 0x3f; // 2 high bits mandatory set to 0b | |
1965 | // now need to fix CRC. | |
1966 | AppendCrc14443a(data_bytes, len - 2); | |
1967 | // transmit S-Block | |
1968 | ReaderTransmit(data_bytes, len, NULL); | |
db68bcdb | 1969 | // retrieve the result again (with increased timeout) |
a63505c9 | 1970 | len = ReaderReceive(data, parity); |
1971 | data_bytes = data; | |
db68bcdb | 1972 | // restore timeout |
7c7327e7 | 1973 | iso14a_set_timeout(save_iso14a_timeout); |
a63505c9 | 1974 | } |
1975 | ||
1976 | // if we received an I- or R(ACK)-Block with a block number equal to the | |
1977 | // current block number, toggle the current block number | |
b7d3e899 | 1978 | if (len >= 3 // PCB+CRC = 3 bytes |
b0127e65 | 1979 | && ((data_bytes[0] & 0xC0) == 0 // I-Block |
1980 | || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0 | |
1981 | && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers | |
b7d3e899 | 1982 | { |
1983 | iso14_pcb_blocknum ^= 1; | |
1984 | } | |
b0127e65 | 1985 | |
b7d3e899 | 1986 | // crc check |
1987 | if (len >=3 && !CheckCrc14443(CRC_14443_A, data_bytes, len)) { | |
1988 | return -1; | |
1989 | } | |
1990 | ||
1991 | } | |
1992 | ||
1993 | // cut frame byte | |
1994 | len -= 1; | |
1995 | // memmove(data_bytes, data_bytes + 1, len); | |
1996 | for (int i = 0; i < len; i++) | |
1997 | data_bytes[i] = data_bytes[i + 1]; | |
1998 | ||
534983d7 | 1999 | return len; |
2000 | } | |
2001 | ||
6e49717b | 2002 | |
7e758047 | 2003 | //----------------------------------------------------------------------------- |
2004 | // Read an ISO 14443a tag. Send out commands and store answers. | |
2005 | // | |
2006 | //----------------------------------------------------------------------------- | |
7bc95e2e | 2007 | void ReaderIso14443a(UsbCommand *c) |
7e758047 | 2008 | { |
534983d7 | 2009 | iso14a_command_t param = c->arg[0]; |
7bc95e2e | 2010 | uint8_t *cmd = c->d.asBytes; |
04bc1c66 | 2011 | size_t len = c->arg[1] & 0xffff; |
2012 | size_t lenbits = c->arg[1] >> 16; | |
2013 | uint32_t timeout = c->arg[2]; | |
9492e0b0 | 2014 | uint32_t arg0 = 0; |
618c220c | 2015 | byte_t buf[USB_CMD_DATA_SIZE] = {0}; |
6a1f2d82 | 2016 | uint8_t par[MAX_PARITY_SIZE]; |
f1a983a3 | 2017 | bool cantSELECT = false; |
902cb3c0 | 2018 | |
eb6e8de4 | 2019 | set_tracing(true); |
2020 | ||
2021 | if(param & ISO14A_CLEAR_TRACE) { | |
3000dc4e | 2022 | clear_trace(); |
5f6d6c90 | 2023 | } |
e691fc45 | 2024 | |
79a73ab2 | 2025 | if(param & ISO14A_REQUEST_TRIGGER) { |
de77d4ac | 2026 | iso14a_set_trigger(true); |
9492e0b0 | 2027 | } |
15c4dc5a | 2028 | |
534983d7 | 2029 | if(param & ISO14A_CONNECT) { |
f1a983a3 | 2030 | LED_A_ON(); |
7bc95e2e | 2031 | iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN); |
5f6d6c90 | 2032 | if(!(param & ISO14A_NO_SELECT)) { |
2033 | iso14a_card_select_t *card = (iso14a_card_select_t*)buf; | |
c04a4b60 | 2034 | arg0 = iso14443a_select_card(NULL, card, NULL, true, 0, param & ISO14A_NO_RATS); |
f1a983a3 | 2035 | |
2036 | // if we cant select then we cant send data | |
499df908 | 2037 | if (arg0 != 1 && arg0 != 2) { |
2038 | // 1 - all is OK with ATS, 2 - without ATS | |
2039 | cantSELECT = true; | |
2040 | } | |
f1a983a3 | 2041 | |
2042 | LED_B_ON(); | |
5f6d6c90 | 2043 | cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t)); |
f1a983a3 | 2044 | LED_B_OFF(); |
5f6d6c90 | 2045 | } |
534983d7 | 2046 | } |
e30c654b | 2047 | |
534983d7 | 2048 | if(param & ISO14A_SET_TIMEOUT) { |
04bc1c66 | 2049 | iso14a_set_timeout(timeout); |
534983d7 | 2050 | } |
e30c654b | 2051 | |
f1a983a3 | 2052 | if(param & ISO14A_APDU && !cantSELECT) { |
902cb3c0 | 2053 | arg0 = iso14_apdu(cmd, len, buf); |
f1a983a3 | 2054 | LED_B_ON(); |
b7d3e899 | 2055 | cmd_send(CMD_ACK, arg0, 0, 0, buf, sizeof(buf)); |
f1a983a3 | 2056 | LED_B_OFF(); |
534983d7 | 2057 | } |
e30c654b | 2058 | |
f1a983a3 | 2059 | if(param & ISO14A_RAW && !cantSELECT) { |
534983d7 | 2060 | if(param & ISO14A_APPEND_CRC) { |
48ece4a7 | 2061 | if(param & ISO14A_TOPAZMODE) { |
2062 | AppendCrc14443b(cmd,len); | |
2063 | } else { | |
2064 | AppendCrc14443a(cmd,len); | |
2065 | } | |
534983d7 | 2066 | len += 2; |
c7324bef | 2067 | if (lenbits) lenbits += 16; |
15c4dc5a | 2068 | } |
48ece4a7 | 2069 | if(lenbits>0) { // want to send a specific number of bits (e.g. short commands) |
2070 | if(param & ISO14A_TOPAZMODE) { | |
2071 | int bits_to_send = lenbits; | |
2072 | uint16_t i = 0; | |
2073 | ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity | |
2074 | bits_to_send -= 7; | |
2075 | while (bits_to_send > 0) { | |
2076 | ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity | |
2077 | bits_to_send -= 8; | |
2078 | } | |
2079 | } else { | |
2080 | GetParity(cmd, lenbits/8, par); | |
2081 | ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity | |
2082 | } | |
2083 | } else { // want to send complete bytes only | |
2084 | if(param & ISO14A_TOPAZMODE) { | |
2085 | uint16_t i = 0; | |
2086 | ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy | |
2087 | while (i < len) { | |
2088 | ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy | |
2089 | } | |
2090 | } else { | |
2091 | ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity | |
2092 | } | |
5f6d6c90 | 2093 | } |
6a1f2d82 | 2094 | arg0 = ReaderReceive(buf, par); |
f1a983a3 | 2095 | |
2096 | LED_B_ON(); | |
9492e0b0 | 2097 | cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf)); |
f1a983a3 | 2098 | LED_B_OFF(); |
534983d7 | 2099 | } |
15c4dc5a | 2100 | |
79a73ab2 | 2101 | if(param & ISO14A_REQUEST_TRIGGER) { |
de77d4ac | 2102 | iso14a_set_trigger(false); |
9492e0b0 | 2103 | } |
15c4dc5a | 2104 | |
79a73ab2 | 2105 | if(param & ISO14A_NO_DISCONNECT) { |
534983d7 | 2106 | return; |
9492e0b0 | 2107 | } |
15c4dc5a | 2108 | |
15c4dc5a | 2109 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
2110 | LEDsoff(); | |
15c4dc5a | 2111 | } |
b0127e65 | 2112 | |
1c611bbd | 2113 | |
1c611bbd | 2114 | // Determine the distance between two nonces. |
2115 | // Assume that the difference is small, but we don't know which is first. | |
2116 | // Therefore try in alternating directions. | |
6e49717b | 2117 | static int32_t dist_nt(uint32_t nt1, uint32_t nt2) { |
1c611bbd | 2118 | |
2119 | uint16_t i; | |
2120 | uint32_t nttmp1, nttmp2; | |
e772353f | 2121 | |
1c611bbd | 2122 | if (nt1 == nt2) return 0; |
2123 | ||
2124 | nttmp1 = nt1; | |
2125 | nttmp2 = nt2; | |
2126 | ||
2127 | for (i = 1; i < 32768; i++) { | |
2128 | nttmp1 = prng_successor(nttmp1, 1); | |
2129 | if (nttmp1 == nt2) return i; | |
2130 | nttmp2 = prng_successor(nttmp2, 1); | |
dc8ba239 | 2131 | if (nttmp2 == nt1) return -i; |
1c611bbd | 2132 | } |
2133 | ||
2134 | return(-99999); // either nt1 or nt2 are invalid nonces | |
e772353f | 2135 | } |
2136 | ||
e772353f | 2137 | |
1c611bbd | 2138 | //----------------------------------------------------------------------------- |
2139 | // Recover several bits of the cypher stream. This implements (first stages of) | |
2140 | // the algorithm described in "The Dark Side of Security by Obscurity and | |
2141 | // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime" | |
2142 | // (article by Nicolas T. Courtois, 2009) | |
2143 | //----------------------------------------------------------------------------- | |
2144 | void ReaderMifare(bool first_try) | |
2145 | { | |
2146 | // Mifare AUTH | |
2147 | uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b }; | |
2148 | uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }; | |
2149 | static uint8_t mf_nr_ar3; | |
e772353f | 2150 | |
f71f4deb | 2151 | uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE]; |
2152 | uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE]; | |
7bc95e2e | 2153 | |
09ffd16e | 2154 | if (first_try) { |
2155 | iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD); | |
2156 | } | |
2157 | ||
f71f4deb | 2158 | // free eventually allocated BigBuf memory. We want all for tracing. |
2159 | BigBuf_free(); | |
2160 | ||
3000dc4e | 2161 | clear_trace(); |
de77d4ac | 2162 | set_tracing(true); |
e772353f | 2163 | |
1c611bbd | 2164 | byte_t nt_diff = 0; |
6a1f2d82 | 2165 | uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough |
1c611bbd | 2166 | static byte_t par_low = 0; |
de77d4ac | 2167 | bool led_on = true; |
ca4714cd | 2168 | uint8_t uid[10] ={0}; |
1c611bbd | 2169 | uint32_t cuid; |
e772353f | 2170 | |
6a1f2d82 | 2171 | uint32_t nt = 0; |
2ed270a8 | 2172 | uint32_t previous_nt = 0; |
1c611bbd | 2173 | static uint32_t nt_attacked = 0; |
3fe4ff4f | 2174 | byte_t par_list[8] = {0x00}; |
2175 | byte_t ks_list[8] = {0x00}; | |
e772353f | 2176 | |
dfb387bf | 2177 | #define PRNG_SEQUENCE_LENGTH (1 << 16); |
1c611bbd | 2178 | static uint32_t sync_time; |
8c6b2298 | 2179 | static int32_t sync_cycles; |
1c611bbd | 2180 | int catch_up_cycles = 0; |
2181 | int last_catch_up = 0; | |
8c6b2298 | 2182 | uint16_t elapsed_prng_sequences; |
1c611bbd | 2183 | uint16_t consecutive_resyncs = 0; |
2184 | int isOK = 0; | |
e772353f | 2185 | |
1c611bbd | 2186 | if (first_try) { |
1c611bbd | 2187 | mf_nr_ar3 = 0; |
7bc95e2e | 2188 | sync_time = GetCountSspClk() & 0xfffffff8; |
dfb387bf | 2189 | sync_cycles = PRNG_SEQUENCE_LENGTH; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the tag nonces). |
1c611bbd | 2190 | nt_attacked = 0; |
6a1f2d82 | 2191 | par[0] = 0; |
1c611bbd | 2192 | } |
2193 | else { | |
2194 | // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same) | |
1c611bbd | 2195 | mf_nr_ar3++; |
2196 | mf_nr_ar[3] = mf_nr_ar3; | |
6a1f2d82 | 2197 | par[0] = par_low; |
1c611bbd | 2198 | } |
e30c654b | 2199 | |
15c4dc5a | 2200 | LED_A_ON(); |
2201 | LED_B_OFF(); | |
2202 | LED_C_OFF(); | |
1c611bbd | 2203 | |
dc8ba239 | 2204 | |
dfb387bf | 2205 | #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up. |
8c6b2298 | 2206 | #define MAX_SYNC_TRIES 32 |
2207 | #define NUM_DEBUG_INFOS 8 // per strategy | |
2208 | #define MAX_STRATEGY 3 | |
dfb387bf | 2209 | uint16_t unexpected_random = 0; |
2210 | uint16_t sync_tries = 0; | |
2211 | int16_t debug_info_nr = -1; | |
8c6b2298 | 2212 | uint16_t strategy = 0; |
2213 | int32_t debug_info[MAX_STRATEGY][NUM_DEBUG_INFOS]; | |
2214 | uint32_t select_time; | |
2215 | uint32_t halt_time; | |
dc8ba239 | 2216 | |
de77d4ac | 2217 | for(uint16_t i = 0; true; i++) { |
1c611bbd | 2218 | |
dc8ba239 | 2219 | LED_C_ON(); |
1c611bbd | 2220 | WDT_HIT(); |
e30c654b | 2221 | |
1c611bbd | 2222 | // Test if the action was cancelled |
2223 | if(BUTTON_PRESS()) { | |
dc8ba239 | 2224 | isOK = -1; |
1c611bbd | 2225 | break; |
2226 | } | |
2227 | ||
8c6b2298 | 2228 | if (strategy == 2) { |
2229 | // test with additional hlt command | |
2230 | halt_time = 0; | |
2231 | int len = mifare_sendcmd_short(NULL, false, 0x50, 0x00, receivedAnswer, receivedAnswerPar, &halt_time); | |
2232 | if (len && MF_DBGLEVEL >= 3) { | |
2233 | Dbprintf("Unexpected response of %d bytes to hlt command (additional debugging).", len); | |
2234 | } | |
2235 | } | |
2236 | ||
2237 | if (strategy == 3) { | |
2238 | // test with FPGA power off/on | |
2239 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
2240 | SpinDelay(200); | |
2241 | iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD); | |
2242 | SpinDelay(100); | |
2243 | } | |
2244 | ||
c04a4b60 | 2245 | if(!iso14443a_select_card(uid, NULL, &cuid, true, 0, true)) { |
9492e0b0 | 2246 | if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card"); |
1c611bbd | 2247 | continue; |
2248 | } | |
8c6b2298 | 2249 | select_time = GetCountSspClk(); |
1c611bbd | 2250 | |
8c6b2298 | 2251 | elapsed_prng_sequences = 1; |
dfb387bf | 2252 | if (debug_info_nr == -1) { |
2253 | sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles; | |
2254 | catch_up_cycles = 0; | |
1c611bbd | 2255 | |
dfb387bf | 2256 | // if we missed the sync time already, advance to the next nonce repeat |
2257 | while(GetCountSspClk() > sync_time) { | |
8c6b2298 | 2258 | elapsed_prng_sequences++; |
dfb387bf | 2259 | sync_time = (sync_time & 0xfffffff8) + sync_cycles; |
2260 | } | |
e30c654b | 2261 | |
dfb387bf | 2262 | // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked) |
2263 | ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time); | |
2264 | } else { | |
8c6b2298 | 2265 | // collect some information on tag nonces for debugging: |
2266 | #define DEBUG_FIXED_SYNC_CYCLES PRNG_SEQUENCE_LENGTH | |
2267 | if (strategy == 0) { | |
2268 | // nonce distances at fixed time after card select: | |
2269 | sync_time = select_time + DEBUG_FIXED_SYNC_CYCLES; | |
2270 | } else if (strategy == 1) { | |
2271 | // nonce distances at fixed time between authentications: | |
2272 | sync_time = sync_time + DEBUG_FIXED_SYNC_CYCLES; | |
2273 | } else if (strategy == 2) { | |
2274 | // nonce distances at fixed time after halt: | |
2275 | sync_time = halt_time + DEBUG_FIXED_SYNC_CYCLES; | |
2276 | } else { | |
2277 | // nonce_distances at fixed time after power on | |
2278 | sync_time = DEBUG_FIXED_SYNC_CYCLES; | |
2279 | } | |
2280 | ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time); | |
dfb387bf | 2281 | } |
f89c7050 | 2282 | |
1c611bbd | 2283 | // Receive the (4 Byte) "random" nonce |
6a1f2d82 | 2284 | if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) { |
9492e0b0 | 2285 | if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce"); |
1c611bbd | 2286 | continue; |
2287 | } | |
2288 | ||
1c611bbd | 2289 | previous_nt = nt; |
2290 | nt = bytes_to_num(receivedAnswer, 4); | |
2291 | ||
2292 | // Transmit reader nonce with fake par | |
9492e0b0 | 2293 | ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL); |
1c611bbd | 2294 | |
2295 | if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet | |
2296 | int nt_distance = dist_nt(previous_nt, nt); | |
2297 | if (nt_distance == 0) { | |
2298 | nt_attacked = nt; | |
dfb387bf | 2299 | } else { |
dc8ba239 | 2300 | if (nt_distance == -99999) { // invalid nonce received |
dfb387bf | 2301 | unexpected_random++; |
8c6b2298 | 2302 | if (unexpected_random > MAX_UNEXPECTED_RANDOM) { |
dc8ba239 | 2303 | isOK = -3; // Card has an unpredictable PRNG. Give up |
2304 | break; | |
2305 | } else { | |
2306 | continue; // continue trying... | |
2307 | } | |
1c611bbd | 2308 | } |
dfb387bf | 2309 | if (++sync_tries > MAX_SYNC_TRIES) { |
8c6b2298 | 2310 | if (strategy > MAX_STRATEGY || MF_DBGLEVEL < 3) { |
dfb387bf | 2311 | isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly |
2312 | break; | |
2313 | } else { // continue for a while, just to collect some debug info | |
8c6b2298 | 2314 | debug_info[strategy][debug_info_nr] = nt_distance; |
2315 | debug_info_nr++; | |
2316 | if (debug_info_nr == NUM_DEBUG_INFOS) { | |
2317 | strategy++; | |
2318 | debug_info_nr = 0; | |
2319 | } | |
dfb387bf | 2320 | continue; |
2321 | } | |
2322 | } | |
8c6b2298 | 2323 | sync_cycles = (sync_cycles - nt_distance/elapsed_prng_sequences); |
dfb387bf | 2324 | if (sync_cycles <= 0) { |
2325 | sync_cycles += PRNG_SEQUENCE_LENGTH; | |
2326 | } | |
2327 | if (MF_DBGLEVEL >= 3) { | |
8c6b2298 | 2328 | Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles); |
dfb387bf | 2329 | } |
1c611bbd | 2330 | continue; |
2331 | } | |
2332 | } | |
2333 | ||
2334 | if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again... | |
2335 | catch_up_cycles = -dist_nt(nt_attacked, nt); | |
2336 | if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one. | |
2337 | catch_up_cycles = 0; | |
2338 | continue; | |
2339 | } | |
8c6b2298 | 2340 | catch_up_cycles /= elapsed_prng_sequences; |
1c611bbd | 2341 | if (catch_up_cycles == last_catch_up) { |
2342 | consecutive_resyncs++; | |
2343 | } | |
2344 | else { | |
2345 | last_catch_up = catch_up_cycles; | |
2346 | consecutive_resyncs = 0; | |
2347 | } | |
2348 | if (consecutive_resyncs < 3) { | |
9492e0b0 | 2349 | if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs); |
1c611bbd | 2350 | } |
2351 | else { | |
2352 | sync_cycles = sync_cycles + catch_up_cycles; | |
9492e0b0 | 2353 | if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles); |
8c6b2298 | 2354 | last_catch_up = 0; |
2355 | catch_up_cycles = 0; | |
2356 | consecutive_resyncs = 0; | |
1c611bbd | 2357 | } |
2358 | continue; | |
2359 | } | |
2360 | ||
2361 | consecutive_resyncs = 0; | |
2362 | ||
2363 | // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding | |
8c6b2298 | 2364 | if (ReaderReceive(receivedAnswer, receivedAnswerPar)) { |
9492e0b0 | 2365 | catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer |
1c611bbd | 2366 | |
8c6b2298 | 2367 | if (nt_diff == 0) { |
6a1f2d82 | 2368 | par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change |
1c611bbd | 2369 | } |
2370 | ||
2371 | led_on = !led_on; | |
2372 | if(led_on) LED_B_ON(); else LED_B_OFF(); | |
2373 | ||
6a1f2d82 | 2374 | par_list[nt_diff] = SwapBits(par[0], 8); |
1c611bbd | 2375 | ks_list[nt_diff] = receivedAnswer[0] ^ 0x05; |
2376 | ||
2377 | // Test if the information is complete | |
2378 | if (nt_diff == 0x07) { | |
2379 | isOK = 1; | |
2380 | break; | |
2381 | } | |
2382 | ||
2383 | nt_diff = (nt_diff + 1) & 0x07; | |
2384 | mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5); | |
6a1f2d82 | 2385 | par[0] = par_low; |
1c611bbd | 2386 | } else { |
2387 | if (nt_diff == 0 && first_try) | |
2388 | { | |
6a1f2d82 | 2389 | par[0]++; |
dc8ba239 | 2390 | if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK. |
2391 | isOK = -2; | |
2392 | break; | |
2393 | } | |
1c611bbd | 2394 | } else { |
6a1f2d82 | 2395 | par[0] = ((par[0] & 0x1F) + 1) | par_low; |
1c611bbd | 2396 | } |
2397 | } | |
2398 | } | |
2399 | ||
1c611bbd | 2400 | |
2401 | mf_nr_ar[3] &= 0x1F; | |
dfb387bf | 2402 | |
2403 | if (isOK == -4) { | |
2404 | if (MF_DBGLEVEL >= 3) { | |
8c6b2298 | 2405 | for (uint16_t i = 0; i <= MAX_STRATEGY; i++) { |
2406 | for(uint16_t j = 0; j < NUM_DEBUG_INFOS; j++) { | |
2407 | Dbprintf("collected debug info[%d][%d] = %d", i, j, debug_info[i][j]); | |
2408 | } | |
dfb387bf | 2409 | } |
2410 | } | |
2411 | } | |
1c611bbd | 2412 | |
2413 | byte_t buf[28]; | |
2414 | memcpy(buf + 0, uid, 4); | |
2415 | num_to_bytes(nt, 4, buf + 4); | |
2416 | memcpy(buf + 8, par_list, 8); | |
2417 | memcpy(buf + 16, ks_list, 8); | |
2418 | memcpy(buf + 24, mf_nr_ar, 4); | |
2419 | ||
dc8ba239 | 2420 | cmd_send(CMD_ACK, isOK, 0, 0, buf, 28); |
1c611bbd | 2421 | |
2422 | // Thats it... | |
2423 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
2424 | LEDsoff(); | |
7bc95e2e | 2425 | |
de77d4ac | 2426 | set_tracing(false); |
20f9a2a1 | 2427 | } |
1c611bbd | 2428 | |
d2f487af | 2429 | |
b62a5a84 M |
2430 | //----------------------------------------------------------------------------- |
2431 | // MIFARE sniffer. | |
2432 | // | |
2433 | //----------------------------------------------------------------------------- | |
5cd9ec01 M |
2434 | void RAMFUNC SniffMifare(uint8_t param) { |
2435 | // param: | |
2436 | // bit 0 - trigger from first card answer | |
2437 | // bit 1 - trigger from first reader 7-bit request | |
39864b0b M |
2438 | |
2439 | // C(red) A(yellow) B(green) | |
b62a5a84 M |
2440 | LEDsoff(); |
2441 | // init trace buffer | |
3000dc4e | 2442 | clear_trace(); |
de77d4ac | 2443 | set_tracing(true); |
b62a5a84 | 2444 | |
b62a5a84 M |
2445 | // The command (reader -> tag) that we're receiving. |
2446 | // The length of a received command will in most cases be no more than 18 bytes. | |
2447 | // So 32 should be enough! | |
f71f4deb | 2448 | uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE]; |
2449 | uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE]; | |
b62a5a84 | 2450 | // The response (tag -> reader) that we're receiving. |
f71f4deb | 2451 | uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE]; |
2452 | uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE]; | |
b62a5a84 | 2453 | |
09ffd16e | 2454 | iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER); |
2455 | ||
f71f4deb | 2456 | // free eventually allocated BigBuf memory |
2457 | BigBuf_free(); | |
2458 | // allocate the DMA buffer, used to stream samples from the FPGA | |
2459 | uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE); | |
7bc95e2e | 2460 | uint8_t *data = dmaBuf; |
2461 | uint8_t previous_data = 0; | |
5cd9ec01 M |
2462 | int maxDataLen = 0; |
2463 | int dataLen = 0; | |
de77d4ac | 2464 | bool ReaderIsActive = false; |
2465 | bool TagIsActive = false; | |
7bc95e2e | 2466 | |
b62a5a84 | 2467 | // Set up the demodulator for tag -> reader responses. |
6a1f2d82 | 2468 | DemodInit(receivedResponse, receivedResponsePar); |
b62a5a84 M |
2469 | |
2470 | // Set up the demodulator for the reader -> tag commands | |
6a1f2d82 | 2471 | UartInit(receivedCmd, receivedCmdPar); |
b62a5a84 M |
2472 | |
2473 | // Setup for the DMA. | |
7bc95e2e | 2474 | FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer. |
b62a5a84 | 2475 | |
b62a5a84 | 2476 | LED_D_OFF(); |
39864b0b M |
2477 | |
2478 | // init sniffer | |
2479 | MfSniffInit(); | |
b62a5a84 | 2480 | |
b62a5a84 | 2481 | // And now we loop, receiving samples. |
de77d4ac | 2482 | for(uint32_t sniffCounter = 0; true; ) { |
7bc95e2e | 2483 | |
5cd9ec01 | 2484 | if(BUTTON_PRESS()) { |
8ec06f5e | 2485 | DbpString("Canceled by button."); |
7bc95e2e | 2486 | break; |
5cd9ec01 M |
2487 | } |
2488 | ||
b62a5a84 M |
2489 | LED_A_ON(); |
2490 | WDT_HIT(); | |
39864b0b | 2491 | |
7bc95e2e | 2492 | if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time |
2493 | // check if a transaction is completed (timeout after 2000ms). | |
2494 | // if yes, stop the DMA transfer and send what we have so far to the client | |
2495 | if (MfSniffSend(2000)) { | |
2496 | // Reset everything - we missed some sniffed data anyway while the DMA was stopped | |
2497 | sniffCounter = 0; | |
2498 | data = dmaBuf; | |
2499 | maxDataLen = 0; | |
de77d4ac | 2500 | ReaderIsActive = false; |
2501 | TagIsActive = false; | |
7bc95e2e | 2502 | FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer. |
39864b0b | 2503 | } |
39864b0b | 2504 | } |
7bc95e2e | 2505 | |
2506 | int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far | |
2507 | int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred | |
2508 | if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred | |
2509 | dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed | |
2510 | } else { | |
2511 | dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed | |
5cd9ec01 M |
2512 | } |
2513 | // test for length of buffer | |
7bc95e2e | 2514 | if(dataLen > maxDataLen) { // we are more behind than ever... |
2515 | maxDataLen = dataLen; | |
f71f4deb | 2516 | if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) { |
5cd9ec01 | 2517 | Dbprintf("blew circular buffer! dataLen=0x%x", dataLen); |
7bc95e2e | 2518 | break; |
b62a5a84 M |
2519 | } |
2520 | } | |
5cd9ec01 | 2521 | if(dataLen < 1) continue; |
b62a5a84 | 2522 | |
7bc95e2e | 2523 | // primary buffer was stopped ( <-- we lost data! |
5cd9ec01 M |
2524 | if (!AT91C_BASE_PDC_SSC->PDC_RCR) { |
2525 | AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf; | |
2526 | AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE; | |
55acbb2a | 2527 | Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary |
5cd9ec01 M |
2528 | } |
2529 | // secondary buffer sets as primary, secondary buffer was stopped | |
2530 | if (!AT91C_BASE_PDC_SSC->PDC_RNCR) { | |
2531 | AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf; | |
b62a5a84 M |
2532 | AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE; |
2533 | } | |
5cd9ec01 M |
2534 | |
2535 | LED_A_OFF(); | |
b62a5a84 | 2536 | |
7bc95e2e | 2537 | if (sniffCounter & 0x01) { |
b62a5a84 | 2538 | |
7bc95e2e | 2539 | if(!TagIsActive) { // no need to try decoding tag data if the reader is sending |
2540 | uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4); | |
2541 | if(MillerDecoding(readerdata, (sniffCounter-1)*4)) { | |
feb328c9 | 2542 | LED_B_ON(); |
2543 | LED_C_OFF(); | |
2544 | ||
de77d4ac | 2545 | if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, true)) break; |
b62a5a84 | 2546 | |
7bc95e2e | 2547 | /* And ready to receive another command. */ |
05ddb52c | 2548 | UartInit(receivedCmd, receivedCmdPar); |
7bc95e2e | 2549 | |
2550 | /* And also reset the demod code */ | |
2551 | DemodReset(); | |
2552 | } | |
2553 | ReaderIsActive = (Uart.state != STATE_UNSYNCD); | |
2554 | } | |
2555 | ||
2556 | if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending | |
2557 | uint8_t tagdata = (previous_data << 4) | (*data & 0x0F); | |
2558 | if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) { | |
feb328c9 | 2559 | LED_B_OFF(); |
2560 | LED_C_ON(); | |
b62a5a84 | 2561 | |
de77d4ac | 2562 | if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, false)) break; |
39864b0b | 2563 | |
7bc95e2e | 2564 | // And ready to receive another response. |
2565 | DemodReset(); | |
48ece4a7 | 2566 | // And reset the Miller decoder including its (now outdated) input buffer |
2567 | UartInit(receivedCmd, receivedCmdPar); | |
7bc95e2e | 2568 | } |
2569 | TagIsActive = (Demod.state != DEMOD_UNSYNCD); | |
2570 | } | |
b62a5a84 M |
2571 | } |
2572 | ||
7bc95e2e | 2573 | previous_data = *data; |
2574 | sniffCounter++; | |
5cd9ec01 | 2575 | data++; |
d714d3ef | 2576 | if(data == dmaBuf + DMA_BUFFER_SIZE) { |
5cd9ec01 | 2577 | data = dmaBuf; |
b62a5a84 | 2578 | } |
7bc95e2e | 2579 | |
b62a5a84 M |
2580 | } // main cycle |
2581 | ||
8ec06f5e | 2582 | DbpString("COMMAND FINISHED."); |
b62a5a84 | 2583 | |
55acbb2a | 2584 | FpgaDisableSscDma(); |
39864b0b M |
2585 | MfSniffEnd(); |
2586 | ||
7bc95e2e | 2587 | Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len); |
b62a5a84 | 2588 | LEDsoff(); |
3803d529 | 2589 | } |