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Reduced the size of BigBuf to make more room for stack/vars
[proxmark3-svn] / fpga / lo_simulate.v
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1//-----------------------------------------------------------------------------\r
2// The way that we connect things in low-frequency simulation mode. In this\r
3// case just pass everything through to the ARM, which can bit-bang this\r
4// (because it is so slow).\r
5//\r
6// Jonathan Westhues, April 2006\r
7//-----------------------------------------------------------------------------\r
8\r
9module lo_simulate(\r
10 pck0, ck_1356meg, ck_1356megb,\r
11 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
12 adc_d, adc_clk,\r
13 ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
14 cross_hi, cross_lo,\r
15 dbg\r
16);\r
17 input pck0, ck_1356meg, ck_1356megb;\r
18 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
19 input [7:0] adc_d;\r
20 output adc_clk;\r
21 input ssp_dout;\r
22 output ssp_frame, ssp_din, ssp_clk;\r
23 input cross_hi, cross_lo;\r
24 output dbg;\r
25\r
26// No logic, straight through.\r
27assign pwr_oe3 = 1'b0;\r
28assign pwr_oe1 = ssp_dout;\r
29assign pwr_oe2 = ssp_dout;\r
30assign pwr_oe4 = ssp_dout;\r
31assign ssp_clk = cross_lo;\r
32assign pwr_lo = 1'b0;\r
33assign adc_clk = 1'b0;\r
34assign pwr_hi = 1'b0;\r
35assign dbg = cross_lo;\r
36\r
37endmodule\r
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