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1//-----------------------------------------------------------------------------
2// Jonathan Westhues, April 2006
3// iZsh <izsh at fail0verflow.com>, 2014
4//
5// This code is licensed to you under the terms of the GNU GPL, version 2 or,
6// at your option, any later version. See the LICENSE.txt file for the text of
7// the license.
8//-----------------------------------------------------------------------------
9// Routines to load the FPGA image, and then to configure the FPGA's major
10// mode once it is configured.
11//-----------------------------------------------------------------------------
12
13#ifndef __FPGALOADER_H
14#define __FPGALOADER_H
15
16#include <stdint.h>
17#include <stdbool.h>
18
19void FpgaSendCommand(uint16_t cmd, uint16_t v);
20void FpgaWriteConfWord(uint8_t v);
21void FpgaDownloadAndGo(int bitstream_version);
22void FpgaSetupSsc(uint8_t mode);
23void SetupSpi(int mode);
24bool FpgaSetupSscDma(uint8_t *buf, uint16_t sample_count);
25void Fpga_print_status();
26int FpgaGetCurrent();
27#define FpgaDisableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
28#define FpgaEnableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;
29void SetAdcMuxFor(uint32_t whichGpio);
30
31// definitions for multiple FPGA config files support
32#define FPGA_BITSTREAM_LF 1
33#define FPGA_BITSTREAM_HF 2
34
35// Definitions for the FPGA commands.
36#define FPGA_CMD_SET_CONFREG (1<<12)
37#define FPGA_CMD_SET_DIVISOR (2<<12)
38#define FPGA_CMD_SET_USER_BYTE1 (3<<12)
39// Definitions for the FPGA configuration word.
40// LF
41#define FPGA_MAJOR_MODE_LF_ADC (0<<5)
42#define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<5)
43#define FPGA_MAJOR_MODE_LF_PASSTHRU (2<<5)
44// HF
45#define FPGA_MAJOR_MODE_HF_READER_TX (0<<5)
46#define FPGA_MAJOR_MODE_HF_READER_RX_XCORR (1<<5)
47#define FPGA_MAJOR_MODE_HF_SIMULATOR (2<<5)
48#define FPGA_MAJOR_MODE_HF_ISO14443A (3<<5)
49#define FPGA_MAJOR_MODE_HF_SNOOP (4<<5)
50// BOTH
51#define FPGA_MAJOR_MODE_OFF (7<<5)
52// Options for LF_ADC
53#define FPGA_LF_ADC_READER_FIELD (1<<0)
54// Options for LF_EDGE_DETECT
55#define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD FPGA_CMD_SET_USER_BYTE1
56#define FPGA_LF_EDGE_DETECT_READER_FIELD (1<<0)
57#define FPGA_LF_EDGE_DETECT_TOGGLE_MODE (1<<1)
58// Options for the HF reader, tx to tag
59#define FPGA_HF_READER_TX_SHALLOW_MOD (1<<0)
60// Options for the HF reader, correlating against rx from tag
61#define FPGA_HF_READER_RX_XCORR_848_KHZ (1<<0)
62#define FPGA_HF_READER_RX_XCORR_SNOOP (1<<1)
63#define FPGA_HF_READER_RX_XCORR_QUARTER_FREQ (1<<2)
64// Options for the HF simulated tag, how to modulate
65#define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0)
66#define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0)
67#define FPGA_HF_SIMULATOR_MODULATE_212K (2<<0)
68#define FPGA_HF_SIMULATOR_MODULATE_424K (4<<0)
69#define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 0x5//101
70
71// Options for ISO14443A
72#define FPGA_HF_ISO14443A_SNIFFER (0<<0)
73#define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0)
74#define FPGA_HF_ISO14443A_TAGSIM_MOD (2<<0)
75#define FPGA_HF_ISO14443A_READER_LISTEN (3<<0)
76#define FPGA_HF_ISO14443A_READER_MOD (4<<0)
77
78#endif
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